OV - attention-gnr-512 - Loop 52

	Loop Id: 52	Module: attention-gnr-512	Source: attention_v2.cpp:163-163 [...]	Coverage: 1.47%

0x403ea0 CMP	$0x270,%RDX

0x403ea7 JB	4040d0

0x403ead XOR	%EAX,%EAX

0x403eaf VPBROADCASTQ	0x9408(%RIP),%YMM3

0x403eb8 VPBROADCASTQ	0x9407(%RIP),%YMM4

0x403ec1 VPBROADCASTQ	0x9406(%RIP),%YMM5

0x403eca VPBROADCASTQ	0x9405(%RIP),%YMM6

0x403ed3 NOPW	%CS:(%RAX,%RAX,1)

  (53) 0x403ee0 VPBROADCASTQ	%R13,%YMM1

  (53) 0x403ee6 MOV	0x3d8(%RSP,%RAX,1),%R13

  (53) 0x403eee VMOVDQU	0x3c0(%RSP,%RAX,1),%YMM0

  (53) 0x403ef7 VPSRLQ	$0x1,%YMM0,%YMM2

  (53) 0x403efc VPAND	%YMM3,%YMM2,%YMM2

  (53) 0x403f00 VPBLENDD	$-0x40,%YMM1,%YMM0,%YMM1

  (53) 0x403f06 VPSRLQ	$0x1,%YMM1,%YMM1

  (53) 0x403f0b VPERMQ	$-0x6d,%YMM1,%YMM1

  (53) 0x403f11 VPAND	%YMM4,%YMM1,%YMM1

  (53) 0x403f15 VPTERNLOGQ	$0x56,0x1020(%RSP,%RAX,1),%YMM2,%YMM1

  (53) 0x403f21 VPTESTMQ	%YMM5,%YMM0,%K1

  (53) 0x403f27 VPXORQ	%YMM6,%YMM1,%YMM1{%K1}

  (53) 0x403f2d VMOVDQU	%YMM1,0x3b8(%RSP,%RAX,1)

  (53) 0x403f36 ADD	$0x20,%RAX

  (53) 0x403f3a CMP	$0x700,%RAX

  (53) 0x403f40 JNE	403ee0

0x403f42 MOV	0xac8(%RSP),%RAX

0x403f4a VMOVDQU	0xac0(%RSP),%XMM1

0x403f53 VPSRLQ	$0x1,%XMM1,%XMM2

0x403f58 VEXTRACTI128	$0x1,%YMM0,%XMM0

0x403f5e VPUNPCKHQDQ	0xac0(%RSP){1to2},%XMM0,%XMM0

0x403f69 VPANDQ	0x934d(%RIP){1to2},%XMM2,%XMM2

0x403f73 VPSRLQ	$0x1,%XMM0,%XMM0

0x403f78 VPANDQ	0x9346(%RIP){1to2},%XMM0,%XMM0

0x403f82 VPTERNLOGQ	$0x56,0x1720(%RSP),%XMM2,%XMM0

0x403f8e VPTESTMQ	0x9338(%RIP){1to0},%XMM1,%K1

0x403f98 VPXORQ	0x9336(%RIP){1to2},%XMM0,%XMM0{%K1}

0x403fa2 VMOVDQU	%XMM0,0xab8(%RSP)

0x403fab MOV	0xad0(%RSP),%ECX

0x403fb2 MOV	%ECX,%EDX

0x403fb4 SHR	$0x1,%EDX

0x403fb6 AND	$0x3fffffff,%EDX

0x403fbc SHR	$0x1,%RAX

0x403fbf MOV	$0x7fffffffc0000000,%R8

0x403fc9 AND	%R8,%RAX

0x403fcc ADD	%RDX,%RAX

0x403fcf XOR	0x1730(%RSP),%RAX

0x403fd7 AND	$0x1,%ECX

0x403fda NEG	%ECX

0x403fdc AND	%ESI,%ECX

0x403fde XOR	%RAX,%RCX

0x403fe1 MOV	%RCX,0xac8(%RSP)

0x403fe9 XOR	%EAX,%EAX

0x403feb VPBROADCASTQ	0x92cb(%RIP),%ZMM3

0x403ff5 VPBROADCASTQ	0x92c9(%RIP),%ZMM4

0x403fff VPBROADCASTQ	0x92c7(%RIP),%ZMM5

0x404009 VPBROADCASTQ	0x92c5(%RIP),%ZMM6

0x404013 NOPW	%CS:(%RAX,%RAX,1)

  (54) 0x404020 VMOVDQU64	0xad8(%RSP,%RAX,8),%ZMM0

  (54) 0x40402b VPSRLQ	$0x1,%ZMM0,%ZMM1

  (54) 0x404032 VPANDQ	%ZMM3,%ZMM1,%ZMM1

  (54) 0x404038 VPSRLQ	$0x1,0xad0(%RSP,%RAX,8),%ZMM2

  (54) 0x404044 VPANDQ	%ZMM4,%ZMM2,%ZMM2

  (54) 0x40404a VPTERNLOGQ	$0x56,0x3b8(%RSP,%RAX,8),%ZMM1,%ZMM2

  (54) 0x404056 VPTESTMQ	%ZMM5,%ZMM0,%K1

  (54) 0x40405c VPXORQ	%ZMM6,%ZMM2,%ZMM2{%K1}

  (54) 0x404062 VMOVDQU64	%ZMM2,0xad0(%RSP,%RAX,8)

  (54) 0x40406d CMP	$0x17f,%RAX

  (54) 0x404073 JA	4040e0

  (54) 0x404075 VMOVDQU64	0xb18(%RSP,%RAX,8),%ZMM0

  (54) 0x404080 VPSRLQ	$0x1,%ZMM0,%ZMM1

  (54) 0x404087 VPANDQ	%ZMM3,%ZMM1,%ZMM1

  (54) 0x40408d VPSRLQ	$0x1,0xb10(%RSP,%RAX,8),%ZMM2

  (54) 0x404099 VPANDQ	%ZMM4,%ZMM2,%ZMM2

  (54) 0x40409f VPTERNLOGQ	$0x56,0x3f8(%RSP,%RAX,8),%ZMM1,%ZMM2

  (54) 0x4040ab VPTESTMQ	%ZMM5,%ZMM0,%K1

  (54) 0x4040b1 VPXORQ	%ZMM6,%ZMM2,%ZMM2{%K1}

  (54) 0x4040b7 VMOVDQU64	%ZMM2,0xb10(%RSP,%RAX,8)

  (54) 0x4040c2 ADD	$0x10,%RAX

  (54) 0x4040c6 JMP	404020

0x4040d0 MOV	0x3b8(%RSP,%RDX,8),%RAX

0x4040d8 INC	%RDX

0x4040db JMP	404188

0x4040e0 VMOVDQU	0x1718(%RSP),%YMM0

0x4040e9 VPSRLQ	$0x1,%YMM0,%YMM1

0x4040ee VPSRLQ	$0x1,0x1710(%RSP),%YMM2

0x4040fa VPANDQ	0x91bc(%RIP){1to4},%YMM1,%YMM1

0x404104 VPANDQ	0x91ba(%RIP){1to4},%YMM2,%YMM2

0x40410e VPTERNLOGQ	$0x56,0xff8(%RSP),%YMM1,%YMM2

0x40411a VPTESTMQ	0x91ac(%RIP){1to0},%YMM0,%K1

0x404124 VPXORQ	0x91aa(%RIP){1to4},%YMM2,%YMM2{%K1}

0x40412e VMOVDQU	%YMM2,0x1710(%RSP)

0x404137 MOV	0x1730(%RSP),%RCX

0x40413f MOV	0x3b8(%RSP),%RAX

0x404147 MOV	%EAX,%EDX

0x404149 SHR	$0x1,%EDX

0x40414b AND	$0x3fffffff,%EDX

0x404151 SHR	$0x1,%RCX

0x404154 MOV	$0x7fffffffc0000000,%R8

0x40415e AND	%R8,%RCX

0x404161 ADD	%RDX,%RCX

0x404164 XOR	0x1018(%RSP),%RCX

0x40416c MOV	%EAX,%EDX

0x40416e AND	$0x1,%EDX

0x404171 NEG	%EDX

0x404173 AND	%ESI,%EDX

0x404175 XOR	%RCX,%RDX

0x404178 MOV	%RDX,0x1730(%RSP)

0x404180 MOV	$0x1,%EDX

0x404185 MOV	%RAX,%R13

0x404188 MOV	%RAX,%RCX

0x40418b SHR	$0xb,%RCX

0x40418f MOV	%ECX,%ECX

0x404191 XOR	%RAX,%RCX

0x404194 MOV	%ECX,%EAX

0x404196 SAL	$0x7,%EAX

0x404199 AND	$-0x62d3a980,%EAX

0x40419e XOR	%RCX,%RAX

0x4041a1 MOV	%EAX,%ECX

0x4041a3 SAL	$0xf,%ECX

0x4041a6 AND	$-0x103a0000,%ECX

0x4041ac XOR	%RAX,%RCX

0x4041af MOV	%RCX,%RAX

0x4041b2 SHR	$0x12,%RAX

0x4041b6 XOR	%RCX,%RAX

0x4041b9 VCVTUSI2SS	%RAX,%XMM7,%XMM0

0x4041bf VMULSS	0x8ea5(%RIP),%XMM0,%XMM0

0x4041c7 VUCOMISS	0x8e99(%RIP),%XMM0

0x4041cf JAE	4041ee

0x4041d1 VMOVSS	%XMM0,(%R14,%R9,4)

0x4041d7 LEA	0x1(%R9),%RAX

0x4041db CMP	0x280(%RSP),%R9

0x4041e3 MOV	%RAX,%R9

0x4041e6 JNE	403ea0

0x4041ee VXORPS	%XMM1,%XMM1,%XMM1

0x4041f2 VMOVSS	0x8e6e(%RIP),%XMM0

0x4041fa MOV	%RDX,0x30(%RSP)

0x4041ff MOV	%R9,0x38(%RSP)

0x404204 VZEROUPPER

0x404207 CALL	406ac0 <nextafterf>

0x40420c MOV	0x38(%RSP),%R9

0x404211 MOV	0x30(%RSP),%RDX

0x404216 MOV	0xb8(%RSP),%RDI

0x40421e MOV	$-0x66f74f21,%ESI

0x404223 JMP	4041d1

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath: 1661 - 1661

--------------------------------------------------------------------------------

1661:   { return __builtin_nextafterf(__x, __y); }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc: 401 - 3370

--------------------------------------------------------------------------------

401:       for (size_t __k = 0; __k < (__n - __m); ++__k)

402:         {

403: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

404: 			   | (_M_x[__k + 1] & __lower_mask));

405: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

406: 		       ^ ((__y & 0x01) ? __a : 0));

407:         }

408:

409:       for (size_t __k = (__n - __m); __k < (__n - 1); ++__k)

410: 	{

411: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

412: 			   | (_M_x[__k + 1] & __lower_mask));

413: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

414: 		       ^ ((__y & 0x01) ? __a : 0));

415: 	}

416:

417:       _UIntType __y = ((_M_x[__n - 1] & __upper_mask)

418: 		       | (_M_x[0] & __lower_mask));

419:       _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1)

420: 		       ^ ((__y & 0x01) ? __a : 0));

[...]

455:       if (_M_p >= state_size)

456: 	_M_gen_rand();

457:

458:       // Calculate o(x(i)).

459:       result_type __z = _M_x[_M_p++];

460:       __z ^= (__z >> __u) & __d;

461:       __z ^= (__z << __s) & __b;

462:       __z ^= (__z << __t) & __c;

463:       __z ^= (__z >> __l);

[...]

3366: 	  __sum += _RealType(__urng() - __urng.min()) * __tmp;

3367: 	  __tmp *= __r;

3368: 	}

3369:       __ret = __sum / __tmp;

3370:       if (__builtin_expect(__ret >= _RealType(1), 0))

/home/eoseret/llm-attention/attention_v2.cpp: 163 - 163

--------------------------------------------------------------------------------

163:       for (size_t i = 0; i < elemsX; ++i) h_X[i] = dist(rng);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.13
CQA speedup if FP arith vectorized	1.91
CQA speedup if fully vectorized	7.53
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.58
Bottlenecks	micro-operation queue,
Function	main
Source	cmath:1661-1661,random.tcc:404-406,random.tcc:412-414,random.tcc:417-420,random.tcc:455-455,random.tcc:459-463,random.tcc:3366-3366,random.tcc:3369-3370,attention_v2.cpp:163-163
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	19.17
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	10.01
CQA cycles if fully vectorized	2.54
Front-end cycles	19.17
P0 cycles	11.93
P1 cycles	12.13
P2 cycles	12.00
P3 cycles	12.00
P4 cycles	4.00
P5 cycles	11.93
P6 cycles	12.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	12.00
P11 cycles	12.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	105.00
Nb uops	115.00
Nb loads	36.00
Nb stores	7.00
Nb stack references	15.00
FLOP/cycle	0.05
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.17
Bytes prefetched	0.00
Bytes loaded	360.00
Bytes stored	84.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	33.33
Vectorization ratio load	44.83
Vectorization ratio store	28.57
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	35.42
Vector-efficiency ratio all	18.95
Vector-efficiency ratio load	23.28
Vector-efficiency ratio store	18.75
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	19.40

Metric	Value
CQA speedup if no scalar integer	2.13
CQA speedup if FP arith vectorized	1.91
CQA speedup if fully vectorized	7.53
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.58
Bottlenecks	micro-operation queue,
Function	main
Source	cmath:1661-1661,random.tcc:404-406,random.tcc:412-414,random.tcc:417-420,random.tcc:455-455,random.tcc:459-463,random.tcc:3366-3366,random.tcc:3369-3370,attention_v2.cpp:163-163
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	19.17
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	10.01
CQA cycles if fully vectorized	2.54
Front-end cycles	19.17
P0 cycles	11.93
P1 cycles	12.13
P2 cycles	12.00
P3 cycles	12.00
P4 cycles	4.00
P5 cycles	11.93
P6 cycles	12.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	12.00
P11 cycles	12.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	105.00
Nb uops	115.00
Nb loads	36.00
Nb stores	7.00
Nb stack references	15.00
FLOP/cycle	0.05
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.17
Bytes prefetched	0.00
Bytes loaded	360.00
Bytes stored	84.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	33.33
Vectorization ratio load	44.83
Vectorization ratio store	28.57
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	35.42
Vector-efficiency ratio all	18.95
Vector-efficiency ratio load	23.28
Vector-efficiency ratio store	18.75
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	19.40

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:163-163
Module	attention-gnr-512

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:401-420,455-463,3366-3370
/home/eoseret/llm-attention/attention_v2.cpp:163

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 5 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.17 to 9.00 cycles (2.13x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 18% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 19.17 to 2.54 cycles (7.53x speedup).

Details

33% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

44% of SSE/AVX loads are used in vector version.
28% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
35% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

nextafterf: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTUSI2SS: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366
VPSRLQ: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:413
VPTERNLOGQ: 2 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:405
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:413
VPTESTMQ: 2 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:406
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:414
VUCOMISS: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370
VZEROUPPER: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 360 bytes (90 single precision FP elements). The binary loop is storing 84 bytes (21 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	105
nb uops	115
loop length	625
used x86 registers	10
used mmx registers	0
used xmm registers	4
used ymm registers	7
used zmm registers	4
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.17 cycles
front end	19.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	11.93	12.13	12.00	12.00	4.00	11.93	12.00	4.00	4.00	4.00	12.00	12.00
cycles	11.93	12.13	12.00	12.00	4.00	11.93	12.00	4.00	4.00	4.00	12.00	12.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.17
Dispatch	12.13
Overall L1	19.17

Vectorization ratios

INT

all	34%
load	50%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	34%

all	20%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	33%
load	44%
store	28%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	35%

Vector efficiency ratios

INT

all	19%
load	25%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	19%

all	10%
load	6%
store	6%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	18%
load	23%
store	18%
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 19.17 cycles. At this rate:

9% of peak load performance is reached (18.78 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.38 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 19.17 to 12.13 cycles (1.58x speedup).

ASM code

In the binary file, the address of the loop is: 403ea0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
CMP $0x270,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 4040d0 <main+0xe10>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ 0x9408(%RIP),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x9407(%RIP),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x9406(%RIP),%YMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x9405(%RIP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xac8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVDQU 0xac0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VEXTRACTI128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPUNPCKHQDQ 0xac0(%RSP){1to2},%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	scal (12.5%)
VPANDQ 0x934d(%RIP){1to2},%XMM2,%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VPANDQ 0x9346(%RIP){1to2},%XMM0,%XMM0	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPTERNLOGQ $0x56,0x1720(%RSP),%XMM2,%XMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPTESTMQ 0x9338(%RIP){1to0},%XMM1,%K1	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (25.0%)
VPXORQ 0x9336(%RIP){1to2},%XMM0,%XMM0{%K1}	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVDQU %XMM0,0xab8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0xad0(%RSP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $0x3fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x1,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV $0x7fffffffc0000000,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
AND %R8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR 0x1730(%RSP),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	N/A
AND $0x1,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
NEG %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
AND %ESI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RCX,0xac8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ 0x92cb(%RIP),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x92c9(%RIP),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x92c7(%RIP),%ZMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x92c5(%RIP),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x3b8(%RSP,%RDX,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 404188 <main+0xec8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VMOVDQU 0x1718(%RSP),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VPSRLQ $0x1,%YMM0,%YMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (50.0%)
VPSRLQ $0x1,0x1710(%RSP),%YMM2	2	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	2-4	0.50	vect (50.0%)
VPANDQ 0x91bc(%RIP){1to4},%YMM1,%YMM1	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPANDQ 0x91ba(%RIP){1to4},%YMM2,%YMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPTERNLOGQ $0x56,0xff8(%RSP),%YMM1,%YMM2	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.38	vect (50.0%)
VPTESTMQ 0x91ac(%RIP){1to0},%YMM0,%K1	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (50.0%)
VPXORQ 0x91aa(%RIP){1to4},%YMM2,%YMM2{%K1}	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.40	vect (50.0%)
VMOVDQU %YMM2,0x1710(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
MOV 0x1730(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x3b8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $0x3fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x1,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV $0x7fffffffc0000000,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
AND %R8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
XOR 0x1018(%RSP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	scal (12.5%)
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
NEG %EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %ESI,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RDX,0x1730(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0xb,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x7,%EAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $-0x62d3a980,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0xf,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
AND $-0x103a0000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x12,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
XOR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VCVTUSI2SS %RAX,%XMM7,%XMM0	3	0.50	0.50	0	0	0	2	0	0	0	0	0	0	8	2	scal (12.5%)
VMULSS 0x8ea5(%RIP),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VUCOMISS 0x8e99(%RIP),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (6.3%)
JAE 4041ee <main+0xf2e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSS %XMM0,(%R14,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x1(%R9),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP 0x280(%RSP),%R9	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 403ea0 <main+0xbe0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSS 0x8e6e(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %RDX,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ac0 <nextafterf>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x38(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xb8(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV $-0x66f74f21,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JMP 4041d1 <main+0xf11>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

Function	main
Source file and lines	attention_v2.cpp:163-163
Module	attention-gnr-512

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:401-420,455-463,3366-3370
/home/eoseret/llm-attention/attention_v2.cpp:163

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.17 to 9.00 cycles (2.13x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

33% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

44% of SSE/AVX loads are used in vector version.
28% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
35% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

CALL instructions

Detected function call instructions.

Details

nextafterf: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTUSI2SS: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366
VPSRLQ: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:413
VPTERNLOGQ: 2 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:405
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:413
VPTESTMQ: 2 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:406
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:414
VUCOMISS: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370
VZEROUPPER: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 360 bytes (90 single precision FP elements). The binary loop is storing 84 bytes (21 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	105
nb uops	115
loop length	625
used x86 registers	10
used mmx registers	0
used xmm registers	4
used ymm registers	7
used zmm registers	4
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.17 cycles
front end	19.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	11.93	12.13	12.00	12.00	4.00	11.93	12.00	4.00	4.00	4.00	12.00	12.00
cycles	11.93	12.13	12.00	12.00	4.00	11.93	12.00	4.00	4.00	4.00	12.00	12.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.17
Dispatch	12.13
Overall L1	19.17

Vectorization ratios

INT

all	34%
load	50%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	34%

all	20%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	33%
load	44%
store	28%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	35%

Vector efficiency ratios

INT

all	19%
load	25%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	19%

all	10%
load	6%
store	6%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	18%
load	23%
store	18%
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 19.17 cycles. At this rate:

9% of peak load performance is reached (18.78 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.38 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 403ea0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
CMP $0x270,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 4040d0 <main+0xe10>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ 0x9408(%RIP),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x9407(%RIP),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x9406(%RIP),%YMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x9405(%RIP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xac8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVDQU 0xac0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VEXTRACTI128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPUNPCKHQDQ 0xac0(%RSP){1to2},%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	scal (12.5%)
VPANDQ 0x934d(%RIP){1to2},%XMM2,%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VPANDQ 0x9346(%RIP){1to2},%XMM0,%XMM0	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPTERNLOGQ $0x56,0x1720(%RSP),%XMM2,%XMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPTESTMQ 0x9338(%RIP){1to0},%XMM1,%K1	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (25.0%)
VPXORQ 0x9336(%RIP){1to2},%XMM0,%XMM0{%K1}	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVDQU %XMM0,0xab8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0xad0(%RSP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $0x3fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x1,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV $0x7fffffffc0000000,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
AND %R8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR 0x1730(%RSP),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	N/A
AND $0x1,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
NEG %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
AND %ESI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RCX,0xac8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ 0x92cb(%RIP),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x92c9(%RIP),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x92c7(%RIP),%ZMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x92c5(%RIP),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x3b8(%RSP,%RDX,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 404188 <main+0xec8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VMOVDQU 0x1718(%RSP),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VPSRLQ $0x1,%YMM0,%YMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (50.0%)
VPSRLQ $0x1,0x1710(%RSP),%YMM2	2	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	2-4	0.50	vect (50.0%)
VPANDQ 0x91bc(%RIP){1to4},%YMM1,%YMM1	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPANDQ 0x91ba(%RIP){1to4},%YMM2,%YMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPTERNLOGQ $0x56,0xff8(%RSP),%YMM1,%YMM2	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.38	vect (50.0%)
VPTESTMQ 0x91ac(%RIP){1to0},%YMM0,%K1	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (50.0%)
VPXORQ 0x91aa(%RIP){1to4},%YMM2,%YMM2{%K1}	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.40	vect (50.0%)
VMOVDQU %YMM2,0x1710(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
MOV 0x1730(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x3b8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $0x3fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x1,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV $0x7fffffffc0000000,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
AND %R8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
XOR 0x1018(%RSP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	scal (12.5%)
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
NEG %EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %ESI,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RDX,0x1730(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0xb,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x7,%EAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $-0x62d3a980,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0xf,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
AND $-0x103a0000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x12,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
XOR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VCVTUSI2SS %RAX,%XMM7,%XMM0	3	0.50	0.50	0	0	0	2	0	0	0	0	0	0	8	2	scal (12.5%)
VMULSS 0x8ea5(%RIP),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VUCOMISS 0x8e99(%RIP),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (6.3%)
JAE 4041ee <main+0xf2e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSS %XMM0,(%R14,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x1(%R9),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP 0x280(%RSP),%R9	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 403ea0 <main+0xbe0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSS 0x8e6e(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %RDX,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ac0 <nextafterf>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x38(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xb8(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV $-0x66f74f21,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JMP 4041d1 <main+0xf11>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code