OV - attention-gnr-512 - Loop 47

	Loop Id: 47	Module: attention-gnr-512	Source: attention_v2.cpp:164-167 [...]	Coverage: 0.64%

0x404280 CMP	$0x270,%RDX

0x404287 JB	4044b0

0x40428d XOR	%EAX,%EAX

0x40428f VPBROADCASTQ	0x9028(%RIP),%YMM3

0x404298 VPBROADCASTQ	0x9027(%RIP),%YMM4

0x4042a1 VPBROADCASTQ	0x9026(%RIP),%YMM5

0x4042aa VPBROADCASTQ	0x9025(%RIP),%YMM6

0x4042b3 NOPW	%CS:(%RAX,%RAX,1)

  (50) 0x4042c0 VPBROADCASTQ	%R13,%YMM1

  (50) 0x4042c6 MOV	0x3d8(%RSP,%RAX,1),%R13

  (50) 0x4042ce VMOVDQU	0x3c0(%RSP,%RAX,1),%YMM0

  (50) 0x4042d7 VPSRLQ	$0x1,%YMM0,%YMM2

  (50) 0x4042dc VPAND	%YMM3,%YMM2,%YMM2

  (50) 0x4042e0 VPBLENDD	$-0x40,%YMM1,%YMM0,%YMM1

  (50) 0x4042e6 VPSRLQ	$0x1,%YMM1,%YMM1

  (50) 0x4042eb VPERMQ	$-0x6d,%YMM1,%YMM1

  (50) 0x4042f1 VPAND	%YMM4,%YMM1,%YMM1

  (50) 0x4042f5 VPTERNLOGQ	$0x56,0x1020(%RSP,%RAX,1),%YMM2,%YMM1

  (50) 0x404301 VPTESTMQ	%YMM5,%YMM0,%K1

  (50) 0x404307 VPXORQ	%YMM6,%YMM1,%YMM1{%K1}

  (50) 0x40430d VMOVDQU	%YMM1,0x3b8(%RSP,%RAX,1)

  (50) 0x404316 ADD	$0x20,%RAX

  (50) 0x40431a CMP	$0x700,%RAX

  (50) 0x404320 JNE	4042c0

0x404322 MOV	0xac8(%RSP),%RAX

0x40432a VMOVDQU	0xac0(%RSP),%XMM1

0x404333 VPSRLQ	$0x1,%XMM1,%XMM2

0x404338 VEXTRACTI128	$0x1,%YMM0,%XMM0

0x40433e VPUNPCKHQDQ	0xac0(%RSP){1to2},%XMM0,%XMM0

0x404349 VPANDQ	0x8f6d(%RIP){1to2},%XMM2,%XMM2

0x404353 VPSRLQ	$0x1,%XMM0,%XMM0

0x404358 VPANDQ	0x8f66(%RIP){1to2},%XMM0,%XMM0

0x404362 VPTERNLOGQ	$0x56,0x1720(%RSP),%XMM2,%XMM0

0x40436e VPTESTMQ	0x8f58(%RIP){1to0},%XMM1,%K1

0x404378 VPXORQ	0x8f56(%RIP){1to2},%XMM0,%XMM0{%K1}

0x404382 VMOVDQU	%XMM0,0xab8(%RSP)

0x40438b MOV	0xad0(%RSP),%ECX

0x404392 MOV	%ECX,%EDX

0x404394 SHR	$0x1,%EDX

0x404396 AND	$0x3fffffff,%EDX

0x40439c SHR	$0x1,%RAX

0x40439f MOV	$0x7fffffffc0000000,%R8

0x4043a9 AND	%R8,%RAX

0x4043ac ADD	%RDX,%RAX

0x4043af XOR	0x1730(%RSP),%RAX

0x4043b7 AND	$0x1,%ECX

0x4043ba NEG	%ECX

0x4043bc AND	%ESI,%ECX

0x4043be XOR	%RAX,%RCX

0x4043c1 MOV	%RCX,0xac8(%RSP)

0x4043c9 XOR	%EAX,%EAX

0x4043cb VPBROADCASTQ	0x8eeb(%RIP),%ZMM3

0x4043d5 VPBROADCASTQ	0x8ee9(%RIP),%ZMM4

0x4043df VPBROADCASTQ	0x8ee7(%RIP),%ZMM5

0x4043e9 VPBROADCASTQ	0x8ee5(%RIP),%ZMM6

0x4043f3 NOPW	%CS:(%RAX,%RAX,1)

  (51) 0x404400 VMOVDQU64	0xad8(%RSP,%RAX,8),%ZMM0

  (51) 0x40440b VPSRLQ	$0x1,%ZMM0,%ZMM1

  (51) 0x404412 VPANDQ	%ZMM3,%ZMM1,%ZMM1

  (51) 0x404418 VPSRLQ	$0x1,0xad0(%RSP,%RAX,8),%ZMM2

  (51) 0x404424 VPANDQ	%ZMM4,%ZMM2,%ZMM2

  (51) 0x40442a VPTERNLOGQ	$0x56,0x3b8(%RSP,%RAX,8),%ZMM1,%ZMM2

  (51) 0x404436 VPTESTMQ	%ZMM5,%ZMM0,%K1

  (51) 0x40443c VPXORQ	%ZMM6,%ZMM2,%ZMM2{%K1}

  (51) 0x404442 VMOVDQU64	%ZMM2,0xad0(%RSP,%RAX,8)

  (51) 0x40444d CMP	$0x17f,%RAX

  (51) 0x404453 JA	4044c0

  (51) 0x404455 VMOVDQU64	0xb18(%RSP,%RAX,8),%ZMM0

  (51) 0x404460 VPSRLQ	$0x1,%ZMM0,%ZMM1

  (51) 0x404467 VPANDQ	%ZMM3,%ZMM1,%ZMM1

  (51) 0x40446d VPSRLQ	$0x1,0xb10(%RSP,%RAX,8),%ZMM2

  (51) 0x404479 VPANDQ	%ZMM4,%ZMM2,%ZMM2

  (51) 0x40447f VPTERNLOGQ	$0x56,0x3f8(%RSP,%RAX,8),%ZMM1,%ZMM2

  (51) 0x40448b VPTESTMQ	%ZMM5,%ZMM0,%K1

  (51) 0x404491 VPXORQ	%ZMM6,%ZMM2,%ZMM2{%K1}

  (51) 0x404497 VMOVDQU64	%ZMM2,0xb10(%RSP,%RAX,8)

  (51) 0x4044a2 ADD	$0x10,%RAX

  (51) 0x4044a6 JMP	404400

0x4044b0 MOV	0x3b8(%RSP,%RDX,8),%RAX

0x4044b8 INC	%RDX

0x4044bb JMP	404568

0x4044c0 VMOVDQU	0x1718(%RSP),%YMM0

0x4044c9 VPSRLQ	$0x1,%YMM0,%YMM1

0x4044ce VPSRLQ	$0x1,0x1710(%RSP),%YMM2

0x4044da VPANDQ	0x8ddc(%RIP){1to4},%YMM1,%YMM1

0x4044e4 VPANDQ	0x8dda(%RIP){1to4},%YMM2,%YMM2

0x4044ee VPTERNLOGQ	$0x56,0xff8(%RSP),%YMM1,%YMM2

0x4044fa VPTESTMQ	0x8dcc(%RIP){1to0},%YMM0,%K1

0x404504 VPXORQ	0x8dca(%RIP){1to4},%YMM2,%YMM2{%K1}

0x40450e VMOVDQU	%YMM2,0x1710(%RSP)

0x404517 MOV	0x1730(%RSP),%RCX

0x40451f MOV	0x3b8(%RSP),%RAX

0x404527 MOV	%EAX,%EDX

0x404529 SHR	$0x1,%EDX

0x40452b AND	$0x3fffffff,%EDX

0x404531 SHR	$0x1,%RCX

0x404534 MOV	$0x7fffffffc0000000,%R8

0x40453e AND	%R8,%RCX

0x404541 ADD	%RDX,%RCX

0x404544 XOR	0x1018(%RSP),%RCX

0x40454c MOV	%EAX,%EDX

0x40454e AND	$0x1,%EDX

0x404551 NEG	%EDX

0x404553 AND	%ESI,%EDX

0x404555 XOR	%RCX,%RDX

0x404558 MOV	%RDX,0x1730(%RSP)

0x404560 MOV	$0x1,%EDX

0x404565 MOV	%RAX,%R13

0x404568 MOV	%RAX,%RCX

0x40456b SHR	$0xb,%RCX

0x40456f MOV	%ECX,%ECX

0x404571 XOR	%RAX,%RCX

0x404574 MOV	%ECX,%EAX

0x404576 SAL	$0x7,%EAX

0x404579 AND	$-0x62d3a980,%EAX

0x40457e XOR	%RCX,%RAX

0x404581 MOV	%EAX,%ECX

0x404583 SAL	$0xf,%ECX

0x404586 AND	$-0x103a0000,%ECX

0x40458c XOR	%RAX,%RCX

0x40458f MOV	%RCX,%RAX

0x404592 SHR	$0x12,%RAX

0x404596 XOR	%RCX,%RAX

0x404599 VCVTUSI2SS	%RAX,%XMM7,%XMM0

0x40459f VMULSS	0x8ac5(%RIP),%XMM0,%XMM0

0x4045a7 VUCOMISS	0x8ab9(%RIP),%XMM0

0x4045af JAE	40489a

0x4045b5 MOV	0x58(%RSP),%RAX

0x4045ba VMOVSS	%XMM0,(%RAX,%R9,4)

0x4045c0 CMP	$0x270,%RDX

0x4045c7 JB	4048f0

0x4045cd XOR	%EAX,%EAX

0x4045cf VPBROADCASTQ	0x8ce8(%RIP),%YMM3

0x4045d8 VPBROADCASTQ	0x8ce7(%RIP),%YMM4

0x4045e1 VPBROADCASTQ	0x8ce6(%RIP),%YMM5

0x4045ea VPBROADCASTQ	0x8ce5(%RIP),%YMM6

0x4045f3 NOPW	%CS:(%RAX,%RAX,1)

  (45) 0x404600 VPBROADCASTQ	%R13,%YMM1

  (45) 0x404606 MOV	0x3d8(%RSP,%RAX,1),%R13

  (45) 0x40460e VMOVDQU	0x3c0(%RSP,%RAX,1),%YMM0

  (45) 0x404617 VPSRLQ	$0x1,%YMM0,%YMM2

  (45) 0x40461c VPAND	%YMM3,%YMM2,%YMM2

  (45) 0x404620 VPBLENDD	$-0x40,%YMM1,%YMM0,%YMM1

  (45) 0x404626 VPSRLQ	$0x1,%YMM1,%YMM1

  (45) 0x40462b VPERMQ	$-0x6d,%YMM1,%YMM1

  (45) 0x404631 VPAND	%YMM4,%YMM1,%YMM1

  (45) 0x404635 VPTERNLOGQ	$0x56,0x1020(%RSP,%RAX,1),%YMM2,%YMM1

  (45) 0x404641 VPTESTMQ	%YMM5,%YMM0,%K1

  (45) 0x404647 VPXORQ	%YMM6,%YMM1,%YMM1{%K1}

  (45) 0x40464d VMOVDQU	%YMM1,0x3b8(%RSP,%RAX,1)

  (45) 0x404656 ADD	$0x20,%RAX

  (45) 0x40465a CMP	$0x700,%RAX

  (45) 0x404660 JNE	404600

0x404662 MOV	0xac8(%RSP),%RAX

0x40466a VMOVDQU	0xac0(%RSP),%XMM1

0x404673 VPSRLQ	$0x1,%XMM1,%XMM2

0x404678 VEXTRACTI128	$0x1,%YMM0,%XMM0

0x40467e VPUNPCKHQDQ	0xac0(%RSP){1to2},%XMM0,%XMM0

0x404689 VPANDQ	0x8c2d(%RIP){1to2},%XMM2,%XMM2

0x404693 VPSRLQ	$0x1,%XMM0,%XMM0

0x404698 VPANDQ	0x8c26(%RIP){1to2},%XMM0,%XMM0

0x4046a2 VPTERNLOGQ	$0x56,0x1720(%RSP),%XMM2,%XMM0

0x4046ae VPTESTMQ	0x8c18(%RIP){1to0},%XMM1,%K1

0x4046b8 VPXORQ	0x8c16(%RIP){1to2},%XMM0,%XMM0{%K1}

0x4046c2 VMOVDQU	%XMM0,0xab8(%RSP)

0x4046cb MOV	0xad0(%RSP),%ECX

0x4046d2 MOV	%ECX,%EDX

0x4046d4 SHR	$0x1,%EDX

0x4046d6 AND	$0x3fffffff,%EDX

0x4046dc SHR	$0x1,%RAX

0x4046df MOV	$0x7fffffffc0000000,%R8

0x4046e9 AND	%R8,%RAX

0x4046ec ADD	%RDX,%RAX

0x4046ef XOR	0x1730(%RSP),%RAX

0x4046f7 AND	$0x1,%ECX

0x4046fa NEG	%ECX

0x4046fc AND	%ESI,%ECX

0x4046fe XOR	%RAX,%RCX

0x404701 MOV	%RCX,0xac8(%RSP)

0x404709 XOR	%EAX,%EAX

0x40470b VPBROADCASTQ	0x8bab(%RIP),%ZMM3

0x404715 VPBROADCASTQ	0x8ba9(%RIP),%ZMM4

0x40471f VPBROADCASTQ	0x8ba7(%RIP),%ZMM5

0x404729 VPBROADCASTQ	0x8ba5(%RIP),%ZMM6

0x404733 NOPW	%CS:(%RAX,%RAX,1)

  (49) 0x404740 VMOVDQU64	0xad8(%RSP,%RAX,8),%ZMM0

  (49) 0x40474b VPSRLQ	$0x1,%ZMM0,%ZMM1

  (49) 0x404752 VPANDQ	%ZMM3,%ZMM1,%ZMM1

  (49) 0x404758 VPSRLQ	$0x1,0xad0(%RSP,%RAX,8),%ZMM2

  (49) 0x404764 VPANDQ	%ZMM4,%ZMM2,%ZMM2

  (49) 0x40476a VPTERNLOGQ	$0x56,0x3b8(%RSP,%RAX,8),%ZMM1,%ZMM2

  (49) 0x404776 VPTESTMQ	%ZMM5,%ZMM0,%K1

  (49) 0x40477c VPXORQ	%ZMM6,%ZMM2,%ZMM2{%K1}

  (49) 0x404782 VMOVDQU64	%ZMM2,0xad0(%RSP,%RAX,8)

  (49) 0x40478d CMP	$0x17f,%RAX

  (49) 0x404793 JA	4047f0

  (49) 0x404795 VMOVDQU64	0xb18(%RSP,%RAX,8),%ZMM0

  (49) 0x4047a0 VPSRLQ	$0x1,%ZMM0,%ZMM1

  (49) 0x4047a7 VPANDQ	%ZMM3,%ZMM1,%ZMM1

  (49) 0x4047ad VPSRLQ	$0x1,0xb10(%RSP,%RAX,8),%ZMM2

  (49) 0x4047b9 VPANDQ	%ZMM4,%ZMM2,%ZMM2

  (49) 0x4047bf VPTERNLOGQ	$0x56,0x3f8(%RSP,%RAX,8),%ZMM1,%ZMM2

  (49) 0x4047cb VPTESTMQ	%ZMM5,%ZMM0,%K1

  (49) 0x4047d1 VPXORQ	%ZMM6,%ZMM2,%ZMM2{%K1}

  (49) 0x4047d7 VMOVDQU64	%ZMM2,0xb10(%RSP,%RAX,8)

  (49) 0x4047e2 ADD	$0x10,%RAX

  (49) 0x4047e6 JMP	404740

0x4047f0 VMOVDQU	0x1718(%RSP),%YMM0

0x4047f9 VPSRLQ	$0x1,%YMM0,%YMM1

0x4047fe VPSRLQ	$0x1,0x1710(%RSP),%YMM2

0x40480a VPANDQ	0x8aac(%RIP){1to4},%YMM1,%YMM1

0x404814 VPANDQ	0x8aaa(%RIP){1to4},%YMM2,%YMM2

0x40481e VPTERNLOGQ	$0x56,0xff8(%RSP),%YMM1,%YMM2

0x40482a VPTESTMQ	0x8a9c(%RIP){1to0},%YMM0,%K1

0x404834 VPXORQ	0x8a9a(%RIP){1to4},%YMM2,%YMM2{%K1}

0x40483e VMOVDQU	%YMM2,0x1710(%RSP)

0x404847 MOV	0x1730(%RSP),%RCX

0x40484f MOV	0x3b8(%RSP),%RAX

0x404857 MOV	%EAX,%EDX

0x404859 SHR	$0x1,%EDX

0x40485b AND	$0x3fffffff,%EDX

0x404861 SHR	$0x1,%RCX

0x404864 MOV	$0x7fffffffc0000000,%R8

0x40486e AND	%R8,%RCX

0x404871 ADD	%RDX,%RCX

0x404874 XOR	0x1018(%RSP),%RCX

0x40487c MOV	%EAX,%EDX

0x40487e AND	$0x1,%EDX

0x404881 NEG	%EDX

0x404883 AND	%ESI,%EDX

0x404885 XOR	%RCX,%RDX

0x404888 MOV	%RDX,0x1730(%RSP)

0x404890 MOV	$0x1,%EDX

0x404895 MOV	%RAX,%R13

0x404898 JMP	4048fb

0x40489a VXORPS	%XMM1,%XMM1,%XMM1

0x40489e VMOVSS	0x87c2(%RIP),%XMM0

0x4048a6 MOV	%R9,0x38(%RSP)

0x4048ab MOV	%RDX,0x30(%RSP)

0x4048b0 VZEROUPPER

0x4048b3 CALL	406ac0 <nextafterf>

0x4048b8 MOV	0x30(%RSP),%RDX

0x4048bd MOV	0x38(%RSP),%R9

0x4048c2 MOV	0xb8(%RSP),%RDI

0x4048ca MOV	$-0x66f74f21,%ESI

0x4048cf MOV	0x58(%RSP),%RAX

0x4048d4 VMOVSS	%XMM0,(%RAX,%R9,4)

0x4048da CMP	$0x270,%RDX

0x4048e1 JAE	4045cd

0x4048e7 NOPW	(%RAX,%RAX,1)

0x4048f0 MOV	0x3b8(%RSP,%RDX,8),%RAX

0x4048f8 INC	%RDX

0x4048fb MOV	%RAX,%RCX

0x4048fe SHR	$0xb,%RCX

0x404902 MOV	%ECX,%ECX

0x404904 XOR	%RAX,%RCX

0x404907 MOV	%ECX,%EAX

0x404909 SAL	$0x7,%EAX

0x40490c AND	$-0x62d3a980,%EAX

0x404911 XOR	%RCX,%RAX

0x404914 MOV	%EAX,%ECX

0x404916 SAL	$0xf,%ECX

0x404919 AND	$-0x103a0000,%ECX

0x40491f XOR	%RAX,%RCX

0x404922 MOV	%RCX,%RAX

0x404925 SHR	$0x12,%RAX

0x404929 XOR	%RCX,%RAX

0x40492c VCVTUSI2SS	%RAX,%XMM7,%XMM0

0x404932 VMULSS	0x8732(%RIP),%XMM0,%XMM0

0x40493a VUCOMISS	0x8726(%RIP),%XMM0

0x404942 JAE	404c2a

0x404948 MOV	0x50(%RSP),%RAX

0x40494d VMOVSS	%XMM0,(%RAX,%R9,4)

0x404953 CMP	$0x270,%RDX

0x40495a JB	404c80

0x404960 XOR	%EAX,%EAX

0x404962 VPBROADCASTQ	0x8955(%RIP),%YMM3

0x40496b VPBROADCASTQ	0x8954(%RIP),%YMM4

0x404974 VPBROADCASTQ	0x8953(%RIP),%YMM5

0x40497d VPBROADCASTQ	0x8952(%RIP),%YMM6

0x404986 NOPW	%CS:(%RAX,%RAX,1)

  (46) 0x404990 VPBROADCASTQ	%R13,%YMM1

  (46) 0x404996 MOV	0x3d8(%RSP,%RAX,1),%R13

  (46) 0x40499e VMOVDQU	0x3c0(%RSP,%RAX,1),%YMM0

  (46) 0x4049a7 VPSRLQ	$0x1,%YMM0,%YMM2

  (46) 0x4049ac VPAND	%YMM3,%YMM2,%YMM2

  (46) 0x4049b0 VPBLENDD	$-0x40,%YMM1,%YMM0,%YMM1

  (46) 0x4049b6 VPSRLQ	$0x1,%YMM1,%YMM1

  (46) 0x4049bb VPERMQ	$-0x6d,%YMM1,%YMM1

  (46) 0x4049c1 VPAND	%YMM4,%YMM1,%YMM1

  (46) 0x4049c5 VPTERNLOGQ	$0x56,0x1020(%RSP,%RAX,1),%YMM2,%YMM1

  (46) 0x4049d1 VPTESTMQ	%YMM5,%YMM0,%K1

  (46) 0x4049d7 VPXORQ	%YMM6,%YMM1,%YMM1{%K1}

  (46) 0x4049dd VMOVDQU	%YMM1,0x3b8(%RSP,%RAX,1)

  (46) 0x4049e6 ADD	$0x20,%RAX

  (46) 0x4049ea CMP	$0x700,%RAX

  (46) 0x4049f0 JNE	404990

0x4049f2 MOV	0xac8(%RSP),%RAX

0x4049fa VMOVDQU	0xac0(%RSP),%XMM1

0x404a03 VPSRLQ	$0x1,%XMM1,%XMM2

0x404a08 VEXTRACTI128	$0x1,%YMM0,%XMM0

0x404a0e VPUNPCKHQDQ	0xac0(%RSP){1to2},%XMM0,%XMM0

0x404a19 VPANDQ	0x889d(%RIP){1to2},%XMM2,%XMM2

0x404a23 VPSRLQ	$0x1,%XMM0,%XMM0

0x404a28 VPANDQ	0x8896(%RIP){1to2},%XMM0,%XMM0

0x404a32 VPTERNLOGQ	$0x56,0x1720(%RSP),%XMM2,%XMM0

0x404a3e VPTESTMQ	0x8888(%RIP){1to0},%XMM1,%K1

0x404a48 VPXORQ	0x8886(%RIP){1to2},%XMM0,%XMM0{%K1}

0x404a52 VMOVDQU	%XMM0,0xab8(%RSP)

0x404a5b MOV	0xad0(%RSP),%ECX

0x404a62 MOV	%ECX,%EDX

0x404a64 SHR	$0x1,%EDX

0x404a66 AND	$0x3fffffff,%EDX

0x404a6c SHR	$0x1,%RAX

0x404a6f MOV	$0x7fffffffc0000000,%R8

0x404a79 AND	%R8,%RAX

0x404a7c ADD	%RDX,%RAX

0x404a7f XOR	0x1730(%RSP),%RAX

0x404a87 AND	$0x1,%ECX

0x404a8a NEG	%ECX

0x404a8c AND	%ESI,%ECX

0x404a8e XOR	%RAX,%RCX

0x404a91 MOV	%RCX,0xac8(%RSP)

0x404a99 XOR	%EAX,%EAX

0x404a9b VPBROADCASTQ	0x881b(%RIP),%ZMM3

0x404aa5 VPBROADCASTQ	0x8819(%RIP),%ZMM4

0x404aaf VPBROADCASTQ	0x8817(%RIP),%ZMM5

0x404ab9 VPBROADCASTQ	0x8815(%RIP),%ZMM6

0x404ac3 NOPW	%CS:(%RAX,%RAX,1)

  (48) 0x404ad0 VMOVDQU64	0xad8(%RSP,%RAX,8),%ZMM0

  (48) 0x404adb VPSRLQ	$0x1,%ZMM0,%ZMM1

  (48) 0x404ae2 VPANDQ	%ZMM3,%ZMM1,%ZMM1

  (48) 0x404ae8 VPSRLQ	$0x1,0xad0(%RSP,%RAX,8),%ZMM2

  (48) 0x404af4 VPANDQ	%ZMM4,%ZMM2,%ZMM2

  (48) 0x404afa VPTERNLOGQ	$0x56,0x3b8(%RSP,%RAX,8),%ZMM1,%ZMM2

  (48) 0x404b06 VPTESTMQ	%ZMM5,%ZMM0,%K1

  (48) 0x404b0c VPXORQ	%ZMM6,%ZMM2,%ZMM2{%K1}

  (48) 0x404b12 VMOVDQU64	%ZMM2,0xad0(%RSP,%RAX,8)

  (48) 0x404b1d CMP	$0x17f,%RAX

  (48) 0x404b23 JA	404b80

  (48) 0x404b25 VMOVDQU64	0xb18(%RSP,%RAX,8),%ZMM0

  (48) 0x404b30 VPSRLQ	$0x1,%ZMM0,%ZMM1

  (48) 0x404b37 VPANDQ	%ZMM3,%ZMM1,%ZMM1

  (48) 0x404b3d VPSRLQ	$0x1,0xb10(%RSP,%RAX,8),%ZMM2

  (48) 0x404b49 VPANDQ	%ZMM4,%ZMM2,%ZMM2

  (48) 0x404b4f VPTERNLOGQ	$0x56,0x3f8(%RSP,%RAX,8),%ZMM1,%ZMM2

  (48) 0x404b5b VPTESTMQ	%ZMM5,%ZMM0,%K1

  (48) 0x404b61 VPXORQ	%ZMM6,%ZMM2,%ZMM2{%K1}

  (48) 0x404b67 VMOVDQU64	%ZMM2,0xb10(%RSP,%RAX,8)

  (48) 0x404b72 ADD	$0x10,%RAX

  (48) 0x404b76 JMP	404ad0

0x404b80 VMOVDQU	0x1718(%RSP),%YMM0

0x404b89 VPSRLQ	$0x1,%YMM0,%YMM1

0x404b8e VPSRLQ	$0x1,0x1710(%RSP),%YMM2

0x404b9a VPANDQ	0x871c(%RIP){1to4},%YMM1,%YMM1

0x404ba4 VPANDQ	0x871a(%RIP){1to4},%YMM2,%YMM2

0x404bae VPTERNLOGQ	$0x56,0xff8(%RSP),%YMM1,%YMM2

0x404bba VPTESTMQ	0x870c(%RIP){1to0},%YMM0,%K1

0x404bc4 VPXORQ	0x870a(%RIP){1to4},%YMM2,%YMM2{%K1}

0x404bce VMOVDQU	%YMM2,0x1710(%RSP)

0x404bd7 MOV	0x1730(%RSP),%RCX

0x404bdf MOV	0x3b8(%RSP),%RAX

0x404be7 MOV	%EAX,%EDX

0x404be9 SHR	$0x1,%EDX

0x404beb AND	$0x3fffffff,%EDX

0x404bf1 SHR	$0x1,%RCX

0x404bf4 MOV	$0x7fffffffc0000000,%R8

0x404bfe AND	%R8,%RCX

0x404c01 ADD	%RDX,%RCX

0x404c04 XOR	0x1018(%RSP),%RCX

0x404c0c MOV	%EAX,%EDX

0x404c0e AND	$0x1,%EDX

0x404c11 NEG	%EDX

0x404c13 AND	%ESI,%EDX

0x404c15 XOR	%RCX,%RDX

0x404c18 MOV	%RDX,0x1730(%RSP)

0x404c20 MOV	$0x1,%EDX

0x404c25 MOV	%RAX,%R13

0x404c28 JMP	404c8b

0x404c2a VXORPS	%XMM1,%XMM1,%XMM1

0x404c2e VMOVSS	0x8432(%RIP),%XMM0

0x404c36 MOV	%R9,0x38(%RSP)

0x404c3b MOV	%RDX,0x30(%RSP)

0x404c40 VZEROUPPER

0x404c43 CALL	406ac0 <nextafterf>

0x404c48 MOV	0x30(%RSP),%RDX

0x404c4d MOV	0x38(%RSP),%R9

0x404c52 MOV	0xb8(%RSP),%RDI

0x404c5a MOV	$-0x66f74f21,%ESI

0x404c5f MOV	0x50(%RSP),%RAX

0x404c64 VMOVSS	%XMM0,(%RAX,%R9,4)

0x404c6a CMP	$0x270,%RDX

0x404c71 JAE	404960

0x404c77 NOPW	(%RAX,%RAX,1)

0x404c80 MOV	0x3b8(%RSP,%RDX,8),%RAX

0x404c88 INC	%RDX

0x404c8b MOV	%RAX,%RCX

0x404c8e SHR	$0xb,%RCX

0x404c92 MOV	%ECX,%ECX

0x404c94 XOR	%RAX,%RCX

0x404c97 MOV	%ECX,%EAX

0x404c99 SAL	$0x7,%EAX

0x404c9c AND	$-0x62d3a980,%EAX

0x404ca1 XOR	%RCX,%RAX

0x404ca4 MOV	%EAX,%ECX

0x404ca6 SAL	$0xf,%ECX

0x404ca9 AND	$-0x103a0000,%ECX

0x404caf XOR	%RAX,%RCX

0x404cb2 MOV	%RCX,%RAX

0x404cb5 SHR	$0x12,%RAX

0x404cb9 XOR	%RCX,%RAX

0x404cbc VCVTUSI2SS	%RAX,%XMM7,%XMM0

0x404cc2 VMULSS	0x83a2(%RIP),%XMM0,%XMM0

0x404cca VUCOMISS	0x8396(%RIP),%XMM0

0x404cd2 JAE	404cf4

0x404cd4 MOV	0xc0(%RSP),%RAX

0x404cdc VMOVSS	%XMM0,(%RAX,%R9,4)

0x404ce2 LEA	0x1(%R9),%RAX

0x404ce6 CMP	%RDI,%R9

0x404ce9 MOV	%RAX,%R9

0x404cec JNE	404280

0x404cf4 VXORPS	%XMM1,%XMM1,%XMM1

0x404cf8 VMOVSS	0x8368(%RIP),%XMM0

0x404d00 MOV	%R9,0x38(%RSP)

0x404d05 MOV	%RDX,0x30(%RSP)

0x404d0a VZEROUPPER

0x404d0d CALL	406ac0 <nextafterf>

0x404d12 MOV	0x30(%RSP),%RDX

0x404d17 MOV	0x38(%RSP),%R9

0x404d1c MOV	0xb8(%RSP),%RDI

0x404d24 MOV	$-0x66f74f21,%ESI

0x404d29 JMP	404cd4

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath: 1661 - 1661

--------------------------------------------------------------------------------

1661:   { return __builtin_nextafterf(__x, __y); }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc: 401 - 3370

--------------------------------------------------------------------------------

401:       for (size_t __k = 0; __k < (__n - __m); ++__k)

402:         {

403: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

404: 			   | (_M_x[__k + 1] & __lower_mask));

405: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

406: 		       ^ ((__y & 0x01) ? __a : 0));

407:         }

408:

409:       for (size_t __k = (__n - __m); __k < (__n - 1); ++__k)

410: 	{

411: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

412: 			   | (_M_x[__k + 1] & __lower_mask));

413: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

414: 		       ^ ((__y & 0x01) ? __a : 0));

415: 	}

416:

417:       _UIntType __y = ((_M_x[__n - 1] & __upper_mask)

418: 		       | (_M_x[0] & __lower_mask));

419:       _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1)

420: 		       ^ ((__y & 0x01) ? __a : 0));

[...]

455:       if (_M_p >= state_size)

456: 	_M_gen_rand();

457:

458:       // Calculate o(x(i)).

459:       result_type __z = _M_x[_M_p++];

460:       __z ^= (__z >> __u) & __d;

461:       __z ^= (__z << __s) & __b;

462:       __z ^= (__z << __t) & __c;

463:       __z ^= (__z >> __l);

[...]

3366: 	  __sum += _RealType(__urng() - __urng.min()) * __tmp;

3367: 	  __tmp *= __r;

3368: 	}

3369:       __ret = __sum / __tmp;

3370:       if (__builtin_expect(__ret >= _RealType(1), 0))

/home/eoseret/llm-attention/attention_v2.cpp: 164 - 167

--------------------------------------------------------------------------------

164:       for (size_t i = 0; i < elemsW; ++i) {

165:          h_WQ[i] = dist(rng);

166:          h_WK[i] = dist(rng);

167:          h_WV[i] = dist(rng);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.15
CQA speedup if FP arith vectorized	1.92
CQA speedup if fully vectorized	7.58
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.58
Bottlenecks	micro-operation queue,
Function	main
Source	cmath:1661-1661,random.tcc:404-406,random.tcc:412-414,random.tcc:417-420,random.tcc:455-455,random.tcc:459-463,random.tcc:3366-3366,random.tcc:3369-3370,attention_v2.cpp:164-167
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	58.00
CQA cycles if no scalar integer	27.00
CQA cycles if FP arith vectorized	30.21
CQA cycles if fully vectorized	7.65
Front-end cycles	58.00
P0 cycles	35.93
P1 cycles	36.10
P2 cycles	36.67
P3 cycles	36.67
P4 cycles	13.00
P5 cycles	36.07
P6 cycles	35.90
P7 cycles	13.00
P8 cycles	13.00
P9 cycles	13.00
P10 cycles	36.00
P11 cycles	36.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	318.00
Nb uops	348.00
Nb loads	110.00
Nb stores	23.00
Nb stack references	17.00
FLOP/cycle	0.05
Nb FLOP add-sub	0.00
Nb FLOP mul	3.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.38
Bytes prefetched	0.00
Bytes loaded	1096.00
Bytes stored	260.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	33.16
Vectorization ratio load	46.43
Vectorization ratio store	26.09
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	34.93
Vector-efficiency ratio all	18.85
Vector-efficiency ratio load	23.66
Vector-efficiency ratio store	17.66
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	19.31

Metric	Value
CQA speedup if no scalar integer	2.15
CQA speedup if FP arith vectorized	1.92
CQA speedup if fully vectorized	7.58
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.58
Bottlenecks	micro-operation queue,
Function	main
Source	cmath:1661-1661,random.tcc:404-406,random.tcc:412-414,random.tcc:417-420,random.tcc:455-455,random.tcc:459-463,random.tcc:3366-3366,random.tcc:3369-3370,attention_v2.cpp:164-167
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	58.00
CQA cycles if no scalar integer	27.00
CQA cycles if FP arith vectorized	30.21
CQA cycles if fully vectorized	7.65
Front-end cycles	58.00
P0 cycles	35.93
P1 cycles	36.10
P2 cycles	36.67
P3 cycles	36.67
P4 cycles	13.00
P5 cycles	36.07
P6 cycles	35.90
P7 cycles	13.00
P8 cycles	13.00
P9 cycles	13.00
P10 cycles	36.00
P11 cycles	36.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	318.00
Nb uops	348.00
Nb loads	110.00
Nb stores	23.00
Nb stack references	17.00
FLOP/cycle	0.05
Nb FLOP add-sub	0.00
Nb FLOP mul	3.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.38
Bytes prefetched	0.00
Bytes loaded	1096.00
Bytes stored	260.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	33.16
Vectorization ratio load	46.43
Vectorization ratio store	26.09
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	34.93
Vector-efficiency ratio all	18.85
Vector-efficiency ratio load	23.66
Vector-efficiency ratio store	17.66
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	19.31

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:164-167
Module	attention-gnr-512

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:401-420,455-463,3366-3370
/home/eoseret/llm-attention/attention_v2.cpp:164-167

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 85 paths individually, rerun with max-paths=85
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 85 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 58.00 to 27.00 cycles (2.15x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 18% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 58.00 to 7.65 cycles (7.58x speedup).

Details

33% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

46% of SSE/AVX loads are used in vector version.
26% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
34% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

nextafterf: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTUSI2SS: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366
VPSRLQ: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:413
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:413
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:413
VPTERNLOGQ: 6 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:405
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:413
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:405
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:413
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:405
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:413
VPTESTMQ: 6 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:406
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:414
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:406
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:414
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:406
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:414
VUCOMISS: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370
VZEROUPPER: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

3: multiply

The binary loop is loading 1096 bytes (274 single precision FP elements). The binary loop is storing 260 bytes (65 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	318
nb uops	348
loop length	1907
used x86 registers	9
used mmx registers	0
used xmm registers	4
used ymm registers	7
used zmm registers	4
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	58.00 cycles
front end	58.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	35.93	36.10	36.67	36.67	13.00	36.07	35.90	13.00	13.00	13.00	36.00	36.67
cycles	35.93	36.10	36.67	36.67	13.00	36.07	35.90	13.00	13.00	13.00	36.00	36.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	58.00
Dispatch	36.67
Overall L1	58.00

Vectorization ratios

INT

all	34%
load	52%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	34%

all	17%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	33%
load	46%
store	26%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	34%

Vector efficiency ratios

INT

all	19%
load	25%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	19%

all	9%
load	6%
store	6%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	18%
load	23%
store	17%
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 58.00 cycles. At this rate:

9% of peak load performance is reached (18.90 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.48 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 58.00 to 36.67 cycles (1.58x speedup).

ASM code

In the binary file, the address of the loop is: 404280

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
CMP $0x270,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 4044b0 <main+0x11f0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ 0x9028(%RIP),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x9027(%RIP),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x9026(%RIP),%YMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x9025(%RIP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xac8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVDQU 0xac0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VEXTRACTI128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPUNPCKHQDQ 0xac0(%RSP){1to2},%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	scal (12.5%)
VPANDQ 0x8f6d(%RIP){1to2},%XMM2,%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VPANDQ 0x8f66(%RIP){1to2},%XMM0,%XMM0	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPTERNLOGQ $0x56,0x1720(%RSP),%XMM2,%XMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPTESTMQ 0x8f58(%RIP){1to0},%XMM1,%K1	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (25.0%)
VPXORQ 0x8f56(%RIP){1to2},%XMM0,%XMM0{%K1}	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVDQU %XMM0,0xab8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0xad0(%RSP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $0x3fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x1,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV $0x7fffffffc0000000,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
AND %R8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR 0x1730(%RSP),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	N/A
AND $0x1,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
NEG %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
AND %ESI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RCX,0xac8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ 0x8eeb(%RIP),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8ee9(%RIP),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8ee7(%RIP),%ZMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8ee5(%RIP),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x3b8(%RSP,%RDX,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 404568 <main+0x12a8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VMOVDQU 0x1718(%RSP),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VPSRLQ $0x1,%YMM0,%YMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (50.0%)
VPSRLQ $0x1,0x1710(%RSP),%YMM2	2	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	2-4	0.50	vect (50.0%)
VPANDQ 0x8ddc(%RIP){1to4},%YMM1,%YMM1	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPANDQ 0x8dda(%RIP){1to4},%YMM2,%YMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPTERNLOGQ $0x56,0xff8(%RSP),%YMM1,%YMM2	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.38	vect (50.0%)
VPTESTMQ 0x8dcc(%RIP){1to0},%YMM0,%K1	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (50.0%)
VPXORQ 0x8dca(%RIP){1to4},%YMM2,%YMM2{%K1}	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.40	vect (50.0%)
VMOVDQU %YMM2,0x1710(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
MOV 0x1730(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x3b8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $0x3fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x1,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV $0x7fffffffc0000000,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
AND %R8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
XOR 0x1018(%RSP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	scal (12.5%)
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
NEG %EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %ESI,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RDX,0x1730(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0xb,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x7,%EAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $-0x62d3a980,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0xf,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
AND $-0x103a0000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x12,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
XOR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VCVTUSI2SS %RAX,%XMM7,%XMM0	3	0.50	0.50	0	0	0	2	0	0	0	0	0	0	8	2	scal (12.5%)
VMULSS 0x8ac5(%RIP),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VUCOMISS 0x8ab9(%RIP),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (6.3%)
JAE 40489a <main+0x15da>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x58(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP $0x270,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 4048f0 <main+0x1630>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ 0x8ce8(%RIP),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8ce7(%RIP),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8ce6(%RIP),%YMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8ce5(%RIP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xac8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVDQU 0xac0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VEXTRACTI128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPUNPCKHQDQ 0xac0(%RSP){1to2},%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	scal (12.5%)
VPANDQ 0x8c2d(%RIP){1to2},%XMM2,%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VPANDQ 0x8c26(%RIP){1to2},%XMM0,%XMM0	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPTERNLOGQ $0x56,0x1720(%RSP),%XMM2,%XMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPTESTMQ 0x8c18(%RIP){1to0},%XMM1,%K1	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (25.0%)
VPXORQ 0x8c16(%RIP){1to2},%XMM0,%XMM0{%K1}	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVDQU %XMM0,0xab8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0xad0(%RSP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $0x3fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x1,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV $0x7fffffffc0000000,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
AND %R8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR 0x1730(%RSP),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	N/A
AND $0x1,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
NEG %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
AND %ESI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RCX,0xac8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ 0x8bab(%RIP),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8ba9(%RIP),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8ba7(%RIP),%ZMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8ba5(%RIP),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVDQU 0x1718(%RSP),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VPSRLQ $0x1,%YMM0,%YMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (50.0%)
VPSRLQ $0x1,0x1710(%RSP),%YMM2	2	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	2-4	0.50	vect (50.0%)
VPANDQ 0x8aac(%RIP){1to4},%YMM1,%YMM1	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPANDQ 0x8aaa(%RIP){1to4},%YMM2,%YMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPTERNLOGQ $0x56,0xff8(%RSP),%YMM1,%YMM2	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.38	vect (50.0%)
VPTESTMQ 0x8a9c(%RIP){1to0},%YMM0,%K1	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (50.0%)
VPXORQ 0x8a9a(%RIP){1to4},%YMM2,%YMM2{%K1}	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.40	vect (50.0%)
VMOVDQU %YMM2,0x1710(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
MOV 0x1730(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x3b8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $0x3fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x1,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV $0x7fffffffc0000000,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
AND %R8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
XOR 0x1018(%RSP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	scal (12.5%)
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
NEG %EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %ESI,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RDX,0x1730(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JMP 4048fb <main+0x163b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSS 0x87c2(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %R9,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ac0 <nextafterf>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x30(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x38(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xb8(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $-0x66f74f21,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV 0x58(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP $0x270,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 4045cd <main+0x130d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x3b8(%RSP,%RDX,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0xb,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x7,%EAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $-0x62d3a980,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0xf,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
AND $-0x103a0000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x12,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
XOR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VCVTUSI2SS %RAX,%XMM7,%XMM0	3	0.50	0.50	0	0	0	2	0	0	0	0	0	0	8	2	scal (12.5%)
VMULSS 0x8732(%RIP),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VUCOMISS 0x8726(%RIP),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (6.3%)
JAE 404c2a <main+0x196a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x50(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP $0x270,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 404c80 <main+0x19c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ 0x8955(%RIP),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8954(%RIP),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8953(%RIP),%YMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8952(%RIP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xac8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVDQU 0xac0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VEXTRACTI128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPUNPCKHQDQ 0xac0(%RSP){1to2},%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	scal (12.5%)
VPANDQ 0x889d(%RIP){1to2},%XMM2,%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VPANDQ 0x8896(%RIP){1to2},%XMM0,%XMM0	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPTERNLOGQ $0x56,0x1720(%RSP),%XMM2,%XMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPTESTMQ 0x8888(%RIP){1to0},%XMM1,%K1	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (25.0%)
VPXORQ 0x8886(%RIP){1to2},%XMM0,%XMM0{%K1}	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVDQU %XMM0,0xab8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0xad0(%RSP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $0x3fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x1,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV $0x7fffffffc0000000,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
AND %R8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR 0x1730(%RSP),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	N/A
AND $0x1,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
NEG %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
AND %ESI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RCX,0xac8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ 0x881b(%RIP),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8819(%RIP),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8817(%RIP),%ZMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8815(%RIP),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVDQU 0x1718(%RSP),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VPSRLQ $0x1,%YMM0,%YMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (50.0%)
VPSRLQ $0x1,0x1710(%RSP),%YMM2	2	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	2-4	0.50	vect (50.0%)
VPANDQ 0x871c(%RIP){1to4},%YMM1,%YMM1	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPANDQ 0x871a(%RIP){1to4},%YMM2,%YMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPTERNLOGQ $0x56,0xff8(%RSP),%YMM1,%YMM2	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.38	vect (50.0%)
VPTESTMQ 0x870c(%RIP){1to0},%YMM0,%K1	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (50.0%)
VPXORQ 0x870a(%RIP){1to4},%YMM2,%YMM2{%K1}	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.40	vect (50.0%)
VMOVDQU %YMM2,0x1710(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
MOV 0x1730(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x3b8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $0x3fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x1,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV $0x7fffffffc0000000,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
AND %R8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
XOR 0x1018(%RSP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	scal (12.5%)
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
NEG %EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %ESI,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RDX,0x1730(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JMP 404c8b <main+0x19cb>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSS 0x8432(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %R9,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ac0 <nextafterf>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x30(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x38(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xb8(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $-0x66f74f21,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV 0x50(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP $0x270,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 404960 <main+0x16a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x3b8(%RSP,%RDX,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0xb,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x7,%EAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $-0x62d3a980,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0xf,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
AND $-0x103a0000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x12,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
XOR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VCVTUSI2SS %RAX,%XMM7,%XMM0	3	0.50	0.50	0	0	0	2	0	0	0	0	0	0	8	2	scal (12.5%)
VMULSS 0x83a2(%RIP),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VUCOMISS 0x8396(%RIP),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (6.3%)
JAE 404cf4 <main+0x1a34>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0xc0(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x1(%R9),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RDI,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 404280 <main+0xfc0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSS 0x8368(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %R9,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ac0 <nextafterf>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x30(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x38(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xb8(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $-0x66f74f21,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JMP 404cd4 <main+0x1a14>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

Function	main
Source file and lines	attention_v2.cpp:164-167
Module	attention-gnr-512

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:401-420,455-463,3366-3370
/home/eoseret/llm-attention/attention_v2.cpp:164-167

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 85 paths individually, rerun with max-paths=85
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

33% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

46% of SSE/AVX loads are used in vector version.
26% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
34% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

CALL instructions

Detected function call instructions.

Details

nextafterf: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTUSI2SS: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366
VPSRLQ: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:413
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:413
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:413
VPTERNLOGQ: 6 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:405
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:413
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:405
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:413
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:405
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:413
VPTESTMQ: 6 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:406
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:414
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:406
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:414
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:406
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:414
VUCOMISS: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370
VZEROUPPER: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

3: multiply

The binary loop is loading 1096 bytes (274 single precision FP elements). The binary loop is storing 260 bytes (65 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	318
nb uops	348
loop length	1907
used x86 registers	9
used mmx registers	0
used xmm registers	4
used ymm registers	7
used zmm registers	4
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	58.00 cycles
front end	58.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	35.93	36.10	36.67	36.67	13.00	36.07	35.90	13.00	13.00	13.00	36.00	36.67
cycles	35.93	36.10	36.67	36.67	13.00	36.07	35.90	13.00	13.00	13.00	36.00	36.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	58.00
Dispatch	36.67
Overall L1	58.00

Vectorization ratios

INT

all	34%
load	52%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	34%

all	17%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	33%
load	46%
store	26%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	34%

Vector efficiency ratios

INT

all	19%
load	25%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	19%

all	9%
load	6%
store	6%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	18%
load	23%
store	17%
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 58.00 cycles. At this rate:

9% of peak load performance is reached (18.90 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.48 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 404280

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
CMP $0x270,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 4044b0 <main+0x11f0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ 0x9028(%RIP),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x9027(%RIP),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x9026(%RIP),%YMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x9025(%RIP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xac8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVDQU 0xac0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VEXTRACTI128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPUNPCKHQDQ 0xac0(%RSP){1to2},%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	scal (12.5%)
VPANDQ 0x8f6d(%RIP){1to2},%XMM2,%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VPANDQ 0x8f66(%RIP){1to2},%XMM0,%XMM0	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPTERNLOGQ $0x56,0x1720(%RSP),%XMM2,%XMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPTESTMQ 0x8f58(%RIP){1to0},%XMM1,%K1	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (25.0%)
VPXORQ 0x8f56(%RIP){1to2},%XMM0,%XMM0{%K1}	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVDQU %XMM0,0xab8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0xad0(%RSP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $0x3fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x1,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV $0x7fffffffc0000000,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
AND %R8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR 0x1730(%RSP),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	N/A
AND $0x1,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
NEG %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
AND %ESI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RCX,0xac8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ 0x8eeb(%RIP),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8ee9(%RIP),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8ee7(%RIP),%ZMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8ee5(%RIP),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x3b8(%RSP,%RDX,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JMP 404568 <main+0x12a8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VMOVDQU 0x1718(%RSP),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VPSRLQ $0x1,%YMM0,%YMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (50.0%)
VPSRLQ $0x1,0x1710(%RSP),%YMM2	2	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	2-4	0.50	vect (50.0%)
VPANDQ 0x8ddc(%RIP){1to4},%YMM1,%YMM1	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPANDQ 0x8dda(%RIP){1to4},%YMM2,%YMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPTERNLOGQ $0x56,0xff8(%RSP),%YMM1,%YMM2	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.38	vect (50.0%)
VPTESTMQ 0x8dcc(%RIP){1to0},%YMM0,%K1	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (50.0%)
VPXORQ 0x8dca(%RIP){1to4},%YMM2,%YMM2{%K1}	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.40	vect (50.0%)
VMOVDQU %YMM2,0x1710(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
MOV 0x1730(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x3b8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $0x3fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x1,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV $0x7fffffffc0000000,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
AND %R8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
XOR 0x1018(%RSP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	scal (12.5%)
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
NEG %EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %ESI,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RDX,0x1730(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0xb,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x7,%EAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $-0x62d3a980,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0xf,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
AND $-0x103a0000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x12,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
XOR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VCVTUSI2SS %RAX,%XMM7,%XMM0	3	0.50	0.50	0	0	0	2	0	0	0	0	0	0	8	2	scal (12.5%)
VMULSS 0x8ac5(%RIP),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VUCOMISS 0x8ab9(%RIP),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (6.3%)
JAE 40489a <main+0x15da>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x58(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP $0x270,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 4048f0 <main+0x1630>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ 0x8ce8(%RIP),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8ce7(%RIP),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8ce6(%RIP),%YMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8ce5(%RIP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xac8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVDQU 0xac0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VEXTRACTI128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPUNPCKHQDQ 0xac0(%RSP){1to2},%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	scal (12.5%)
VPANDQ 0x8c2d(%RIP){1to2},%XMM2,%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VPANDQ 0x8c26(%RIP){1to2},%XMM0,%XMM0	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPTERNLOGQ $0x56,0x1720(%RSP),%XMM2,%XMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPTESTMQ 0x8c18(%RIP){1to0},%XMM1,%K1	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (25.0%)
VPXORQ 0x8c16(%RIP){1to2},%XMM0,%XMM0{%K1}	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVDQU %XMM0,0xab8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0xad0(%RSP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $0x3fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x1,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV $0x7fffffffc0000000,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
AND %R8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR 0x1730(%RSP),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	N/A
AND $0x1,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
NEG %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
AND %ESI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RCX,0xac8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ 0x8bab(%RIP),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8ba9(%RIP),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8ba7(%RIP),%ZMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8ba5(%RIP),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVDQU 0x1718(%RSP),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VPSRLQ $0x1,%YMM0,%YMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (50.0%)
VPSRLQ $0x1,0x1710(%RSP),%YMM2	2	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	2-4	0.50	vect (50.0%)
VPANDQ 0x8aac(%RIP){1to4},%YMM1,%YMM1	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPANDQ 0x8aaa(%RIP){1to4},%YMM2,%YMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPTERNLOGQ $0x56,0xff8(%RSP),%YMM1,%YMM2	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.38	vect (50.0%)
VPTESTMQ 0x8a9c(%RIP){1to0},%YMM0,%K1	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (50.0%)
VPXORQ 0x8a9a(%RIP){1to4},%YMM2,%YMM2{%K1}	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.40	vect (50.0%)
VMOVDQU %YMM2,0x1710(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
MOV 0x1730(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x3b8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $0x3fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x1,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV $0x7fffffffc0000000,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
AND %R8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
XOR 0x1018(%RSP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	scal (12.5%)
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
NEG %EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %ESI,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RDX,0x1730(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JMP 4048fb <main+0x163b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSS 0x87c2(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %R9,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ac0 <nextafterf>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x30(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x38(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xb8(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $-0x66f74f21,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV 0x58(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP $0x270,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 4045cd <main+0x130d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x3b8(%RSP,%RDX,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0xb,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x7,%EAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $-0x62d3a980,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0xf,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
AND $-0x103a0000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x12,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
XOR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VCVTUSI2SS %RAX,%XMM7,%XMM0	3	0.50	0.50	0	0	0	2	0	0	0	0	0	0	8	2	scal (12.5%)
VMULSS 0x8732(%RIP),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VUCOMISS 0x8726(%RIP),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (6.3%)
JAE 404c2a <main+0x196a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x50(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP $0x270,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 404c80 <main+0x19c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ 0x8955(%RIP),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8954(%RIP),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8953(%RIP),%YMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8952(%RIP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xac8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVDQU 0xac0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VEXTRACTI128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPUNPCKHQDQ 0xac0(%RSP){1to2},%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	scal (12.5%)
VPANDQ 0x889d(%RIP){1to2},%XMM2,%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VPANDQ 0x8896(%RIP){1to2},%XMM0,%XMM0	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPTERNLOGQ $0x56,0x1720(%RSP),%XMM2,%XMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPTESTMQ 0x8888(%RIP){1to0},%XMM1,%K1	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (25.0%)
VPXORQ 0x8886(%RIP){1to2},%XMM0,%XMM0{%K1}	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVDQU %XMM0,0xab8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0xad0(%RSP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $0x3fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x1,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV $0x7fffffffc0000000,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
AND %R8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR 0x1730(%RSP),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	N/A
AND $0x1,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
NEG %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
AND %ESI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RCX,0xac8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ 0x881b(%RIP),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8819(%RIP),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8817(%RIP),%ZMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x8815(%RIP),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVDQU 0x1718(%RSP),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VPSRLQ $0x1,%YMM0,%YMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (50.0%)
VPSRLQ $0x1,0x1710(%RSP),%YMM2	2	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	2-4	0.50	vect (50.0%)
VPANDQ 0x871c(%RIP){1to4},%YMM1,%YMM1	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPANDQ 0x871a(%RIP){1to4},%YMM2,%YMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPTERNLOGQ $0x56,0xff8(%RSP),%YMM1,%YMM2	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.38	vect (50.0%)
VPTESTMQ 0x870c(%RIP){1to0},%YMM0,%K1	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (50.0%)
VPXORQ 0x870a(%RIP){1to4},%YMM2,%YMM2{%K1}	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.40	vect (50.0%)
VMOVDQU %YMM2,0x1710(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
MOV 0x1730(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x3b8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $0x3fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x1,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV $0x7fffffffc0000000,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
AND %R8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
XOR 0x1018(%RSP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	scal (12.5%)
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
NEG %EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %ESI,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RDX,0x1730(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JMP 404c8b <main+0x19cb>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSS 0x8432(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %R9,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ac0 <nextafterf>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x30(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x38(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xb8(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $-0x66f74f21,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV 0x50(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP $0x270,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 404960 <main+0x16a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x3b8(%RSP,%RDX,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0xb,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x7,%EAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $-0x62d3a980,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0xf,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
AND $-0x103a0000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x12,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
XOR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VCVTUSI2SS %RAX,%XMM7,%XMM0	3	0.50	0.50	0	0	0	2	0	0	0	0	0	0	8	2	scal (12.5%)
VMULSS 0x83a2(%RIP),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VUCOMISS 0x8396(%RIP),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (6.3%)
JAE 404cf4 <main+0x1a34>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0xc0(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x1(%R9),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RDI,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 404280 <main+0xfc0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSS 0x8368(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %R9,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 406ac0 <nextafterf>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x30(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x38(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xb8(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $-0x66f74f21,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JMP 404cd4 <main+0x1a14>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

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ASM code

Code clean check

Workaround

Vectorization

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Execution units bottlenecks

Masked instructions

Details

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code