OV - attention-gnr-512 - Loop 44

	Loop Id: 44	Module: attention-gnr-512	Source: attention_v2.cpp:30-31	Coverage: 5.13%

0x404ea0 LEA	(%RAX,%RDI,1),%R8D

0x404ea4 VPBROADCASTD	%R8D,%YMM3

0x404eaa LEA	(%R14,%R15,1),%R8

0x404eae VPADDD	%YMM3,%YMM9,%YMM3

0x404eb2 VPXOR	%XMM4,%XMM4,%XMM4

0x404eb6 KXNORW	%K0,%K0,%K1

0x404eba VGATHERDPS	(%R8,%YMM3,4),%YMM4{%K1}    [2]

0x404ec1 VCVTPS2PD	%YMM4,%ZMM3

0x404ec7 VPBROADCASTD	%EDI,%YMM4

0x404ecd VPADDD	%YMM7,%YMM4,%YMM4

0x404ed1 VPMULLD	%YMM4,%YMM6,%YMM4

0x404ed6 VPADDD	%YMM4,%YMM2,%YMM4

0x404eda LEA	(%R9,%R15,1),%R8

0x404ede VPSUBD	%YMM8,%YMM4,%YMM4

0x404ee3 VPXOR	%XMM5,%XMM5,%XMM5

0x404ee7 KXNORW	%K0,%K0,%K1

0x404eeb VGATHERDPS	(%R8,%YMM4,4),%YMM5{%K1}    [1]

0x404ef2 VCVTPS2PD	%YMM5,%ZMM4

0x404ef8 VFMADD231PD	%ZMM4,%ZMM3,%ZMM1

0x404efe ADD	$0x8,%RDI

0x404f02 CMP	%RBX,%RDI

0x404f05 JB	404ea0

/home/eoseret/llm-attention/attention_v2.cpp: 30 - 31

--------------------------------------------------------------------------------

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.11
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.75
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.31
Bottlenecks	P0, P1, P5,
Function	main
Source	attention_v2.cpp:30-31
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00
CQA cycles if no scalar integer	6.33
CQA cycles if FP arith vectorized	7.00
CQA cycles if fully vectorized	4.00
Front-end cycles	5.33
P0 cycles	7.00
P1 cycles	7.00
P2 cycles	5.33
P3 cycles	5.33
P4 cycles	0.00
P5 cycles	7.00
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.00
P11 cycles	5.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	32.00
Nb loads	2.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.29
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.14
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	1.00
Vectorization ratio all	85.71
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	75.00
Vector-efficiency ratio all	43.75
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	32.81

Metric	Value
CQA speedup if no scalar integer	1.11
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.75
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.31
Bottlenecks	P0, P1, P5,
Function	main
Source	attention_v2.cpp:30-31
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00
CQA cycles if no scalar integer	6.33
CQA cycles if FP arith vectorized	7.00
CQA cycles if fully vectorized	4.00
Front-end cycles	5.33
P0 cycles	7.00
P1 cycles	7.00
P2 cycles	5.33
P3 cycles	5.33
P4 cycles	0.00
P5 cycles	7.00
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	1.00
P11 cycles	5.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	22.00
Nb uops	32.00
Nb loads	2.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	2.29
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.14
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	1.00
Vectorization ratio all	85.71
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	75.00
Vector-efficiency ratio all	43.75
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	32.81

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:30-31
Module	attention-gnr-512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:30-31.

The related source loop is multi-versionned.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.00 to 6.33 cycles (1.11x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 43% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 7.00 to 4.00 cycles (1.75x speedup).

Details

85% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

75% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 7.00 to 5.33 cycles (1.31x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 8 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
VGATHERDPS: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
VPMULLD: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

1 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is loading 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	22
nb uops	32
loop length	103
used x86 registers	7
used mmx registers	0
used xmm registers	2
used ymm registers	8
used zmm registers	3
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.33 cycles
front end	5.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.00	7.00	5.33	5.33	0.00	7.00	1.00	0.00	0.00	0.00	1.00	5.33
cycles	7.00	7.00	5.33	5.33	0.00	7.00	1.00	0.00	0.00	0.00	1.00	5.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	5.33
Dispatch	7.00
Data deps.	4.00
Overall L1	7.00

Vectorization ratios

INT

all	77%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	85%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	75%

Vector efficiency ratios

INT

all	34%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	15%

all	60%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	43%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	32%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

4% of peak load performance is reached (9.14 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 404ea0

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
LEA (%RAX,%RDI,1),%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VPBROADCASTD %R8D,%YMM3	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
LEA (%R14,%R15,1),%R8	1	0	0	0	0	0	0	0	0	0	0.17	N/A
VPADDD %YMM3,%YMM9,%YMM3	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPXOR %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R8,%YMM3,4),%YMM4{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VCVTPS2PD %YMM4,%ZMM3	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VPBROADCASTD %EDI,%YMM4	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
VPADDD %YMM7,%YMM4,%YMM4	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPMULLD %YMM4,%YMM6,%YMM4	2	1	1	0	0	0	0	0	0	10	1	vect (50.0%)
VPADDD %YMM4,%YMM2,%YMM4	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
LEA (%R9,%R15,1),%R8	1	0	0	0	0	0	0	0	0	0	0.17	N/A
VPSUBD %YMM8,%YMM4,%YMM4	1	0.33	0.33	0	0	0.33	0	0	0	0-1	0.33	vect (50.0%)
VPXOR %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R8,%YMM4,4),%YMM5{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VCVTPS2PD %YMM5,%ZMM4	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VFMADD231PD %ZMM4,%ZMM3,%ZMM1	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
ADD $0x8,%RDI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RBX,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JB 404ea0 <main+0x1be0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:30-31
Module	attention-gnr-512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:30-31.

The related source loop is multi-versionned.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.00 to 6.33 cycles (1.11x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

85% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

75% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 8 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
VGATHERDPS: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
VPMULLD: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31

Workaround

Type of elements and instruction set

1 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction (all inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is loading 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	22
nb uops	32
loop length	103
used x86 registers	7
used mmx registers	0
used xmm registers	2
used ymm registers	8
used zmm registers	3
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.33 cycles
front end	5.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.00	7.00	5.33	5.33	0.00	7.00	1.00	0.00	0.00	0.00	1.00	5.33
cycles	7.00	7.00	5.33	5.33	0.00	7.00	1.00	0.00	0.00	0.00	1.00	5.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	5.33
Dispatch	7.00
Data deps.	4.00
Overall L1	7.00

Vectorization ratios

INT

all	77%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	85%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	75%

Vector efficiency ratios

INT

all	34%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	15%

all	60%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	43%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	32%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

4% of peak load performance is reached (9.14 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 404ea0

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
LEA (%RAX,%RDI,1),%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VPBROADCASTD %R8D,%YMM3	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
LEA (%R14,%R15,1),%R8	1	0	0	0	0	0	0	0	0	0	0.17	N/A
VPADDD %YMM3,%YMM9,%YMM3	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPXOR %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R8,%YMM3,4),%YMM4{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VCVTPS2PD %YMM4,%ZMM3	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VPBROADCASTD %EDI,%YMM4	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
VPADDD %YMM7,%YMM4,%YMM4	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPMULLD %YMM4,%YMM6,%YMM4	2	1	1	0	0	0	0	0	0	10	1	vect (50.0%)
VPADDD %YMM4,%YMM2,%YMM4	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
LEA (%R9,%R15,1),%R8	1	0	0	0	0	0	0	0	0	0	0.17	N/A
VPSUBD %YMM8,%YMM4,%YMM4	1	0.33	0.33	0	0	0.33	0	0	0	0-1	0.33	vect (50.0%)
VPXOR %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VGATHERDPS (%R8,%YMM4,4),%YMM5{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VCVTPS2PD %YMM5,%ZMM4	2	1	0	0	0	1	0	0	0	7	1	vect (50.0%)
VFMADD231PD %ZMM4,%ZMM3,%ZMM1	1	0.50	0	0	0	0.50	0	0	0	4	0.50	vect (100.0%)
ADD $0x8,%RDI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RBX,%RDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JB 404ea0 <main+0x1be0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

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Workaround

Execution units bottlenecks

Workaround

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code