OV - attention-gnr-512 - Loop 43

	Loop Id: 43	Module: attention-gnr-512	Source: attention_v2.cpp:27-98 [...]	Coverage: 3.85%

0x404d90 VPBROADCASTQ	%RDI,%ZMM3

0x404d96 VMOVDQU64	0x2c0(%RSP),%ZMM4

0x404d9e VPSUBQ	%ZMM3,%ZMM4,%ZMM4

0x404da4 VPCMPNLEUQ	0x8451(%RIP),%ZMM4,%K1

0x404daf VPMOVQD	%ZMM3,%YMM3

0x404db5 VPADDD	0x8283(%RIP),%YMM3,%YMM3

0x404dbd VPADDD	%YMM3,%YMM0,%YMM4

0x404dc1 LEA	(%R14,%R15,1),%RDI

0x404dc5 VPBROADCASTD	0x8292(%RIP),%YMM6

0x404dce VPSUBD	%YMM6,%YMM4,%YMM4

0x404dd2 VXORPS	%XMM5,%XMM5,%XMM5

0x404dd6 KMOVQ	%K1,%K2

0x404ddb VGATHERDPS	(%RDI,%YMM4,4),%YMM5{%K2}

0x404de2 VPMULLD	0x200(%RSP),%YMM3,%YMM3

0x404dec VPADDD	%YMM3,%YMM2,%YMM2

0x404df0 LEA	(%R9,%R15,1),%RDI

0x404df4 VPSUBD	%YMM6,%YMM2,%YMM2

0x404df8 VPXOR	%XMM3,%XMM3,%XMM3

0x404dfc KMOVQ	%K1,%K2

0x404e01 VGATHERDPS	(%RDI,%YMM2,4),%YMM3{%K2}

0x404e08 VCVTPS2PD	%YMM5,%ZMM2

0x404e0e VCVTPS2PD	%YMM3,%ZMM3

0x404e14 VFMADD231PD	%ZMM2,%ZMM3,%ZMM1{%K1}

0x404e1a VEXTRACTF64X4	$0x1,%ZMM1,%YMM2

0x404e21 VADDPD	%ZMM2,%ZMM1,%ZMM1

0x404e27 VEXTRACTF128	$0x1,%YMM1,%XMM2

0x404e2d VADDPD	%XMM2,%XMM1,%XMM1

0x404e31 VSHUFPD	$0x1,%XMM1,%XMM1,%XMM2

0x404e36 VADDSD	%XMM2,%XMM1,%XMM1

0x404e3a VCVTSD2SS	%XMM1,%XMM1,%XMM1

0x404e3e LEA	(%RDX,%RSI,1),%EDI

0x404e41 MOV	0x70(%RSP),%R8

0x404e46 VMOVSS	%XMM1,(%R8,%RDI,4)

0x404e4c LEA	0x1(%RSI),%RDI

0x404e50 CMP	0x148(%RSP),%RSI

0x404e58 MOV	%RDI,%RSI

0x404e5b JE	404d60

0x404e61 VPBROADCASTD	%ESI,%YMM2

0x404e67 VXORPS	%XMM1,%XMM1,%XMM1

0x404e6b XOR	%EDI,%EDI

0x404e6d TEST	%RBX,%RBX

0x404e70 JE	404d90

0x404e76 VMOVDQU	0x200(%RSP),%YMM6

0x404e7f VPMOVSXBD	0x8400(%RIP),%YMM7

0x404e88 VPBROADCASTD	0x81cf(%RIP),%YMM8

0x404e91 VMOVDQU	0x8187(%RIP),%YMM9

0x404e99 NOPL	(%RAX)

  (44) 0x404ea0 LEA	(%RAX,%RDI,1),%R8D

  (44) 0x404ea4 VPBROADCASTD	%R8D,%YMM3

  (44) 0x404eaa LEA	(%R14,%R15,1),%R8

  (44) 0x404eae VPADDD	%YMM3,%YMM9,%YMM3

  (44) 0x404eb2 VPXOR	%XMM4,%XMM4,%XMM4

  (44) 0x404eb6 KXNORW	%K0,%K0,%K1

  (44) 0x404eba VGATHERDPS	(%R8,%YMM3,4),%YMM4{%K1}

  (44) 0x404ec1 VCVTPS2PD	%YMM4,%ZMM3

  (44) 0x404ec7 VPBROADCASTD	%EDI,%YMM4

  (44) 0x404ecd VPADDD	%YMM7,%YMM4,%YMM4

  (44) 0x404ed1 VPMULLD	%YMM4,%YMM6,%YMM4

  (44) 0x404ed6 VPADDD	%YMM4,%YMM2,%YMM4

  (44) 0x404eda LEA	(%R9,%R15,1),%R8

  (44) 0x404ede VPSUBD	%YMM8,%YMM4,%YMM4

  (44) 0x404ee3 VPXOR	%XMM5,%XMM5,%XMM5

  (44) 0x404ee7 KXNORW	%K0,%K0,%K1

  (44) 0x404eeb VGATHERDPS	(%R8,%YMM4,4),%YMM5{%K1}

  (44) 0x404ef2 VCVTPS2PD	%YMM5,%ZMM4

  (44) 0x404ef8 VFMADD231PD	%ZMM4,%ZMM3,%ZMM1

  (44) 0x404efe ADD	$0x8,%RDI

  (44) 0x404f02 CMP	%RBX,%RDI

  (44) 0x404f05 JB	404ea0

0x404f07 MOV	%RBX,%RDI

0x404f0a TESTB	$0x1,0xb0(%RSP)

0x404f12 JE	404d90

0x404f18 JMP	404e1a

/home/eoseret/llm-attention/attention_v2.cpp: 27 - 98

--------------------------------------------------------------------------------

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

[...]

98:    if (argc < 4) {

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.06
CQA speedup if FP arith vectorized	1.05
CQA speedup if fully vectorized	1.72
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-33,attention_v2.cpp:98-98
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.00
CQA cycles if no scalar integer	8.50
CQA cycles if FP arith vectorized	8.61
CQA cycles if fully vectorized	5.23
Front-end cycles	8.11
P0 cycles	8.37
P1 cycles	8.17
P2 cycles	6.22
P3 cycles	6.22
P4 cycles	0.50
P5 cycles	8.83
P6 cycles	2.83
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	2.80
P11 cycles	6.22
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	48.67
Nb loads	10.00
Nb stores	1.00
Nb stack references	4.33
FLOP/cycle	2.41
Nb FLOP add-sub	11.00
Nb FLOP mul	0.00
Nb FLOP fma	5.33
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.74
Bytes prefetched	0.00
Bytes loaded	240.67
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	69.07
Vectorization ratio load	70.00
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	81.48
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	59.40
Vector-efficiency ratio all	38.48
Vector-efficiency ratio load	41.13
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	51.39
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	30.03

Metric	Value
CQA speedup if no scalar integer	1.07
CQA speedup if FP arith vectorized	1.07
CQA speedup if fully vectorized	1.84
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P0,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-33,attention_v2.cpp:98-98
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.83
CQA cycles if no scalar integer	10.17
CQA cycles if FP arith vectorized	10.17
CQA cycles if fully vectorized	5.88
Front-end cycles	8.83
P0 cycles	10.83
P1 cycles	10.67
P2 cycles	7.33
P3 cycles	7.33
P4 cycles	0.50
P5 cycles	10.50
P6 cycles	2.00
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	2.00
P11 cycles	7.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	53.00
Nb loads	9.00
Nb stores	1.00
Nb stack references	4.00
FLOP/cycle	2.49
Nb FLOP add-sub	11.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.85
Bytes prefetched	0.00
Bytes loaded	276.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	76.67
Vectorization ratio load	75.00
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	88.89
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	70.59
Vector-efficiency ratio all	45.63
Vector-efficiency ratio load	52.34
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	54.17
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	36.76

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.64
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.61
Bottlenecks	micro-operation queue, P5,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-33,attention_v2.cpp:98-98
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	3.05
Front-end cycles	5.00
P0 cycles	3.10
P1 cycles	3.00
P2 cycles	2.33
P3 cycles	2.33
P4 cycles	0.50
P5 cycles	5.00
P6 cycles	2.90
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	3.00
P11 cycles	2.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	30.00
Nb loads	7.00
Nb stores	1.00
Nb stack references	4.00
FLOP/cycle	2.20
Nb FLOP add-sub	11.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.40
Bytes prefetched	0.00
Bytes loaded	93.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	56.25
Vectorization ratio load	60.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	66.67
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	44.44
Vector-efficiency ratio all	26.95
Vector-efficiency ratio load	26.25
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	45.83
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	19.44

Metric	Value
CQA speedup if no scalar integer	1.08
CQA speedup if FP arith vectorized	1.05
CQA speedup if fully vectorized	1.65
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P0,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-33,attention_v2.cpp:98-98
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.17
CQA cycles if no scalar integer	10.33
CQA cycles if FP arith vectorized	10.67
CQA cycles if fully vectorized	6.77
Front-end cycles	10.50
P0 cycles	11.17
P1 cycles	10.83
P2 cycles	9.00
P3 cycles	9.00
P4 cycles	0.50
P5 cycles	11.00
P6 cycles	3.60
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	3.40
P11 cycles	9.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	50.00
Nb uops	63.00
Nb loads	14.00
Nb stores	1.00
Nb stack references	5.00
FLOP/cycle	2.42
Nb FLOP add-sub	11.00
Nb FLOP mul	0.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	31.97
Bytes prefetched	0.00
Bytes loaded	353.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	74.29
Vectorization ratio load	75.00
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	88.89
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	63.16
Vector-efficiency ratio all	42.86
Vector-efficiency ratio load	44.79
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	54.17
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	33.88

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:27-98
Module	attention-gnr-512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:27-33,98.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:27,30-33,98.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 38% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 9.00 to 5.23 cycles (1.72x speedup).

Details

69% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

70% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
81% of SSE/AVX addition or subtraction instructions are used in vector version.
59% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 5.33 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 0 occurrences
VCVTSD2SS: 0 occurrences
VGATHERDPS: 0 occurrences
VPMULLD: 0 occurrences

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 0 occurrences

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 0 occurrences
VCVTSD2SS (FP64 to FP32, scalar): 0 occurrences
VPMOVQD: 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 1 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 21.666666666667 FP arithmetical operations:

16.33: addition or subtraction (5 inside FMA instructions)
5.33: multiply (all inside FMA instructions)

The binary loop is loading 240 bytes (30 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

General properties

nb instructions	40
nb uops	48.67
loop length	225
used x86 registers	8.67
used mmx registers	0
used xmm registers	3.33
used ymm registers	7.67
used zmm registers	3.33
nb stack references	4.33

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	8.11 cycles
front end	8.11 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.37	8.17	6.22	6.22	0.50	8.83	2.83	0.50	0.50	0.50	2.80	6.22
cycles	8.37	8.17	6.22	6.22	0.50	8.83	2.83	0.50	0.50	0.50	2.80	6.22

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	8.11
Dispatch	9.00
Data deps.	0.00
Overall L1	9.00

Vectorization ratios

INT

all	62%
load	65%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	75%
load	100%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	86%

INT+FP

all	69%
load	70%
store	0%
mul	100%
add-sub	81%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	59%

Vector efficiency ratios

INT

all	38%
load	41%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	58%
fma	NA (no fma vectorizable/vectorized instructions)
other	26%

all	37%
load	50%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	45%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

INT+FP

all	38%
load	41%
store	6%
mul	50%
add-sub	51%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.00 cycles. At this rate:

13% of peak load performance is reached (25.23 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.51 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	main
Source file and lines	attention_v2.cpp:27-98
Module	attention-gnr-512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.83 to 10.17 cycles (1.07x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 45% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 10.83 to 5.88 cycles (1.84x speedup).

Details

76% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

75% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
88% of SSE/AVX addition or subtraction instructions are used in vector version.
70% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 8 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
VCVTSD2SS: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33
VGATHERDPS: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
VPMULLD: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33
VPMOVQD: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31

Workaround

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 2 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 27 FP arithmetical operations:

19: addition or subtraction (8 inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is loading 276 bytes (34 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	42
nb uops	53
loop length	230
used x86 registers	9
used mmx registers	0
used xmm registers	4
used ymm registers	7
used zmm registers	4
nb stack references	4

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.83 cycles
front end	8.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	10.83	10.67	7.33	7.33	0.50	10.50	2.00	0.50	0.50	0.50	2.00	7.33
cycles	10.83	10.67	7.33	7.33	0.50	10.50	2.00	0.50	0.50	0.50	2.00	7.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	8.83
Dispatch	10.83
Data deps.	0.00
Overall L1	10.83

Vectorization ratios

INT

all	73%
load	66%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	42%

all	80%
load	100%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	90%

INT+FP

all	76%
load	75%
store	0%
mul	100%
add-sub	88%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	70%

Vector efficiency ratios

INT

all	50%
load	53%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	58%
fma	NA (no fma vectorizable/vectorized instructions)
other	37%

all	40%
load	50%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	45%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	36%

INT+FP

all	45%
load	52%
store	6%
mul	50%
add-sub	54%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	36%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.83 cycles. At this rate:

13% of peak load performance is reached (25.48 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.37 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 404e61

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VPBROADCASTQ %RDI,%ZMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVDQU64 0x2c0(%RSP),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VPSUBQ %ZMM3,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPCMPNLEUQ 0x8451(%RIP),%ZMM4,%K1																vect (100.0%)
VPMOVQD %ZMM3,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VPADDD 0x8283(%RIP),%YMM3,%YMM3	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPADDD %YMM3,%YMM0,%YMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
LEA (%R14,%R15,1),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTD 0x8292(%RIP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VPSUBD %YMM6,%YMM4,%YMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
VXORPS %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VGATHERDPS (%RDI,%YMM4,4),%YMM5{%K2}	5	1	1	2.67	2.67	0	1	0	0	0	0	0	2.67	29	3	vect (50.0%)
VPMULLD 0x200(%RSP),%YMM3,%YMM3	3	1	1	0.33	0.33	0	0	0	0	0	0	0	0.33	10	1	vect (50.0%)
VPADDD %YMM3,%YMM2,%YMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
LEA (%R9,%R15,1),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPSUBD %YMM6,%YMM2,%YMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
VPXOR %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VGATHERDPS (%RDI,%YMM2,4),%YMM3{%K2}	5	1	1	2.67	2.67	0	1	0	0	0	0	0	2.67	29	3	vect (50.0%)
VCVTPS2PD %YMM5,%ZMM2	2	1	0	0	0	0	1	0	0	0	0	0	0	7	1	vect (50.0%)
VCVTPS2PD %YMM3,%ZMM3	2	1	0	0	0	0	1	0	0	0	0	0	0	7	1	vect (50.0%)
VFMADD231PD %ZMM2,%ZMM3,%ZMM1{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM1,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM2,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM2,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM2,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VCVTSD2SS %XMM1,%XMM1,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA (%RDX,%RSI,1),%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV 0x70(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM1,(%R8,%RDI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x1(%RSI),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP 0x148(%RSP),%RSI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 404d60 <main+0x1aa0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPBROADCASTD %ESI,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %RBX,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 404d90 <main+0x1ad0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:27-98
Module	attention-gnr-512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 26% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 5.00 to 3.05 cycles (1.64x speedup).

Details

56% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

60% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
66% of SSE/AVX addition or subtraction instructions are used in vector version.
44% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.00 to 3.10 cycles (1.61x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33
VPMOVSXBD: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:30

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33
VPMOVSXBD: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:30

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 11 FP arithmetical operations:

11: addition or subtraction

The binary loop is loading 93 bytes (11 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	28
nb uops	30
loop length	156
used x86 registers	7
used mmx registers	0
used xmm registers	2
used ymm registers	6
used zmm registers	2
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.00 cycles
front end	5.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.10	3.00	2.33	2.33	0.50	5.00	2.90	0.50	0.50	0.50	3.00	2.33
cycles	3.10	3.00	2.33	2.33	0.50	5.00	2.90	0.50	0.50	0.50	3.00	2.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	5.00
Dispatch	5.00
Data deps.	0.00
Overall L1	5.00

Vectorization ratios

INT

all	42%
load	60%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	66%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	80%

INT+FP

all	56%
load	60%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	44%

Vector efficiency ratios

INT

all	21%
load	26%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	31%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

INT+FP

all	26%
load	26%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	45%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

9% of peak load performance is reached (18.60 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.80 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.00 to 3.10 cycles (1.61x speedup).

ASM code

In the binary file, the address of the loop is: 404e61

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VEXTRACTF64X4 $0x1,%ZMM1,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM2,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM2,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM2,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VCVTSD2SS %XMM1,%XMM1,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA (%RDX,%RSI,1),%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV 0x70(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM1,(%R8,%RDI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x1(%RSI),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP 0x148(%RSP),%RSI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 404d60 <main+0x1aa0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPBROADCASTD %ESI,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %RBX,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 404d90 <main+0x1ad0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVDQU 0x200(%RSP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VPMOVSXBD 0x8400(%RIP),%YMM7	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VPBROADCASTD 0x81cf(%RIP),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VMOVDQU 0x8187(%RIP),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TESTB $0x1,0xb0(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	2	0.33	N/A
JE 404d90 <main+0x1ad0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 404e1a <main+0x1b5a>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	main
Source file and lines	attention_v2.cpp:27-98
Module	attention-gnr-512

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.17 to 10.33 cycles (1.08x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 42% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 11.17 to 6.77 cycles (1.65x speedup).

Details

74% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

75% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
88% of SSE/AVX addition or subtraction instructions are used in vector version.
63% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck).

Workaround

Reduce the number of FP multiply/FMA instructions

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 8 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
VCVTSD2SS: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33
VGATHERDPS: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
VPMOVSXBD: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:30
VPMULLD: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33
VPMOVQD: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
VPMOVSXBD: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:30

Workaround

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 2 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 27 FP arithmetical operations:

19: addition or subtraction (8 inside FMA instructions)
8: multiply (all inside FMA instructions)

The binary loop is loading 353 bytes (44 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	50
nb uops	63
loop length	289
used x86 registers	10
used mmx registers	0
used xmm registers	4
used ymm registers	10
used zmm registers	4
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.50 cycles
front end	10.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	11.17	10.83	9.00	9.00	0.50	11.00	3.60	0.50	0.50	0.50	3.40	9.00
cycles	11.17	10.83	9.00	9.00	0.50	11.00	3.60	0.50	0.50	0.50	3.40	9.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	10.50
Dispatch	11.17
Data deps.	0.00
Overall L1	11.17

Vectorization ratios

INT

all	70%
load	70%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	33%

all	80%
load	100%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	66%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	90%

INT+FP

all	74%
load	75%
store	0%
mul	100%
add-sub	88%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	63%

Vector efficiency ratios

INT

all	44%
load	43%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	58%
fma	NA (no fma vectorizable/vectorized instructions)
other	31%

all	40%
load	50%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	45%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	36%

INT+FP

all	42%
load	44%
store	6%
mul	50%
add-sub	54%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.17 cycles. At this rate:

16% of peak load performance is reached (31.61 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.36 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 404e61

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VPBROADCASTQ %RDI,%ZMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VMOVDQU64 0x2c0(%RSP),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VPSUBQ %ZMM3,%ZMM4,%ZMM4	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPCMPNLEUQ 0x8451(%RIP),%ZMM4,%K1																vect (100.0%)
VPMOVQD %ZMM3,%YMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
VPADDD 0x8283(%RIP),%YMM3,%YMM3	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPADDD %YMM3,%YMM0,%YMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
LEA (%R14,%R15,1),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTD 0x8292(%RIP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VPSUBD %YMM6,%YMM4,%YMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
VXORPS %XMM5,%XMM5,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VGATHERDPS (%RDI,%YMM4,4),%YMM5{%K2}	5	1	1	2.67	2.67	0	1	0	0	0	0	0	2.67	29	3	vect (50.0%)
VPMULLD 0x200(%RSP),%YMM3,%YMM3	3	1	1	0.33	0.33	0	0	0	0	0	0	0	0.33	10	1	vect (50.0%)
VPADDD %YMM3,%YMM2,%YMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
LEA (%R9,%R15,1),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPSUBD %YMM6,%YMM2,%YMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
VPXOR %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KMOVQ %K1,%K2	1	1	0	0	0	0	0	0	0	0	0	0	0	0	1	N/A
VGATHERDPS (%RDI,%YMM2,4),%YMM3{%K2}	5	1	1	2.67	2.67	0	1	0	0	0	0	0	2.67	29	3	vect (50.0%)
VCVTPS2PD %YMM5,%ZMM2	2	1	0	0	0	0	1	0	0	0	0	0	0	7	1	vect (50.0%)
VCVTPS2PD %YMM3,%ZMM3	2	1	0	0	0	0	1	0	0	0	0	0	0	7	1	vect (50.0%)
VFMADD231PD %ZMM2,%ZMM3,%ZMM1{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM1,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM2,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM1,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM2,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM2,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
VCVTSD2SS %XMM1,%XMM1,%XMM1	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
LEA (%RDX,%RSI,1),%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV 0x70(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM1,(%R8,%RDI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x1(%RSI),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP 0x148(%RSP),%RSI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %RDI,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 404d60 <main+0x1aa0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPBROADCASTD %ESI,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %RBX,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 404d90 <main+0x1ad0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVDQU 0x200(%RSP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VPMOVSXBD 0x8400(%RIP),%YMM7	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VPBROADCASTD 0x81cf(%RIP),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VMOVDQU 0x8187(%RIP),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TESTB $0x1,0xb0(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	2	0.33	N/A
JE 404d90 <main+0x1ad0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Masked instructions

Details

Workaround

FMA

Complex instructions

Details

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Masked instructions

Details

Workaround

FMA

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties