OV - attention-gnr-512 - Loop 33

	Loop Id: 33	Module: attention-gnr-512	Source: attention_v2.cpp:237-238	Coverage: 0.27%

0x406100 VPBROADCASTQ	%RDX,%ZMM1

0x406106 VPADDQ	%ZMM6,%ZMM1,%ZMM2

0x40610c VPMULLQ	%ZMM2,%ZMM5,%ZMM2

0x406112 VPADDQ	%ZMM7,%ZMM1,%ZMM1

0x406118 VPADDQ	%ZMM0,%ZMM2,%ZMM2

0x40611e VMOVUPS	(%RAX,%RDX,4),%YMM3    [1]

0x406123 VMOVUPS	0x20(%RAX,%RDX,4),%YMM4    [1]

0x406129 KXNORW	%K0,%K0,%K1

0x40612d VSCATTERQPS	%YMM3,(%RSI,%ZMM2,4){%K1}    [2]

0x406134 VPMULLQ	%ZMM1,%ZMM5,%ZMM1

0x40613a VPADDQ	%ZMM0,%ZMM1,%ZMM1

0x406140 KXNORW	%K0,%K0,%K1

0x406144 VSCATTERQPS	%YMM4,(%RSI,%ZMM1,4){%K1}    [2]

0x40614b ADD	$0x10,%RDX

0x40614f CMP	%R8,%RDX

0x406152 JB	406100

/home/eoseret/llm-attention/attention_v2.cpp: 237 - 238

--------------------------------------------------------------------------------

237:          for (int j = 0; j < dim; ++j)// vectorized

238:             h_KT[j * context_size + i] = h_K[i * dim + j];

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.03
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.22
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:237-238
Source loop unroll info	unrolled by 32
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	32
CQA cycles	10.17
CQA cycles if no scalar integer	9.83
CQA cycles if FP arith vectorized	10.17
CQA cycles if fully vectorized	8.34
Front-end cycles	10.17
P0 cycles	8.50
P1 cycles	1.00
P2 cycles	0.67
P3 cycles	0.67
P4 cycles	8.00
P5 cycles	8.50
P6 cycles	1.00
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	1.00
P11 cycles	0.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	16.00
Nb uops	61.00
Nb loads	2.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.89
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	128.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	90.91
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	73.86
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.03
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.22
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:237-238
Source loop unroll info	unrolled by 32
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	32
CQA cycles	10.17
CQA cycles if no scalar integer	9.83
CQA cycles if FP arith vectorized	10.17
CQA cycles if fully vectorized	8.34
Front-end cycles	10.17
P0 cycles	8.50
P1 cycles	1.00
P2 cycles	0.67
P3 cycles	0.67
P4 cycles	8.00
P5 cycles	8.50
P6 cycles	1.00
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	1.00
P11 cycles	0.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	16.00
Nb uops	61.00
Nb loads	2.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.89
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	128.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	90.91
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	73.86
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:237-238
Module	attention-gnr-512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:237-238.

It is main loop of related source loop which is unrolled by 32 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 73% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 10.17 to 8.34 cycles (1.22x speedup).

Details

90% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPMULLQ: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:238
- /home/eoseret/llm-attention/attention_v2.cpp:238
VSCATTERQPS: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:238
- /home/eoseret/llm-attention/attention_v2.cpp:238

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 2 optimal vector unaligned load/store instructions.

Details

VMOVUPS: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:238
- /home/eoseret/llm-attention/attention_v2.cpp:238

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VSCATTERQPS: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:238
- /home/eoseret/llm-attention/attention_v2.cpp:238

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 128 bytes.

General properties

nb instructions	16
nb uops	61
loop length	84
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	2
used zmm registers	6
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.17 cycles
front end	10.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.50	1.00	0.67	0.67	8.00	8.50	1.00	8.00	8.00	8.00	1.00	0.67
cycles	8.50	1.00	0.67	0.67	8.00	8.50	1.00	8.00	8.00	8.00	1.00	0.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	10.17
Dispatch	8.50
Data deps.	1.00
Overall L1	10.17

Vectorization ratios

INT

all	85%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	90%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	87%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	73%
load	50%
store	50%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.17 cycles. At this rate:

3% of peak load performance is reached (6.30 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (12.59 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 10.17 to 8.50 cycles (1.20x speedup).

ASM code

In the binary file, the address of the loop is: 406100

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VPBROADCASTQ %RDX,%ZMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPADDQ %ZMM6,%ZMM1,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPMULLQ %ZMM2,%ZMM5,%ZMM2	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPADDQ %ZMM7,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM0,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMOVUPS (%RAX,%RDX,4),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0x20(%RAX,%RDX,4),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VSCATTERQPS %YMM3,(%RSI,%ZMM2,4){%K1}	20	2.20	0.20	0	0	4	0.20	0.20	4	4	4	0.20	0	2-12	7	vect (50.0%)
VPMULLQ %ZMM1,%ZMM5,%ZMM1	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPADDQ %ZMM0,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VSCATTERQPS %YMM4,(%RSI,%ZMM1,4){%K1}	20	2.20	0.20	0	0	4	0.20	0.20	4	4	4	0.20	0	2-12	7	vect (50.0%)
ADD $0x10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JB 406100 <main+0x2e40>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:237-238
Module	attention-gnr-512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:237-238.

It is main loop of related source loop which is unrolled by 32 (including vectorization).

gain
potential
hint
expert

Vectorization

Details

90% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPMULLQ: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:238
- /home/eoseret/llm-attention/attention_v2.cpp:238
VSCATTERQPS: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:238
- /home/eoseret/llm-attention/attention_v2.cpp:238

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 2 optimal vector unaligned load/store instructions.

Details

VMOVUPS: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:238
- /home/eoseret/llm-attention/attention_v2.cpp:238

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VSCATTERQPS: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:238
- /home/eoseret/llm-attention/attention_v2.cpp:238

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 128 bytes.

General properties

nb instructions	16
nb uops	61
loop length	84
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	2
used zmm registers	6
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.17 cycles
front end	10.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.50	1.00	0.67	0.67	8.00	8.50	1.00	8.00	8.00	8.00	1.00	0.67
cycles	8.50	1.00	0.67	0.67	8.00	8.50	1.00	8.00	8.00	8.00	1.00	0.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	10.17
Dispatch	8.50
Data deps.	1.00
Overall L1	10.17

Vectorization ratios

INT

all	85%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	90%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	87%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	73%
load	50%
store	50%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.17 cycles. At this rate:

3% of peak load performance is reached (6.30 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
9% of peak store performance is reached (12.59 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 406100

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VPBROADCASTQ %RDX,%ZMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPADDQ %ZMM6,%ZMM1,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPMULLQ %ZMM2,%ZMM5,%ZMM2	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPADDQ %ZMM7,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VPADDQ %ZMM0,%ZMM2,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
VMOVUPS (%RAX,%RDX,4),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0x20(%RAX,%RDX,4),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VSCATTERQPS %YMM3,(%RSI,%ZMM2,4){%K1}	20	2.20	0.20	0	0	4	0.20	0.20	4	4	4	0.20	0	2-12	7	vect (50.0%)
VPMULLQ %ZMM1,%ZMM5,%ZMM1	5	1.50	0	0	0	0	1.50	0	0	0	0	0	0	15	1.50	vect (100.0%)
VPADDQ %ZMM0,%ZMM1,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (100.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VSCATTERQPS %YMM4,(%RSI,%ZMM1,4){%K1}	20	2.20	0.20	0	0	4	0.20	0.20	4	4	4	0.20	0	2-12	7	vect (50.0%)
ADD $0x10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R8,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JB 406100 <main+0x2e40>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code