OV - attention-gnr-512 - Loop 23

	Loop Id: 23	Module: attention-gnr-512	Source: attention_v2.cpp:43-273 [...]	Coverage: 0.46%

0x4056b0 MOV	0xd0(%RSP),%RAX

0x4056b8 VMOVSS	%XMM19,(%RAX,%RDI,4)

0x4056bf MOV	0x130(%RSP),%RAX

0x4056c7 MOV	0x298(%RSP),%RDX

0x4056cf ADD	%RAX,%RDX

0x4056d2 MOV	0x290(%RSP),%RSI

0x4056da INC	%RSI

0x4056dd ADD	%RAX,0x1c8(%RSP)

0x4056e5 MOV	0x1f8(%RSP),%RCX

0x4056ed ADD	%RAX,%RCX

0x4056f0 MOV	%RCX,%RAX

0x4056f3 CMP	0x140(%RSP),%RDI

0x4056fb MOV	%R8,%RDI

0x4056fe JE	405ad0

0x405704 MOV	%RAX,0x1f8(%RSP)

0x40570c LEA	0x1(%RDI),%R8

0x405710 VMOVSS	0x794a(%RIP),%XMM16

0x40571a CMP	$0x8,%R8

0x40571e JB	405774

0x405720 MOV	%RSI,%RAX

0x405723 SHR	$0x3,%RAX

0x405727 MOV	%RDX,%RCX

0x40572a VMOVSS	0x7930(%RIP),%XMM16

0x405734 NOPW	%CS:(%RAX,%RAX,1)

  (27) 0x405740 VMAXSS	-0x1c(%RCX),%XMM16,%XMM0

  (27) 0x405747 VMAXSS	-0x18(%RCX),%XMM0,%XMM0

  (27) 0x40574c VMAXSS	-0x14(%RCX),%XMM0,%XMM0

  (27) 0x405751 VMAXSS	-0x10(%RCX),%XMM0,%XMM0

  (27) 0x405756 VMAXSS	-0xc(%RCX),%XMM0,%XMM0

  (27) 0x40575b VMAXSS	-0x8(%RCX),%XMM0,%XMM0

  (27) 0x405760 VMAXSS	-0x4(%RCX),%XMM0,%XMM0

  (27) 0x405765 VMAXSS	(%RCX),%XMM0,%XMM16

  (27) 0x40576b ADD	$0x20,%RCX

  (27) 0x40576f DEC	%RAX

  (27) 0x405772 JNE	405740

0x405774 MOV	%R8,%RAX

0x405777 AND	$-0x8,%RAX

0x40577b CMP	%R8,%RAX

0x40577e MOV	0x1c8(%RSP),%R12

0x405786 JE	40579f

0x405788 NOPL	(%RAX,%RAX,1)

  (26) 0x405790 VMAXSS	(%R12,%RAX,4),%XMM16,%XMM16

  (26) 0x405797 INC	%RAX

  (26) 0x40579a CMP	%RAX,%RSI

  (26) 0x40579d JNE	405790

0x40579f MOV	%RSI,0x290(%RSP)

0x4057a7 MOV	%RDX,0x298(%RSP)

0x4057af MOV	%R8,%RSI

0x4057b2 AND	$-0x10,%RSI

0x4057b6 VPBROADCASTQ	%RSI,%ZMM17

0x4057bc MOV	%RDI,0x30(%RSP)

0x4057c1 MOV	%R8,0x38(%RSP)

0x4057c6 MOV	%RSI,0xd8(%RSP)

0x4057ce VPBROADCASTQ	%R8,%ZMM19

0x4057d4 JE	405850

0x4057d6 DEC	%RSI

0x4057d9 MOV	0x78(%RSP),%RAX

0x4057de IMUL	%RDI,%RAX

0x4057e2 MOV	%RAX,0xf0(%RSP)

0x4057ea VBROADCASTSS	%XMM16,%ZMM20

0x4057f0 VXORPS	%XMM18,%XMM18,%XMM18

0x4057f6 XOR	%EDI,%EDI

0x4057f8 MOV	$0x406980,%R13

0x4057ff NOP

  (25) 0x405800 VMOVUPS	(%R12,%RDI,4),%ZMM0

  (25) 0x405807 VSUBPS	%ZMM20,%ZMM0,%ZMM0

  (25) 0x40580d CALL	%R13

  (25) 0x405810 VADDPS	%ZMM18,%ZMM0,%ZMM18

  (25) 0x405816 ADD	$0x10,%RDI

  (25) 0x40581a CMP	%RSI,%RDI

  (25) 0x40581d JLE	405800

0x40581f VPCMPEQQ	%ZMM17,%ZMM19,%K0

0x405825 KMOVD	%K0,%ECX

0x405829 MOV	0xd8(%RSP),%RSI

0x405831 MOV	%RSI,%RAX

0x405834 TEST	$0x1,%CL

0x405837 MOV	0x68(%RSP),%R13

0x40583c MOV	0x30(%RSP),%RDI

0x405841 MOV	0xf0(%RSP),%RCX

0x405849 JE	405867

0x40584b JMP	4058c2

0x405850 MOV	0x78(%RSP),%RCX

0x405855 IMUL	%RDI,%RCX

0x405859 VBROADCASTSS	%XMM16,%ZMM20

0x40585f VXORPS	%XMM18,%XMM18,%XMM18

0x405865 XOR	%EAX,%EAX

0x405867 VPBROADCASTQ	%RAX,%ZMM0

0x40586d VPSUBQ	%ZMM0,%ZMM19,%ZMM1

0x405873 VPSUBQ	%ZMM0,%ZMM19,%ZMM0

0x405879 VPCMPNLEUQ	0x797c(%RIP),%ZMM0,%K0

0x405884 VPCMPNLEUQ	0x79b1(%RIP),%ZMM1,%K1

0x40588f KUNPCKBW	%K0,%K1,%K1

0x405893 KMOVW	%K1,0xf0(%RSP)

0x40589c ADD	%RAX,%RCX

0x40589f VMOVUPS	(%R13,%RCX,4),%ZMM0{%K1}{z}

0x4058a7 VSUBPS	%ZMM20,%ZMM0,%ZMM1

0x4058ad CALL	406a20 <__svml_expf16_mask_z0>

0x4058b3 KMOVW	0xf0(%RSP),%K1

0x4058bc VADDPS	%ZMM0,%ZMM18,%ZMM18{%K1}

0x4058c2 VEXTRACTF64X4	$0x1,%ZMM18,%YMM0

0x4058c9 VADDPS	%ZMM0,%ZMM18,%ZMM0

0x4058cf VEXTRACTF128	$0x1,%YMM0,%XMM1

0x4058d5 VADDPS	%XMM1,%XMM0,%XMM0

0x4058d9 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x4058de VADDPS	%XMM1,%XMM0,%XMM0

0x4058e2 VMOVSHDUP	%XMM0,%XMM1

0x4058e6 VADDSS	%XMM1,%XMM0,%XMM19

0x4058ec VMOVSS	0x7774(%RIP),%XMM0

0x4058f4 VDIVSS	%XMM19,%XMM0,%XMM1

0x4058fa TEST	%RSI,%RSI

0x4058fd JE	4059c0

0x405903 DEC	%RSI

0x405906 MOV	0x78(%RSP),%RAX

0x40590b IMUL	%RDI,%RAX

0x40590f MOV	%RAX,0xf0(%RSP)

0x405917 VBROADCASTSS	%XMM16,%ZMM18

0x40591d VBROADCASTSS	%XMM1,%ZMM16

0x405923 XOR	%EDI,%EDI

0x405925 MOV	0x1f8(%RSP),%R12

0x40592d MOV	0x1c8(%RSP),%R13

0x405935 NOPW	%CS:(%RAX,%RAX,1)

  (24) 0x405940 VMOVUPS	(%R13,%RDI,4),%ZMM0

  (24) 0x405948 VSUBPS	%ZMM18,%ZMM0,%ZMM0

  (24) 0x40594e MOV	$0x406980,%RAX

  (24) 0x405955 CALL	%RAX

  (24) 0x405957 VMULPS	%ZMM16,%ZMM0,%ZMM0

  (24) 0x40595d VMOVUPS	%ZMM0,(%R12,%RDI,4)

  (24) 0x405964 ADD	$0x10,%RDI

  (24) 0x405968 CMP	%RSI,%RDI

  (24) 0x40596b JLE	405940

0x40596d MOV	0x38(%RSP),%R8

0x405972 VPBROADCASTQ	%R8,%ZMM0

0x405978 VPCMPEQQ	%ZMM17,%ZMM0,%K0

0x40597e KMOVD	%K0,%EAX

0x405982 TEST	$0x1,%AL

0x405984 MOV	0x68(%RSP),%R13

0x405989 MOV	0xc8(%RSP),%R12

0x405991 MOV	0x30(%RSP),%RDI

0x405996 MOV	0xd8(%RSP),%RAX

0x40599e MOV	0xf0(%RSP),%RSI

0x4059a6 JE	4059ea

0x4059a8 CMP	0x288(%RSP),%R8

0x4059b0 JAE	4056b0

0x4059b6 JMP	405a5f

0x4059c0 MOV	0x38(%RSP),%RAX

0x4059c5 VPBROADCASTQ	%RAX,%ZMM0

0x4059cb MOV	0x78(%RSP),%RSI

0x4059d0 IMUL	%RDI,%RSI

0x4059d4 VBROADCASTSS	%XMM16,%ZMM18

0x4059da VBROADCASTSS	%XMM1,%ZMM16

0x4059e0 XOR	%EAX,%EAX

0x4059e2 MOV	0xc8(%RSP),%R12

0x4059ea VPBROADCASTQ	%RAX,%ZMM1

0x4059f0 VPSUBQ	%ZMM1,%ZMM0,%ZMM2

0x4059f6 VPSUBQ	%ZMM1,%ZMM0,%ZMM0

0x4059fc VPCMPNLEUQ	0x77f9(%RIP),%ZMM0,%K0

0x405a07 VPCMPNLEUQ	0x782e(%RIP),%ZMM2,%K1

0x405a12 KUNPCKBW	%K0,%K1,%K1

0x405a16 KMOVW	%K1,0xd8(%RSP)

0x405a1f ADD	%RAX,%RSI

0x405a22 VMOVUPS	(%R13,%RSI,4),%ZMM0{%K1}{z}

0x405a2a VSUBPS	%ZMM18,%ZMM0,%ZMM1

0x405a30 CALL	406a20 <__svml_expf16_mask_z0>

0x405a36 MOV	0x38(%RSP),%R8

0x405a3b VMULPS	%ZMM16,%ZMM0,%ZMM0

0x405a41 KMOVW	0xd8(%RSP),%K1

0x405a4a VMOVUPS	%ZMM0,(%R12,%RSI,4){%K1}

0x405a51 CMP	0x288(%RSP),%R8

0x405a59 JAE	4056b0

0x405a5f MOV	0x270(%RSP),%RDI

0x405a67 IMUL	0x30(%RSP),%RDI

0x405a6d ADD	$0x4,%RDI

0x405a71 MOV	0x278(%RSP),%RDX

0x405a79 SUB	0x30(%RSP),%RDX

0x405a7e MOV	$0x3fffffffc,%RAX

0x405a88 AND	%RAX,%RDI

0x405a8b ADD	%R12,%RDI

0x405a8e SAL	$0x2,%RDX

0x405a92 AND	%RAX,%RDX

0x405a95 ADD	$0x4,%RDX

0x405a99 XOR	%ESI,%ESI

0x405a9b VMOVSS	%XMM19,0xd8(%RSP)

0x405aa3 VZEROUPPER

0x405aa6 CALL	407990 <_intel_fast_memset>

0x405aab VMOVSS	0xd8(%RSP),%XMM19

0x405ab3 MOV	0x38(%RSP),%R8

0x405ab8 MOV	0x30(%RSP),%RDI

0x405abd JMP	4056b0

/home/eoseret/llm-attention/attention_v2.cpp: 43 - 273

--------------------------------------------------------------------------------

43:    for (int row = 0; row < N; ++row) {

44:       const float *S_row = &S[row * N];

45:

46:       float max_val = -FLT_MAX;

47:       for (int idx = 0; idx <= row; ++idx) // vectorised

48:          if (S_row[idx] > max_val) max_val = S_row[idx];

49:

50:       float sum = 0.0f;

51: #pragma clang loop vectorize(enable)

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

54:

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

57:

58:       for (int idx = row + 1; idx < N; ++idx)

59:          P[row * N + idx] = 0.0f;

60:

61:       D[row] = sum;

[...]

98:    if (argc < 4) {

[...]

273:       start = std::chrono::steady_clock::now();

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.69
CQA speedup if FP arith vectorized	1.02
CQA speedup if fully vectorized	1.32
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.35
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:43-44,attention_v2.cpp:47-47,attention_v2.cpp:52-61,attention_v2.cpp:98-98,attention_v2.cpp:273-273
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	26.42
CQA cycles if fully vectorized	20.40
Front-end cycles	27.00
P0 cycles	13.50
P1 cycles	13.40
P2 cycles	14.33
P3 cycles	14.33
P4 cycles	8.50
P5 cycles	20.00
P6 cycles	13.50
P7 cycles	8.50
P8 cycles	8.50
P9 cycles	8.50
P10 cycles	13.60
P11 cycles	14.33
DIV/SQRT cycles	3.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	157.00
Nb uops	162.00
Nb loads	47.00
Nb stores	14.00
Nb stack references	17.00
FLOP/cycle	3.33
Nb FLOP add-sub	73.00
Nb FLOP mul	16.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.81
Bytes prefetched	0.00
Bytes loaded	684.00
Bytes stored	148.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	41.54
Vectorization ratio load	35.29
Vectorization ratio store	8.33
Vectorization ratio mul	100.00
Vectorization ratio add_sub	90.91
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	41.94
Vector-efficiency ratio all	37.31
Vector-efficiency ratio load	41.91
Vector-efficiency ratio store	18.75
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	77.84
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	31.45

Metric	Value
CQA speedup if no scalar integer	1.69
CQA speedup if FP arith vectorized	1.02
CQA speedup if fully vectorized	1.32
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.35
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:43-44,attention_v2.cpp:47-47,attention_v2.cpp:52-61,attention_v2.cpp:98-98,attention_v2.cpp:273-273
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	26.42
CQA cycles if fully vectorized	20.40
Front-end cycles	27.00
P0 cycles	13.50
P1 cycles	13.40
P2 cycles	14.33
P3 cycles	14.33
P4 cycles	8.50
P5 cycles	20.00
P6 cycles	13.50
P7 cycles	8.50
P8 cycles	8.50
P9 cycles	8.50
P10 cycles	13.60
P11 cycles	14.33
DIV/SQRT cycles	3.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	157.00
Nb uops	162.00
Nb loads	47.00
Nb stores	14.00
Nb stack references	17.00
FLOP/cycle	3.33
Nb FLOP add-sub	73.00
Nb FLOP mul	16.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.81
Bytes prefetched	0.00
Bytes loaded	684.00
Bytes stored	148.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	41.54
Vectorization ratio load	35.29
Vectorization ratio store	8.33
Vectorization ratio mul	100.00
Vectorization ratio add_sub	90.91
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	41.94
Vector-efficiency ratio all	37.31
Vector-efficiency ratio load	41.91
Vector-efficiency ratio store	18.75
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	77.84
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	31.45

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:43-273
Module	attention-gnr-512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:43-61,98,273.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:43-44,47,52-61,98,273.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 72 paths individually, rerun with max-paths=72
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 72 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 27.00 to 16.00 cycles (1.69x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 37% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 27.00 to 20.40 cycles (1.32x speedup).

Details

41% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

35% of SSE/AVX loads are used in vector version.
8% of SSE/AVX stores are used in vector version.
90% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
41% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. Estimated speedup by perfect pairing: 1.01x. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__svml_expf16_mask_z0: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:56
_intel_fast_memset: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:59

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:43
KMOVW: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:56
VZEROUPPER: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:59

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (four at a time). 5 AVX-512 instructions are processing arithmetic or math operations on single precision FP elements in vector mode (sixteen at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 90 FP arithmetical operations:

73: addition or subtraction
16: multiply
1: divide

The binary loop is loading 684 bytes (171 single precision FP elements). The binary loop is storing 148 bytes (37 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	157
nb uops	162
loop length	891
used x86 registers	9
used mmx registers	0
used xmm registers	5
used ymm registers	1
used zmm registers	8
nb stack references	17
ADD-SUB / MUL ratio	7.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	27.00 cycles
front end	27.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	13.50	13.40	14.33	14.33	8.50	20.00	13.50	8.50	8.50	8.50	13.60	14.33
cycles	13.50	13.40	14.33	14.33	8.50	20.00	13.50	8.50	8.50	8.50	13.60	14.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

3.00

Cycles summary

Front-end	27.00
Dispatch	20.00
DIV/SQRT	3.00
Overall L1	27.00

Vectorization ratios

INT

all	31%
load	36%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	36%

all	53%
load	33%
store	33%
mul	100%
add-sub	85%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	50%

INT+FP

all	41%
load	35%
store	8%
mul	100%
add-sub	90%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	41%

Vector efficiency ratios

INT

all	37%
load	44%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	40%

all	36%
load	37%
store	37%
mul	100%
add-sub	65%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	16%

INT+FP

all	37%
load	41%
store	18%
mul	100%
add-sub	77%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	31%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 27.00 cycles. At this rate:

13% of peak load performance is reached (25.33 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.48 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 27.00 to 20.00 cycles (1.35x speedup).

ASM code

In the binary file, the address of the loop is: 405704

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV 0xd0(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM19,(%RAX,%RDI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x130(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x298(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x290(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RAX,0x1c8(%RSP)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV 0x1f8(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP 0x140(%RSP),%RDI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %R8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 405ad0 <main+0x2810>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,0x1f8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x1(%RDI),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSS 0x794a(%RIP),%XMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
CMP $0x8,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 405774 <main+0x24b4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS 0x7930(%RIP),%XMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %R8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x1c8(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 40579f <main+0x24df>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,0x290(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,0x298(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x10,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VPBROADCASTQ %RSI,%ZMM17	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RDI,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0xd8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %R8,%ZMM19	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
JE 405850 <main+0x2590>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
DEC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x78(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RDI,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,0xf0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSS %XMM16,%ZMM20	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPS %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x406980,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPCMPEQQ %ZMM17,%ZMM19,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
KMOVD %K0,%ECX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0xd8(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST $0x1,%CL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV 0x68(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xf0(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 405867 <main+0x25a7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 4058c2 <main+0x2602>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV 0x78(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RDI,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VBROADCASTSS %XMM16,%ZMM20	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPS %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RAX,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %ZMM0,%ZMM19,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPSUBQ %ZMM0,%ZMM19,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPCMPNLEUQ 0x797c(%RIP),%ZMM0,%K0																vect (100.0%)
VPCMPNLEUQ 0x79b1(%RIP),%ZMM1,%K1																vect (100.0%)
KUNPCKBW %K0,%K1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KMOVW %K1,0xf0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPS (%R13,%RCX,4),%ZMM0{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPS %ZMM20,%ZMM0,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
CALL 406a20 <__svml_expf16_mask_z0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
KMOVW 0xf0(%RSP),%K1	3	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	N/A
VADDPS %ZMM0,%ZMM18,%ZMM18{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM18,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPS %ZMM0,%ZMM18,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
VADDSS %XMM1,%XMM0,%XMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VMOVSS 0x7774(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VDIVSS %XMM19,%XMM0,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	11-12	3	scal (6.3%)
TEST %RSI,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 4059c0 <main+0x2700>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
DEC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x78(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RDI,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,0xf0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSS %XMM16,%ZMM18	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM1,%ZMM16	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x1f8(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x1c8(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x38(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPBROADCASTQ %R8,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPCMPEQQ %ZMM17,%ZMM0,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
KMOVD %K0,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
TEST $0x1,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV 0x68(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xc8(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xd8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xf0(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 4059ea <main+0x272a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP 0x288(%RSP),%R8	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JAE 4056b0 <main+0x23f0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 405a5f <main+0x279f>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV 0x38(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VPBROADCASTQ %RAX,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV 0x78(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RDI,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VBROADCASTSS %XMM16,%ZMM18	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM1,%ZMM16	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xc8(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VPBROADCASTQ %RAX,%ZMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %ZMM1,%ZMM0,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPSUBQ %ZMM1,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPCMPNLEUQ 0x77f9(%RIP),%ZMM0,%K0																vect (100.0%)
VPCMPNLEUQ 0x782e(%RIP),%ZMM2,%K1																vect (100.0%)
KUNPCKBW %K0,%K1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KMOVW %K1,0xd8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPS (%R13,%RSI,4),%ZMM0{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPS %ZMM18,%ZMM0,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
CALL 406a20 <__svml_expf16_mask_z0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x38(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULPS %ZMM16,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
KMOVW 0xd8(%RSP),%K1	3	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	N/A
VMOVUPS %ZMM0,(%R12,%RSI,4){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
CMP 0x288(%RSP),%R8	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JAE 4056b0 <main+0x23f0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x270(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL 0x30(%RSP),%RDI	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
ADD $0x4,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x278(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB 0x30(%RSP),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV $0x3fffffffc,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
AND %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %R12,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SAL $0x2,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $0x4,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSS %XMM19,0xd8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407990 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSS 0xd8(%RSP),%XMM19	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x38(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 4056b0 <main+0x23f0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	main
Source file and lines	attention_v2.cpp:43-273
Module	attention-gnr-512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:43-61,98,273.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:43-44,47,52-61,98,273.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 72 paths individually, rerun with max-paths=72
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

41% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

35% of SSE/AVX loads are used in vector version.
8% of SSE/AVX stores are used in vector version.
90% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
41% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. Estimated speedup by perfect pairing: 1.01x. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

__svml_expf16_mask_z0: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:56
_intel_fast_memset: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:59

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:43
KMOVW: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:56
VZEROUPPER: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:59

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 90 FP arithmetical operations:

73: addition or subtraction
16: multiply
1: divide

The binary loop is loading 684 bytes (171 single precision FP elements). The binary loop is storing 148 bytes (37 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	157
nb uops	162
loop length	891
used x86 registers	9
used mmx registers	0
used xmm registers	5
used ymm registers	1
used zmm registers	8
nb stack references	17
ADD-SUB / MUL ratio	7.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	27.00 cycles
front end	27.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	13.50	13.40	14.33	14.33	8.50	20.00	13.50	8.50	8.50	8.50	13.60	14.33
cycles	13.50	13.40	14.33	14.33	8.50	20.00	13.50	8.50	8.50	8.50	13.60	14.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

3.00

Cycles summary

Front-end	27.00
Dispatch	20.00
DIV/SQRT	3.00
Overall L1	27.00

Vectorization ratios

INT

all	31%
load	36%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	36%

all	53%
load	33%
store	33%
mul	100%
add-sub	85%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	50%

INT+FP

all	41%
load	35%
store	8%
mul	100%
add-sub	90%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	41%

Vector efficiency ratios

INT

all	37%
load	44%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	40%

all	36%
load	37%
store	37%
mul	100%
add-sub	65%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	16%

INT+FP

all	37%
load	41%
store	18%
mul	100%
add-sub	77%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	31%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 27.00 cycles. At this rate:

13% of peak load performance is reached (25.33 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.48 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 405704

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV 0xd0(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM19,(%RAX,%RDI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x130(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x298(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x290(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RAX,0x1c8(%RSP)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV 0x1f8(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP 0x140(%RSP),%RDI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %R8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 405ad0 <main+0x2810>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,0x1f8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x1(%RDI),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSS 0x794a(%RIP),%XMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
CMP $0x8,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 405774 <main+0x24b4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS 0x7930(%RIP),%XMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %R8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x1c8(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 40579f <main+0x24df>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,0x290(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,0x298(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x10,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VPBROADCASTQ %RSI,%ZMM17	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %RDI,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0xd8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %R8,%ZMM19	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
JE 405850 <main+0x2590>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
DEC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x78(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RDI,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,0xf0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSS %XMM16,%ZMM20	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPS %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV $0x406980,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPCMPEQQ %ZMM17,%ZMM19,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
KMOVD %K0,%ECX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0xd8(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST $0x1,%CL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV 0x68(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xf0(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 405867 <main+0x25a7>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 4058c2 <main+0x2602>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV 0x78(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RDI,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VBROADCASTSS %XMM16,%ZMM20	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VXORPS %XMM18,%XMM18,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RAX,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %ZMM0,%ZMM19,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPSUBQ %ZMM0,%ZMM19,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPCMPNLEUQ 0x797c(%RIP),%ZMM0,%K0																vect (100.0%)
VPCMPNLEUQ 0x79b1(%RIP),%ZMM1,%K1																vect (100.0%)
KUNPCKBW %K0,%K1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KMOVW %K1,0xf0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPS (%R13,%RCX,4),%ZMM0{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPS %ZMM20,%ZMM0,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
CALL 406a20 <__svml_expf16_mask_z0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
KMOVW 0xf0(%RSP),%K1	3	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	N/A
VADDPS %ZMM0,%ZMM18,%ZMM18{%K1}	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM18,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPS %ZMM0,%ZMM18,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
VADDSS %XMM1,%XMM0,%XMM19	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VMOVSS 0x7774(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VDIVSS %XMM19,%XMM0,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	11-12	3	scal (6.3%)
TEST %RSI,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 4059c0 <main+0x2700>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
DEC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x78(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RDI,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,0xf0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSS %XMM16,%ZMM18	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM1,%ZMM16	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x1f8(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x1c8(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x38(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPBROADCASTQ %R8,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPCMPEQQ %ZMM17,%ZMM0,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (100.0%)
KMOVD %K0,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
TEST $0x1,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV 0x68(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xc8(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xd8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xf0(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 4059ea <main+0x272a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP 0x288(%RSP),%R8	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JAE 4056b0 <main+0x23f0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 405a5f <main+0x279f>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV 0x38(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VPBROADCASTQ %RAX,%ZMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV 0x78(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RDI,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VBROADCASTSS %XMM16,%ZMM18	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM1,%ZMM16	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xc8(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VPBROADCASTQ %RAX,%ZMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %ZMM1,%ZMM0,%ZMM2	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPSUBQ %ZMM1,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	0-1	0.50	vect (100.0%)
VPCMPNLEUQ 0x77f9(%RIP),%ZMM0,%K0																vect (100.0%)
VPCMPNLEUQ 0x782e(%RIP),%ZMM2,%K1																vect (100.0%)
KUNPCKBW %K0,%K1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KMOVW %K1,0xd8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPS (%R13,%RSI,4),%ZMM0{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPS %ZMM18,%ZMM0,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
CALL 406a20 <__svml_expf16_mask_z0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x38(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULPS %ZMM16,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	4	0.50	vect (100.0%)
KMOVW 0xd8(%RSP),%K1	3	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	N/A
VMOVUPS %ZMM0,(%R12,%RSI,4){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
CMP 0x288(%RSP),%R8	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JAE 4056b0 <main+0x23f0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x270(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL 0x30(%RSP),%RDI	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
ADD $0x4,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x278(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB 0x30(%RSP),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV $0x3fffffffc,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
AND %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %R12,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SAL $0x2,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $0x4,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSS %XMM19,0xd8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407990 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSS 0xd8(%RSP),%XMM19	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x38(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 4056b0 <main+0x23f0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

FMA

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

FMA

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code