OV - attention-clang-gnr512 - Loop 97 - attention-clang-gnr512

	Loop Id: 97	Module: attention-clang-gnr512	Source: attention_v2.cpp:163-164 [...]	Coverage: 0.17%

0x4450 VPXOR	%XMM0,%XMM0,%XMM0

0x4454 MOV	%RAX,%RCX

0x4457 VMOVSS	0x4bb5(%RIP),%XMM1

0x445f JMP	44d4

  (98) 0x4470 MOV	%RBX,%RDX

  (98) 0x4473 INC	%RBX

  (98) 0x4476 MOV	%RBX,0x1938(%RSP)

  (98) 0x447e MOV	0x5b8(%RSP,%RDX,8),%RDX

  (98) 0x4486 MOV	%RDX,%RSI

  (98) 0x4489 SHR	$0xb,%RSI

  (98) 0x448d MOV	%ESI,%ESI

  (98) 0x448f XOR	%RDX,%RSI

  (98) 0x4492 MOV	%ESI,%EDX

  (98) 0x4494 SAL	$0x7,%EDX

  (98) 0x4497 AND	$-0x62d3a980,%EDX

  (98) 0x449d XOR	%RSI,%RDX

  (98) 0x44a0 MOV	%EDX,%ESI

  (98) 0x44a2 SAL	$0xf,%ESI

  (98) 0x44a5 AND	$-0x103a0000,%ESI

  (98) 0x44ab XOR	%RDX,%RSI

  (98) 0x44ae MOV	%RSI,%RDX

  (98) 0x44b1 SHR	$0x12,%RDX

  (98) 0x44b5 XOR	%RSI,%RDX

  (98) 0x44b8 VCVTUSI2SS	%RDX,%XMM15,%XMM2

  (98) 0x44be VFMADD231SS	%XMM2,%XMM1,%XMM0

  (98) 0x44c3 VMULSS	0x4b3d(%RIP),%XMM1,%XMM1

  (98) 0x44cb DEC	%RCX

  (98) 0x44ce JE	4840

  (98) 0x44d4 CMP	$0x270,%RBX

  (98) 0x44db JB	4470

  (98) 0x44dd VPBROADCASTQ	%R13,%ZMM2

  (98) 0x44e3 XOR	%EDX,%EDX

  (98) 0x44e5 VPBROADCASTQ	0x4b51(%RIP),%ZMM14

  (98) 0x44ef VPBROADCASTQ	0x4b4f(%RIP),%ZMM15

  (98) 0x44f9 VPBROADCASTQ	0x4b4d(%RIP),%ZMM16

  (98) 0x4503 VPBROADCASTQ	0x4b4b(%RIP),%ZMM17

  (98) 0x450d NOPL	(%RAX)

    (99) 0x4510 VMOVDQU64	0x5c0(%RSP,%RDX,8),%ZMM3

    (99) 0x4518 VMOVDQU64	0x600(%RSP,%RDX,8),%ZMM4

    (99) 0x4520 VMOVDQU64	0x640(%RSP,%RDX,8),%ZMM5

    (99) 0x4528 VALIGNQ	$0x7,%ZMM2,%ZMM3,%ZMM6

    (99) 0x452f VMOVDQU64	0x680(%RSP,%RDX,8),%ZMM2

    (99) 0x4537 VALIGNQ	$0x7,%ZMM3,%ZMM4,%ZMM7

    (99) 0x453e VALIGNQ	$0x7,%ZMM4,%ZMM5,%ZMM8

    (99) 0x4545 VALIGNQ	$0x7,%ZMM5,%ZMM2,%ZMM9

    (99) 0x454c VPANDQ	%ZMM15,%ZMM3,%ZMM10

    (99) 0x4552 VPANDQ	%ZMM15,%ZMM4,%ZMM11

    (99) 0x4558 VPANDQ	%ZMM15,%ZMM5,%ZMM12

    (99) 0x455e VPANDQ	%ZMM15,%ZMM2,%ZMM13

    (99) 0x4564 VPTERNLOGQ	$-0x8,%ZMM14,%ZMM6,%ZMM10

    (99) 0x456b VPTERNLOGQ	$-0x8,%ZMM14,%ZMM7,%ZMM11

    (99) 0x4572 VPTERNLOGQ	$-0x8,%ZMM14,%ZMM8,%ZMM12

    (99) 0x4579 VPTERNLOGQ	$-0x8,%ZMM14,%ZMM9,%ZMM13

    (99) 0x4580 VPSRLQ	$0x1,%ZMM10,%ZMM6

    (99) 0x4587 VPSRLQ	$0x1,%ZMM11,%ZMM7

    (99) 0x458e VPSRLQ	$0x1,%ZMM12,%ZMM8

    (99) 0x4595 VPSRLQ	$0x1,%ZMM13,%ZMM9

    (99) 0x459c VPXORQ	0x1220(%RSP,%RDX,8),%ZMM6,%ZMM6

    (99) 0x45a7 VPXORQ	0x1260(%RSP,%RDX,8),%ZMM7,%ZMM7

    (99) 0x45b2 VPXORQ	0x12a0(%RSP,%RDX,8),%ZMM8,%ZMM8

    (99) 0x45bd VPXORQ	0x12e0(%RSP,%RDX,8),%ZMM9,%ZMM9

    (99) 0x45c8 VPTESTMQ	%ZMM16,%ZMM3,%K1

    (99) 0x45ce VPTESTMQ	%ZMM16,%ZMM4,%K2

    (99) 0x45d4 VPTESTMQ	%ZMM16,%ZMM5,%K3

    (99) 0x45da VPTESTMQ	%ZMM16,%ZMM2,%K4

    (99) 0x45e0 VPXORQ	%ZMM17,%ZMM6,%ZMM6{%K1}

    (99) 0x45e6 VPXORQ	%ZMM17,%ZMM7,%ZMM7{%K2}

    (99) 0x45ec VPXORQ	%ZMM17,%ZMM8,%ZMM8{%K3}

    (99) 0x45f2 VPXORQ	%ZMM17,%ZMM9,%ZMM9{%K4}

    (99) 0x45f8 VMOVDQU64	%ZMM6,0x5b8(%RSP,%RDX,8)

    (99) 0x4603 VMOVDQU64	%ZMM7,0x5f8(%RSP,%RDX,8)

    (99) 0x460e VMOVDQU64	%ZMM8,0x638(%RSP,%RDX,8)

    (99) 0x4619 VMOVDQU64	%ZMM9,0x678(%RSP,%RDX,8)

    (99) 0x4624 ADD	$0x20,%RDX

    (99) 0x4628 CMP	$0xe0,%RDX

    (99) 0x462f JNE	4510

  (98) 0x4635 VEXTRACTI32X4	$0x3,%ZMM2,%XMM2

  (98) 0x463c VPEXTRQ	$0x1,%XMM2,%RDI

  (98) 0x4642 AND	$-0x80000000,%RDI

  (98) 0x4649 MOV	0xcc0(%RSP),%RSI

  (98) 0x4651 MOV	0xcc8(%RSP),%RDX

  (98) 0x4659 MOV	%ESI,%R8D

  (98) 0x465c AND	$0x7ffffffe,%R8D

  (98) 0x4663 OR	%RDI,%R8

  (98) 0x4666 SHR	$0x1,%R8

  (98) 0x4669 XOR	0x1920(%RSP),%R8

  (98) 0x4671 MOV	%ESI,%EDI

  (98) 0x4673 AND	$0x1,%EDI

  (98) 0x4676 NEG	%EDI

  (98) 0x4678 AND	%R12D,%EDI

  (98) 0x467b XOR	%R8,%RDI

  (98) 0x467e MOV	%RDI,0xcb8(%RSP)

  (98) 0x4686 AND	$-0x80000000,%RSI

  (98) 0x468d MOV	%EDX,%EDI

  (98) 0x468f AND	$0x7ffffffe,%EDI

  (98) 0x4695 OR	%RSI,%RDI

  (98) 0x4698 SHR	$0x1,%RDI

  (98) 0x469b XOR	0x1928(%RSP),%RDI

  (98) 0x46a3 MOV	%EDX,%ESI

  (98) 0x46a5 AND	$0x1,%ESI

  (98) 0x46a8 NEG	%ESI

  (98) 0x46aa AND	%R12D,%ESI

  (98) 0x46ad XOR	%RDI,%RSI

  (98) 0x46b0 MOV	%RSI,0xcc0(%RSP)

  (98) 0x46b8 AND	$-0x80000000,%RDX

  (98) 0x46bf MOV	0xcd0(%RSP),%RSI

  (98) 0x46c7 MOV	%ESI,%EDI

  (98) 0x46c9 VPBROADCASTQ	%RSI,%XMM2

  (98) 0x46cf AND	$0x7ffffffe,%ESI

  (98) 0x46d5 OR	%RDX,%RSI

  (98) 0x46d8 SHR	$0x1,%RSI

  (98) 0x46db XOR	0x1930(%RSP),%RSI

  (98) 0x46e3 AND	$0x1,%EDI

  (98) 0x46e6 NEG	%EDI

  (98) 0x46e8 AND	%R12D,%EDI

  (98) 0x46eb XOR	%RSI,%RDI

  (98) 0x46ee MOV	%RDI,0xcc8(%RSP)

  (98) 0x46f6 MOV	$0xe8,%EDX

  (98) 0x46fb VPBROADCASTQ	0x493c(%RIP),%XMM7

  (98) 0x4704 VPBROADCASTQ	0x493b(%RIP),%XMM8

  (98) 0x470d VPBROADCASTQ	0x493a(%RIP),%XMM9

  (98) 0x4716 VPBROADCASTQ	0x4939(%RIP),%XMM10

  (98) 0x471f NOP

    (100) 0x4720 VMOVDQU	0x598(%RSP,%RDX,8),%XMM3

    (100) 0x4729 VMOVDQU	0x5a8(%RSP,%RDX,8),%XMM4

    (100) 0x4732 VPALIGNR	$0x8,%XMM2,%XMM3,%XMM2

    (100) 0x4738 VMOVDQU	0x5b8(%RSP,%RDX,8),%XMM5

    (100) 0x4741 VPAND	%XMM3,%XMM8,%XMM6

    (100) 0x4745 VPTERNLOGQ	$-0x8,%XMM7,%XMM2,%XMM6

    (100) 0x474c VPSRLQ	$0x1,%XMM6,%XMM2

    (100) 0x4751 VPXOR	-0x188(%RSP,%RDX,8),%XMM2,%XMM2

    (100) 0x475a VPTESTMQ	%XMM9,%XMM3,%K1

    (100) 0x4760 VPXORQ	%XMM10,%XMM2,%XMM2{%K1}

    (100) 0x4766 VMOVDQU	%XMM2,0x590(%RSP,%RDX,8)

    (100) 0x476f VPALIGNR	$0x8,%XMM3,%XMM4,%XMM2

    (100) 0x4775 VPAND	%XMM4,%XMM8,%XMM3

    (100) 0x4779 VPTERNLOGQ	$-0x8,%XMM7,%XMM2,%XMM3

    (100) 0x4780 VPSRLQ	$0x1,%XMM3,%XMM2

    (100) 0x4785 VPXOR	-0x178(%RSP,%RDX,8),%XMM2,%XMM2

    (100) 0x478e VPTESTMQ	%XMM9,%XMM4,%K1

    (100) 0x4794 VPXORQ	%XMM10,%XMM2,%XMM2{%K1}

    (100) 0x479a VMOVDQU	%XMM2,0x5a0(%RSP,%RDX,8)

    (100) 0x47a3 VPALIGNR	$0x8,%XMM4,%XMM5,%XMM2

    (100) 0x47a9 VPAND	%XMM5,%XMM8,%XMM3

    (100) 0x47ad VPTERNLOGQ	$-0x8,%XMM7,%XMM2,%XMM3

    (100) 0x47b4 VPSRLQ	$0x1,%XMM3,%XMM2

    (100) 0x47b9 VPXOR	-0x168(%RSP,%RDX,8),%XMM2,%XMM2

    (100) 0x47c2 VPTESTMQ	%XMM9,%XMM5,%K1

    (100) 0x47c8 VPXORQ	%XMM10,%XMM2,%XMM2{%K1}

    (100) 0x47ce VMOVDQU	%XMM2,0x5b0(%RSP,%RDX,8)

    (100) 0x47d7 ADD	$0x6,%RDX

    (100) 0x47db VMOVDQA	%XMM5,%XMM2

    (100) 0x47df CMP	$0x274,%RDX

    (100) 0x47e6 JNE	4720

  (98) 0x47ec MOV	0x1930(%RSP),%RDX

  (98) 0x47f4 MOV	$-0x80000000,%RSI

  (98) 0x47fb AND	%RSI,%RDX

  (98) 0x47fe MOV	0x5b8(%RSP),%R13

  (98) 0x4806 MOV	%R13D,%ESI

  (98) 0x4809 AND	$0x7ffffffe,%ESI

  (98) 0x480f OR	%RDX,%RSI

  (98) 0x4812 SHR	$0x1,%RSI

  (98) 0x4815 XOR	0x1218(%RSP),%RSI

  (98) 0x481d MOV	%R13D,%EDX

  (98) 0x4820 AND	$0x1,%EDX

  (98) 0x4823 NEG	%EDX

  (98) 0x4825 AND	%R12D,%EDX

  (98) 0x4828 XOR	%RSI,%RDX

  (98) 0x482b MOV	%RDX,0x1930(%RSP)

  (98) 0x4833 XOR	%EBX,%EBX

  (98) 0x4835 JMP	4470

0x4840 VDIVSS	%XMM1,%XMM0,%XMM0

0x4844 VUCOMISS	0x47c8(%RIP),%XMM0

0x484c JAE	486a

0x484e VMOVSS	%XMM0,(%R14,%R9,4)

0x4854 INC	%R9

0x4857 CMP	0xa0(%RSP),%R9

0x485f JNE	4450

0x486a VXORPS	%XMM1,%XMM1,%XMM1

0x486e VMOVSS	0x479e(%RIP),%XMM0

0x4876 MOV	%RAX,0x30(%RSP)

0x487b MOV	%R9,0x2c0(%RSP)

0x4883 VZEROUPPER

0x4886 CALL	10a0 <nextafterf@plt>

0x488b MOV	0x2c0(%RSP),%R9

0x4893 MOV	0x30(%RSP),%RAX

0x4898 JMP	484e

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath: 1661 - 1661

--------------------------------------------------------------------------------

1661:   { return __builtin_nextafterf(__x, __y); }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc: 401 - 3370

--------------------------------------------------------------------------------

401:       for (size_t __k = 0; __k < (__n - __m); ++__k)

402:         {

403: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

404: 			   | (_M_x[__k + 1] & __lower_mask));

405: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

406: 		       ^ ((__y & 0x01) ? __a : 0));

407:         }

408:

409:       for (size_t __k = (__n - __m); __k < (__n - 1); ++__k)

410: 	{

411: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

412: 			   | (_M_x[__k + 1] & __lower_mask));

413: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

414: 		       ^ ((__y & 0x01) ? __a : 0));

415: 	}

416:

417:       _UIntType __y = ((_M_x[__n - 1] & __upper_mask)

418: 		       | (_M_x[0] & __lower_mask));

419:       _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1)

420: 		       ^ ((__y & 0x01) ? __a : 0));

[...]

455:       if (_M_p >= state_size)

456: 	_M_gen_rand();

457:

458:       // Calculate o(x(i)).

459:       result_type __z = _M_x[_M_p++];

460:       __z ^= (__z >> __u) & __d;

461:       __z ^= (__z << __s) & __b;

462:       __z ^= (__z << __t) & __c;

463:       __z ^= (__z >> __l);

[...]

3364:       for (size_t __k = __m; __k != 0; --__k)

3365: 	{

3366: 	  __sum += _RealType(__urng() - __urng.min()) * __tmp;

3367: 	  __tmp *= __r;

3368: 	}

3369:       __ret = __sum / __tmp;

3370:       if (__builtin_expect(__ret >= _RealType(1), 0))

/home/eoseret/llm-attention/attention_v2.cpp: 163 - 164

--------------------------------------------------------------------------------

163:       for (size_t i = 0; i < elemsX; ++i) h_X[i] = dist(rng);

164:       for (size_t i = 0; i < elemsW; ++i) {

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.14
CQA speedup if FP arith vectorized	2.49
CQA speedup if fully vectorized	4.56
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.71
Bottlenecks
Function	main
Source	cmath:1661-1661,random.tcc:3369-3370,attention_v2.cpp:163-164
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.42
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	1.37
CQA cycles if fully vectorized	0.75
Front-end cycles	2.83
P0 cycles	2.00
P1 cycles	0.20
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	1.25
P5 cycles	0.20
P6 cycles	2.00
P7 cycles	1.25
P8 cycles	1.25
P9 cycles	1.25
P10 cycles	0.10
P11 cycles	1.50
DIV/SQRT cycles	3.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	15.50
Nb uops	17.00
Nb loads	4.50
Nb stores	2.00
Nb stack references	2.00
FLOP/cycle	0.29
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.64
Bytes prefetched	0.00
Bytes loaded	26.00
Bytes stored	12.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	20.83
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	46.67
Vector-efficiency ratio all	11.72
Vector-efficiency ratio load	7.03
Vector-efficiency ratio store	8.33
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	16.67

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.82
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P0,
Function	main
Source	cmath:1661-1661,random.tcc:3369-3370,attention_v2.cpp:163-164
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	1.06
CQA cycles if fully vectorized	0.75
Front-end cycles	1.83
P0 cycles	2.00
P1 cycles	0.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	0.50
P5 cycles	0.00
P6 cycles	2.00
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	0.00
P11 cycles	1.00
DIV/SQRT cycles	3.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	11.00
Nb loads	3.00
Nb stores	1.00
Nb stack references	1.00
FLOP/cycle	0.33
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.67
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	16.67
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	33.33
Vector-efficiency ratio all	10.42
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	14.58

Metric	Value
CQA speedup if no scalar integer	1.28
CQA speedup if FP arith vectorized	2.29
CQA speedup if fully vectorized	5.11
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	micro-operation queue,
Function	main
Source	cmath:1661-1661,random.tcc:3369-3370,attention_v2.cpp:163-164
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.83
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	1.68
CQA cycles if fully vectorized	0.75
Front-end cycles	3.83
P0 cycles	2.00
P1 cycles	0.40
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	0.40
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.20
P11 cycles	2.00
DIV/SQRT cycles	3.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	23.00
Nb loads	6.00
Nb stores	3.00
Nb stack references	3.00
FLOP/cycle	0.26
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.61
Bytes prefetched	0.00
Bytes loaded	36.00
Bytes stored	20.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	25.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	60.00
Vector-efficiency ratio all	13.02
Vector-efficiency ratio load	7.81
Vector-efficiency ratio store	10.42
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	18.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:163-164
Module	attention-clang-gnr512

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:401-420,455-463,3364-3370
/home/eoseret/llm-attention/attention_v2.cpp:163-164

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.42 to 0.75 cycles (4.56x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.42 to 2.83 cycles (1.21x speedup).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISS: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: divide

The binary loop is loading 26 bytes (6 single precision FP elements). The binary loop is storing 12 bytes (3 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	15.50
nb uops	17
loop length	78
used x86 registers	5
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	2.83 cycles
front end	2.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.00	0.20	1.50	1.50	1.25	0.20	2.00	1.25	1.25	1.25	0.10	1.50
cycles	2.00	0.20	1.50	1.50	1.25	0.20	2.00	1.25	1.25	1.25	0.10	1.50

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	3.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.83
Dispatch	2.00
DIV/SQRT	3.00
Data deps.	1.00
Overall L1	3.42

Vectorization ratios

INT

all	41%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	58%

all	8%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	25%

INT+FP

all	20%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	46%

Vector efficiency ratios

INT

all	17%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	19%

all	7%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

INT+FP

all	11%
load	7%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.42 cycles. At this rate:

3% of peak load performance is reached (7.36 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.28 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	main
Source file and lines	attention_v2.cpp:163-164
Module	attention-clang-gnr512

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:401-420,455-463,3364-3370
/home/eoseret/llm-attention/attention_v2.cpp:163-164

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.75 cycles (4.00x speedup).

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.00 to 2.00 cycles (1.50x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.00 to 1.83 cycles (1.64x speedup).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISS: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: divide

The binary loop is loading 16 bytes (4 single precision FP elements). The binary loop is storing 4 bytes (1 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	11
nb uops	11
loop length	54
used x86 registers	5
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	1.83 cycles
front end	1.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.00	0.00	1.00	1.00	0.50	0.00	2.00	0.50	0.50	0.50	0.00	1.00
cycles	2.00	0.00	1.00	1.00	0.50	0.00	2.00	0.50	0.50	0.50	0.00	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	3.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.83
Dispatch	2.00
DIV/SQRT	3.00
Data deps.	1.00
Overall L1	3.00

Vectorization ratios

INT

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

INT+FP

all	16%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	33%

Vector efficiency ratios

INT

all	18%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	6%

INT+FP

all	10%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

2% of peak load performance is reached (5.33 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4450

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVSS 0x4bb5(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
JMP 44d4 <main+0xc54>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
VDIVSS %XMM1,%XMM0,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	11-12	3	scal (6.3%)
VUCOMISS 0x47c8(%RIP),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (6.3%)
JAE 486a <main+0xfea>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSS %XMM0,(%R14,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
INC %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP 0xa0(%RSP),%R9	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JNE 4450 <main+0xbd0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:163-164
Module	attention-clang-gnr512

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:401-420,455-463,3364-3370
/home/eoseret/llm-attention/attention_v2.cpp:163-164

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.83 to 3.00 cycles (1.28x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.83 to 0.75 cycles (5.11x speedup).

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

nextafterf@plt: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISS: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370
VZEROUPPER: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: divide

The binary loop is loading 36 bytes (9 single precision FP elements). The binary loop is storing 20 bytes (5 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	20
nb uops	23
loop length	102
used x86 registers	5
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.83 cycles
front end	3.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.00	0.40	2.00	2.00	2.00	0.40	2.00	2.00	2.00	2.00	0.20	2.00
cycles	2.00	0.40	2.00	2.00	2.00	0.40	2.00	2.00	2.00	2.00	0.20	2.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	3.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.83
Dispatch	2.00
DIV/SQRT	3.00
Data deps.	1.00
Overall L1	3.83

Vectorization ratios

INT

all	33%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	66%

all	16%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	50%

INT+FP

all	25%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	60%

Vector efficiency ratios

INT

all	16%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	9%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	15%

INT+FP

all	13%
load	7%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.83 cycles. At this rate:

4% of peak load performance is reached (9.39 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.22 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 4450

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVSS 0x4bb5(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
JMP 44d4 <main+0xc54>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
VDIVSS %XMM1,%XMM0,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	11-12	3	scal (6.3%)
VUCOMISS 0x47c8(%RIP),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (6.3%)
JAE 486a <main+0xfea>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSS %XMM0,(%R14,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
INC %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP 0xa0(%RSP),%R9	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JNE 4450 <main+0xbd0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSS 0x479e(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %RAX,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,0x2c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 10a0 <nextafterf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x2c0(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 484e <main+0xfce>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code