OV - attention-clang-gnr512 - Loop 87 - attention-clang-gnr512

	Loop Id: 87	Module: attention-clang-gnr512	Source: attention_v2.cpp:164-167 [...]	Coverage: 0.17%

0x48b0 VXORPS	%XMM0,%XMM0,%XMM0

0x48b4 MOV	%R8,%RAX

0x48b7 VMOVSS	0x4755(%RIP),%XMM1

0x48bf JMP	4934

  (94) 0x48d0 MOV	%RBX,%RCX

  (94) 0x48d3 INC	%RBX

  (94) 0x48d6 MOV	%RBX,0x1938(%RSP)

  (94) 0x48de MOV	0x5b8(%RSP,%RCX,8),%RCX

  (94) 0x48e6 MOV	%RCX,%RDX

  (94) 0x48e9 SHR	$0xb,%RDX

  (94) 0x48ed MOV	%EDX,%EDX

  (94) 0x48ef XOR	%RCX,%RDX

  (94) 0x48f2 MOV	%EDX,%ECX

  (94) 0x48f4 SAL	$0x7,%ECX

  (94) 0x48f7 AND	$-0x62d3a980,%ECX

  (94) 0x48fd XOR	%RDX,%RCX

  (94) 0x4900 MOV	%ECX,%EDX

  (94) 0x4902 SAL	$0xf,%EDX

  (94) 0x4905 AND	$-0x103a0000,%EDX

  (94) 0x490b XOR	%RCX,%RDX

  (94) 0x490e MOV	%RDX,%RCX

  (94) 0x4911 SHR	$0x12,%RCX

  (94) 0x4915 XOR	%RDX,%RCX

  (94) 0x4918 VCVTUSI2SS	%RCX,%XMM15,%XMM2

  (94) 0x491e VFMADD231SS	%XMM2,%XMM1,%XMM0

  (94) 0x4923 VMULSS	0x46dd(%RIP),%XMM1,%XMM1

  (94) 0x492b DEC	%RAX

  (94) 0x492e JE	4ca0

  (94) 0x4934 CMP	$0x270,%RBX

  (94) 0x493b JB	48d0

  (94) 0x493d VPBROADCASTQ	%R13,%ZMM2

  (94) 0x4943 XOR	%ECX,%ECX

  (94) 0x4945 VPBROADCASTQ	0x46f1(%RIP),%ZMM14

  (94) 0x494f VPBROADCASTQ	0x46ef(%RIP),%ZMM15

  (94) 0x4959 VPBROADCASTQ	0x46ed(%RIP),%ZMM16

  (94) 0x4963 VPBROADCASTQ	0x46eb(%RIP),%ZMM17

  (94) 0x496d NOPL	(%RAX)

    (95) 0x4970 VMOVDQU64	0x5c0(%RSP,%RCX,8),%ZMM3

    (95) 0x4978 VMOVDQU64	0x600(%RSP,%RCX,8),%ZMM4

    (95) 0x4980 VMOVDQU64	0x640(%RSP,%RCX,8),%ZMM5

    (95) 0x4988 VALIGNQ	$0x7,%ZMM2,%ZMM3,%ZMM6

    (95) 0x498f VMOVDQU64	0x680(%RSP,%RCX,8),%ZMM2

    (95) 0x4997 VALIGNQ	$0x7,%ZMM3,%ZMM4,%ZMM7

    (95) 0x499e VALIGNQ	$0x7,%ZMM4,%ZMM5,%ZMM8

    (95) 0x49a5 VALIGNQ	$0x7,%ZMM5,%ZMM2,%ZMM9

    (95) 0x49ac VPANDQ	%ZMM15,%ZMM3,%ZMM10

    (95) 0x49b2 VPANDQ	%ZMM15,%ZMM4,%ZMM11

    (95) 0x49b8 VPANDQ	%ZMM15,%ZMM5,%ZMM12

    (95) 0x49be VPANDQ	%ZMM15,%ZMM2,%ZMM13

    (95) 0x49c4 VPTERNLOGQ	$-0x8,%ZMM14,%ZMM6,%ZMM10

    (95) 0x49cb VPTERNLOGQ	$-0x8,%ZMM14,%ZMM7,%ZMM11

    (95) 0x49d2 VPTERNLOGQ	$-0x8,%ZMM14,%ZMM8,%ZMM12

    (95) 0x49d9 VPTERNLOGQ	$-0x8,%ZMM14,%ZMM9,%ZMM13

    (95) 0x49e0 VPSRLQ	$0x1,%ZMM10,%ZMM6

    (95) 0x49e7 VPSRLQ	$0x1,%ZMM11,%ZMM7

    (95) 0x49ee VPSRLQ	$0x1,%ZMM12,%ZMM8

    (95) 0x49f5 VPSRLQ	$0x1,%ZMM13,%ZMM9

    (95) 0x49fc VPXORQ	0x1220(%RSP,%RCX,8),%ZMM6,%ZMM6

    (95) 0x4a07 VPXORQ	0x1260(%RSP,%RCX,8),%ZMM7,%ZMM7

    (95) 0x4a12 VPXORQ	0x12a0(%RSP,%RCX,8),%ZMM8,%ZMM8

    (95) 0x4a1d VPXORQ	0x12e0(%RSP,%RCX,8),%ZMM9,%ZMM9

    (95) 0x4a28 VPTESTMQ	%ZMM16,%ZMM3,%K1

    (95) 0x4a2e VPTESTMQ	%ZMM16,%ZMM4,%K2

    (95) 0x4a34 VPTESTMQ	%ZMM16,%ZMM5,%K3

    (95) 0x4a3a VPTESTMQ	%ZMM16,%ZMM2,%K4

    (95) 0x4a40 VPXORQ	%ZMM17,%ZMM6,%ZMM6{%K1}

    (95) 0x4a46 VPXORQ	%ZMM17,%ZMM7,%ZMM7{%K2}

    (95) 0x4a4c VPXORQ	%ZMM17,%ZMM8,%ZMM8{%K3}

    (95) 0x4a52 VPXORQ	%ZMM17,%ZMM9,%ZMM9{%K4}

    (95) 0x4a58 VMOVDQU64	%ZMM6,0x5b8(%RSP,%RCX,8)

    (95) 0x4a63 VMOVDQU64	%ZMM7,0x5f8(%RSP,%RCX,8)

    (95) 0x4a6e VMOVDQU64	%ZMM8,0x638(%RSP,%RCX,8)

    (95) 0x4a79 VMOVDQU64	%ZMM9,0x678(%RSP,%RCX,8)

    (95) 0x4a84 ADD	$0x20,%RCX

    (95) 0x4a88 CMP	$0xe0,%RCX

    (95) 0x4a8f JNE	4970

  (94) 0x4a95 VEXTRACTI32X4	$0x3,%ZMM2,%XMM2

  (94) 0x4a9c VPEXTRQ	$0x1,%XMM2,%RSI

  (94) 0x4aa2 AND	$-0x80000000,%RSI

  (94) 0x4aa9 MOV	0xcc0(%RSP),%RDX

  (94) 0x4ab1 MOV	0xcc8(%RSP),%RCX

  (94) 0x4ab9 MOV	%EDX,%EDI

  (94) 0x4abb AND	$0x7ffffffe,%EDI

  (94) 0x4ac1 OR	%RSI,%RDI

  (94) 0x4ac4 SHR	$0x1,%RDI

  (94) 0x4ac7 XOR	0x1920(%RSP),%RDI

  (94) 0x4acf MOV	%EDX,%ESI

  (94) 0x4ad1 AND	$0x1,%ESI

  (94) 0x4ad4 NEG	%ESI

  (94) 0x4ad6 AND	%R12D,%ESI

  (94) 0x4ad9 XOR	%RDI,%RSI

  (94) 0x4adc MOV	%RSI,0xcb8(%RSP)

  (94) 0x4ae4 AND	$-0x80000000,%RDX

  (94) 0x4aeb MOV	%ECX,%ESI

  (94) 0x4aed AND	$0x7ffffffe,%ESI

  (94) 0x4af3 OR	%RDX,%RSI

  (94) 0x4af6 SHR	$0x1,%RSI

  (94) 0x4af9 XOR	0x1928(%RSP),%RSI

  (94) 0x4b01 MOV	%ECX,%EDX

  (94) 0x4b03 AND	$0x1,%EDX

  (94) 0x4b06 NEG	%EDX

  (94) 0x4b08 AND	%R12D,%EDX

  (94) 0x4b0b XOR	%RSI,%RDX

  (94) 0x4b0e MOV	%RDX,0xcc0(%RSP)

  (94) 0x4b16 AND	$-0x80000000,%RCX

  (94) 0x4b1d MOV	0xcd0(%RSP),%RDX

  (94) 0x4b25 MOV	%EDX,%ESI

  (94) 0x4b27 VPBROADCASTQ	%RDX,%XMM2

  (94) 0x4b2d AND	$0x7ffffffe,%EDX

  (94) 0x4b33 OR	%RCX,%RDX

  (94) 0x4b36 SHR	$0x1,%RDX

  (94) 0x4b39 XOR	0x1930(%RSP),%RDX

  (94) 0x4b41 AND	$0x1,%ESI

  (94) 0x4b44 NEG	%ESI

  (94) 0x4b46 AND	%R12D,%ESI

  (94) 0x4b49 XOR	%RDX,%RSI

  (94) 0x4b4c MOV	%RSI,0xcc8(%RSP)

  (94) 0x4b54 MOV	$0xe8,%ECX

  (94) 0x4b59 VPBROADCASTQ	0x44de(%RIP),%XMM7

  (94) 0x4b62 VPBROADCASTQ	0x44dd(%RIP),%XMM8

  (94) 0x4b6b VPBROADCASTQ	0x44dc(%RIP),%XMM9

  (94) 0x4b74 VPBROADCASTQ	0x44db(%RIP),%XMM10

  (94) 0x4b7d NOPL	(%RAX)

    (96) 0x4b80 VMOVDQU	0x598(%RSP,%RCX,8),%XMM3

    (96) 0x4b89 VMOVDQU	0x5a8(%RSP,%RCX,8),%XMM4

    (96) 0x4b92 VPALIGNR	$0x8,%XMM2,%XMM3,%XMM2

    (96) 0x4b98 VMOVDQU	0x5b8(%RSP,%RCX,8),%XMM5

    (96) 0x4ba1 VPAND	%XMM3,%XMM8,%XMM6

    (96) 0x4ba5 VPTERNLOGQ	$-0x8,%XMM7,%XMM2,%XMM6

    (96) 0x4bac VPSRLQ	$0x1,%XMM6,%XMM2

    (96) 0x4bb1 VPXOR	-0x188(%RSP,%RCX,8),%XMM2,%XMM2

    (96) 0x4bba VPTESTMQ	%XMM9,%XMM3,%K1

    (96) 0x4bc0 VPXORQ	%XMM10,%XMM2,%XMM2{%K1}

    (96) 0x4bc6 VMOVDQU	%XMM2,0x590(%RSP,%RCX,8)

    (96) 0x4bcf VPALIGNR	$0x8,%XMM3,%XMM4,%XMM2

    (96) 0x4bd5 VPAND	%XMM4,%XMM8,%XMM3

    (96) 0x4bd9 VPTERNLOGQ	$-0x8,%XMM7,%XMM2,%XMM3

    (96) 0x4be0 VPSRLQ	$0x1,%XMM3,%XMM2

    (96) 0x4be5 VPXOR	-0x178(%RSP,%RCX,8),%XMM2,%XMM2

    (96) 0x4bee VPTESTMQ	%XMM9,%XMM4,%K1

    (96) 0x4bf4 VPXORQ	%XMM10,%XMM2,%XMM2{%K1}

    (96) 0x4bfa VMOVDQU	%XMM2,0x5a0(%RSP,%RCX,8)

    (96) 0x4c03 VPALIGNR	$0x8,%XMM4,%XMM5,%XMM2

    (96) 0x4c09 VPAND	%XMM5,%XMM8,%XMM3

    (96) 0x4c0d VPTERNLOGQ	$-0x8,%XMM7,%XMM2,%XMM3

    (96) 0x4c14 VPSRLQ	$0x1,%XMM3,%XMM2

    (96) 0x4c19 VPXOR	-0x168(%RSP,%RCX,8),%XMM2,%XMM2

    (96) 0x4c22 VPTESTMQ	%XMM9,%XMM5,%K1

    (96) 0x4c28 VPXORQ	%XMM10,%XMM2,%XMM2{%K1}

    (96) 0x4c2e VMOVDQU	%XMM2,0x5b0(%RSP,%RCX,8)

    (96) 0x4c37 ADD	$0x6,%RCX

    (96) 0x4c3b VMOVDQA	%XMM5,%XMM2

    (96) 0x4c3f CMP	$0x274,%RCX

    (96) 0x4c46 JNE	4b80

  (94) 0x4c4c MOV	0x1930(%RSP),%RCX

  (94) 0x4c54 MOV	$-0x80000000,%RDX

  (94) 0x4c5b AND	%RDX,%RCX

  (94) 0x4c5e MOV	0x5b8(%RSP),%R13

  (94) 0x4c66 MOV	%R13D,%EDX

  (94) 0x4c69 AND	$0x7ffffffe,%EDX

  (94) 0x4c6f OR	%RCX,%RDX

  (94) 0x4c72 SHR	$0x1,%RDX

  (94) 0x4c75 XOR	0x1218(%RSP),%RDX

  (94) 0x4c7d MOV	%R13D,%ECX

  (94) 0x4c80 AND	$0x1,%ECX

  (94) 0x4c83 NEG	%ECX

  (94) 0x4c85 AND	%R12D,%ECX

  (94) 0x4c88 XOR	%RDX,%RCX

  (94) 0x4c8b MOV	%RCX,0x1930(%RSP)

  (94) 0x4c93 XOR	%EBX,%EBX

  (94) 0x4c95 JMP	48d0

0x4ca0 VDIVSS	%XMM1,%XMM0,%XMM0

0x4ca4 VMOVSS	0x4368(%RIP),%XMM2

0x4cac VUCOMISS	%XMM2,%XMM0

0x4cb0 JAE	54e6

0x4cb6 VMOVSS	%XMM0,(%R15,%R9,4)

0x4cbc VXORPS	%XMM0,%XMM0,%XMM0

0x4cc0 MOV	%R8,%RAX

0x4cc3 VMOVAPS	%XMM2,%XMM1

0x4cc7 JMP	4d34

  (91) 0x4cd0 MOV	%RBX,%RCX

  (91) 0x4cd3 INC	%RBX

  (91) 0x4cd6 MOV	%RBX,0x1938(%RSP)

  (91) 0x4cde MOV	0x5b8(%RSP,%RCX,8),%RCX

  (91) 0x4ce6 MOV	%RCX,%RDX

  (91) 0x4ce9 SHR	$0xb,%RDX

  (91) 0x4ced MOV	%EDX,%EDX

  (91) 0x4cef XOR	%RCX,%RDX

  (91) 0x4cf2 MOV	%EDX,%ECX

  (91) 0x4cf4 SAL	$0x7,%ECX

  (91) 0x4cf7 AND	$-0x62d3a980,%ECX

  (91) 0x4cfd XOR	%RDX,%RCX

  (91) 0x4d00 MOV	%ECX,%EDX

  (91) 0x4d02 SAL	$0xf,%EDX

  (91) 0x4d05 AND	$-0x103a0000,%EDX

  (91) 0x4d0b XOR	%RCX,%RDX

  (91) 0x4d0e MOV	%RDX,%RCX

  (91) 0x4d11 SHR	$0x12,%RCX

  (91) 0x4d15 XOR	%RDX,%RCX

  (91) 0x4d18 VCVTUSI2SS	%RCX,%XMM15,%XMM2

  (91) 0x4d1e VFMADD231SS	%XMM2,%XMM1,%XMM0

  (91) 0x4d23 VMULSS	0x42dd(%RIP),%XMM1,%XMM1

  (91) 0x4d2b DEC	%RAX

  (91) 0x4d2e JE	50a0

  (91) 0x4d34 CMP	$0x270,%RBX

  (91) 0x4d3b JB	4cd0

  (91) 0x4d3d VPBROADCASTQ	%R13,%ZMM2

  (91) 0x4d43 XOR	%ECX,%ECX

  (91) 0x4d45 VPBROADCASTQ	0x42f1(%RIP),%ZMM14

  (91) 0x4d4f VPBROADCASTQ	0x42ef(%RIP),%ZMM15

  (91) 0x4d59 VPBROADCASTQ	0x42ed(%RIP),%ZMM16

  (91) 0x4d63 VPBROADCASTQ	0x42eb(%RIP),%ZMM17

  (91) 0x4d6d NOPL	(%RAX)

    (92) 0x4d70 VMOVDQU64	0x5c0(%RSP,%RCX,8),%ZMM3

    (92) 0x4d78 VMOVDQU64	0x600(%RSP,%RCX,8),%ZMM4

    (92) 0x4d80 VMOVDQU64	0x640(%RSP,%RCX,8),%ZMM5

    (92) 0x4d88 VALIGNQ	$0x7,%ZMM2,%ZMM3,%ZMM6

    (92) 0x4d8f VMOVDQU64	0x680(%RSP,%RCX,8),%ZMM2

    (92) 0x4d97 VALIGNQ	$0x7,%ZMM3,%ZMM4,%ZMM7

    (92) 0x4d9e VALIGNQ	$0x7,%ZMM4,%ZMM5,%ZMM8

    (92) 0x4da5 VALIGNQ	$0x7,%ZMM5,%ZMM2,%ZMM9

    (92) 0x4dac VPANDQ	%ZMM15,%ZMM3,%ZMM10

    (92) 0x4db2 VPANDQ	%ZMM15,%ZMM4,%ZMM11

    (92) 0x4db8 VPANDQ	%ZMM15,%ZMM5,%ZMM12

    (92) 0x4dbe VPANDQ	%ZMM15,%ZMM2,%ZMM13

    (92) 0x4dc4 VPTERNLOGQ	$-0x8,%ZMM14,%ZMM6,%ZMM10

    (92) 0x4dcb VPTERNLOGQ	$-0x8,%ZMM14,%ZMM7,%ZMM11

    (92) 0x4dd2 VPTERNLOGQ	$-0x8,%ZMM14,%ZMM8,%ZMM12

    (92) 0x4dd9 VPTERNLOGQ	$-0x8,%ZMM14,%ZMM9,%ZMM13

    (92) 0x4de0 VPSRLQ	$0x1,%ZMM10,%ZMM6

    (92) 0x4de7 VPSRLQ	$0x1,%ZMM11,%ZMM7

    (92) 0x4dee VPSRLQ	$0x1,%ZMM12,%ZMM8

    (92) 0x4df5 VPSRLQ	$0x1,%ZMM13,%ZMM9

    (92) 0x4dfc VPXORQ	0x1220(%RSP,%RCX,8),%ZMM6,%ZMM6

    (92) 0x4e07 VPXORQ	0x1260(%RSP,%RCX,8),%ZMM7,%ZMM7

    (92) 0x4e12 VPXORQ	0x12a0(%RSP,%RCX,8),%ZMM8,%ZMM8

    (92) 0x4e1d VPXORQ	0x12e0(%RSP,%RCX,8),%ZMM9,%ZMM9

    (92) 0x4e28 VPTESTMQ	%ZMM16,%ZMM3,%K1

    (92) 0x4e2e VPTESTMQ	%ZMM16,%ZMM4,%K2

    (92) 0x4e34 VPTESTMQ	%ZMM16,%ZMM5,%K3

    (92) 0x4e3a VPTESTMQ	%ZMM16,%ZMM2,%K4

    (92) 0x4e40 VPXORQ	%ZMM17,%ZMM6,%ZMM6{%K1}

    (92) 0x4e46 VPXORQ	%ZMM17,%ZMM7,%ZMM7{%K2}

    (92) 0x4e4c VPXORQ	%ZMM17,%ZMM8,%ZMM8{%K3}

    (92) 0x4e52 VPXORQ	%ZMM17,%ZMM9,%ZMM9{%K4}

    (92) 0x4e58 VMOVDQU64	%ZMM6,0x5b8(%RSP,%RCX,8)

    (92) 0x4e63 VMOVDQU64	%ZMM7,0x5f8(%RSP,%RCX,8)

    (92) 0x4e6e VMOVDQU64	%ZMM8,0x638(%RSP,%RCX,8)

    (92) 0x4e79 VMOVDQU64	%ZMM9,0x678(%RSP,%RCX,8)

    (92) 0x4e84 ADD	$0x20,%RCX

    (92) 0x4e88 CMP	$0xe0,%RCX

    (92) 0x4e8f JNE	4d70

  (91) 0x4e95 VEXTRACTI32X4	$0x3,%ZMM2,%XMM2

  (91) 0x4e9c VPEXTRQ	$0x1,%XMM2,%RSI

  (91) 0x4ea2 AND	$-0x80000000,%RSI

  (91) 0x4ea9 MOV	0xcc0(%RSP),%RDX

  (91) 0x4eb1 MOV	0xcc8(%RSP),%RCX

  (91) 0x4eb9 MOV	%EDX,%EDI

  (91) 0x4ebb AND	$0x7ffffffe,%EDI

  (91) 0x4ec1 OR	%RSI,%RDI

  (91) 0x4ec4 SHR	$0x1,%RDI

  (91) 0x4ec7 XOR	0x1920(%RSP),%RDI

  (91) 0x4ecf MOV	%EDX,%ESI

  (91) 0x4ed1 AND	$0x1,%ESI

  (91) 0x4ed4 NEG	%ESI

  (91) 0x4ed6 AND	%R12D,%ESI

  (91) 0x4ed9 XOR	%RDI,%RSI

  (91) 0x4edc MOV	%RSI,0xcb8(%RSP)

  (91) 0x4ee4 AND	$-0x80000000,%RDX

  (91) 0x4eeb MOV	%ECX,%ESI

  (91) 0x4eed AND	$0x7ffffffe,%ESI

  (91) 0x4ef3 OR	%RDX,%RSI

  (91) 0x4ef6 SHR	$0x1,%RSI

  (91) 0x4ef9 XOR	0x1928(%RSP),%RSI

  (91) 0x4f01 MOV	%ECX,%EDX

  (91) 0x4f03 AND	$0x1,%EDX

  (91) 0x4f06 NEG	%EDX

  (91) 0x4f08 AND	%R12D,%EDX

  (91) 0x4f0b XOR	%RSI,%RDX

  (91) 0x4f0e MOV	%RDX,0xcc0(%RSP)

  (91) 0x4f16 AND	$-0x80000000,%RCX

  (91) 0x4f1d MOV	0xcd0(%RSP),%RDX

  (91) 0x4f25 MOV	%EDX,%ESI

  (91) 0x4f27 VPBROADCASTQ	%RDX,%XMM2

  (91) 0x4f2d AND	$0x7ffffffe,%EDX

  (91) 0x4f33 OR	%RCX,%RDX

  (91) 0x4f36 SHR	$0x1,%RDX

  (91) 0x4f39 XOR	0x1930(%RSP),%RDX

  (91) 0x4f41 AND	$0x1,%ESI

  (91) 0x4f44 NEG	%ESI

  (91) 0x4f46 AND	%R12D,%ESI

  (91) 0x4f49 XOR	%RDX,%RSI

  (91) 0x4f4c MOV	%RSI,0xcc8(%RSP)

  (91) 0x4f54 MOV	$0xe8,%ECX

  (91) 0x4f59 VPBROADCASTQ	0x40de(%RIP),%XMM7

  (91) 0x4f62 VPBROADCASTQ	0x40dd(%RIP),%XMM8

  (91) 0x4f6b VPBROADCASTQ	0x40dc(%RIP),%XMM9

  (91) 0x4f74 VPBROADCASTQ	0x40db(%RIP),%XMM10

  (91) 0x4f7d NOPL	(%RAX)

    (93) 0x4f80 VMOVDQU	0x598(%RSP,%RCX,8),%XMM3

    (93) 0x4f89 VMOVDQU	0x5a8(%RSP,%RCX,8),%XMM4

    (93) 0x4f92 VPALIGNR	$0x8,%XMM2,%XMM3,%XMM2

    (93) 0x4f98 VMOVDQU	0x5b8(%RSP,%RCX,8),%XMM5

    (93) 0x4fa1 VPAND	%XMM3,%XMM8,%XMM6

    (93) 0x4fa5 VPTERNLOGQ	$-0x8,%XMM7,%XMM2,%XMM6

    (93) 0x4fac VPSRLQ	$0x1,%XMM6,%XMM2

    (93) 0x4fb1 VPXOR	-0x188(%RSP,%RCX,8),%XMM2,%XMM2

    (93) 0x4fba VPTESTMQ	%XMM9,%XMM3,%K1

    (93) 0x4fc0 VPXORQ	%XMM10,%XMM2,%XMM2{%K1}

    (93) 0x4fc6 VMOVDQU	%XMM2,0x590(%RSP,%RCX,8)

    (93) 0x4fcf VPALIGNR	$0x8,%XMM3,%XMM4,%XMM2

    (93) 0x4fd5 VPAND	%XMM4,%XMM8,%XMM3

    (93) 0x4fd9 VPTERNLOGQ	$-0x8,%XMM7,%XMM2,%XMM3

    (93) 0x4fe0 VPSRLQ	$0x1,%XMM3,%XMM2

    (93) 0x4fe5 VPXOR	-0x178(%RSP,%RCX,8),%XMM2,%XMM2

    (93) 0x4fee VPTESTMQ	%XMM9,%XMM4,%K1

    (93) 0x4ff4 VPXORQ	%XMM10,%XMM2,%XMM2{%K1}

    (93) 0x4ffa VMOVDQU	%XMM2,0x5a0(%RSP,%RCX,8)

    (93) 0x5003 VPALIGNR	$0x8,%XMM4,%XMM5,%XMM2

    (93) 0x5009 VPAND	%XMM5,%XMM8,%XMM3

    (93) 0x500d VPTERNLOGQ	$-0x8,%XMM7,%XMM2,%XMM3

    (93) 0x5014 VPSRLQ	$0x1,%XMM3,%XMM2

    (93) 0x5019 VPXOR	-0x168(%RSP,%RCX,8),%XMM2,%XMM2

    (93) 0x5022 VPTESTMQ	%XMM9,%XMM5,%K1

    (93) 0x5028 VPXORQ	%XMM10,%XMM2,%XMM2{%K1}

    (93) 0x502e VMOVDQU	%XMM2,0x5b0(%RSP,%RCX,8)

    (93) 0x5037 ADD	$0x6,%RCX

    (93) 0x503b VMOVDQA	%XMM5,%XMM2

    (93) 0x503f CMP	$0x274,%RCX

    (93) 0x5046 JNE	4f80

  (91) 0x504c MOV	0x1930(%RSP),%RCX

  (91) 0x5054 MOV	$-0x80000000,%RDX

  (91) 0x505b AND	%RDX,%RCX

  (91) 0x505e MOV	0x5b8(%RSP),%R13

  (91) 0x5066 MOV	%R13D,%EDX

  (91) 0x5069 AND	$0x7ffffffe,%EDX

  (91) 0x506f OR	%RCX,%RDX

  (91) 0x5072 SHR	$0x1,%RDX

  (91) 0x5075 XOR	0x1218(%RSP),%RDX

  (91) 0x507d MOV	%R13D,%ECX

  (91) 0x5080 AND	$0x1,%ECX

  (91) 0x5083 NEG	%ECX

  (91) 0x5085 AND	%R12D,%ECX

  (91) 0x5088 XOR	%RDX,%RCX

  (91) 0x508b MOV	%RCX,0x1930(%RSP)

  (91) 0x5093 XOR	%EBX,%EBX

  (91) 0x5095 JMP	4cd0

0x50a0 VDIVSS	%XMM1,%XMM0,%XMM0

0x50a4 VMOVSS	0x3f68(%RIP),%XMM2

0x50ac VUCOMISS	%XMM2,%XMM0

0x50b0 JAE	551d

0x50b6 MOV	0x1b0(%RSP),%RAX

0x50be VMOVSS	%XMM0,(%RAX,%R9,4)

0x50c4 VXORPS	%XMM0,%XMM0,%XMM0

0x50c8 MOV	%R8,%RAX

0x50cb VMOVAPS	%XMM2,%XMM1

0x50cf JMP	5144

  (88) 0x50e0 MOV	%RBX,%RCX

  (88) 0x50e3 INC	%RBX

  (88) 0x50e6 MOV	%RBX,0x1938(%RSP)

  (88) 0x50ee MOV	0x5b8(%RSP,%RCX,8),%RCX

  (88) 0x50f6 MOV	%RCX,%RDX

  (88) 0x50f9 SHR	$0xb,%RDX

  (88) 0x50fd MOV	%EDX,%EDX

  (88) 0x50ff XOR	%RCX,%RDX

  (88) 0x5102 MOV	%EDX,%ECX

  (88) 0x5104 SAL	$0x7,%ECX

  (88) 0x5107 AND	$-0x62d3a980,%ECX

  (88) 0x510d XOR	%RDX,%RCX

  (88) 0x5110 MOV	%ECX,%EDX

  (88) 0x5112 SAL	$0xf,%EDX

  (88) 0x5115 AND	$-0x103a0000,%EDX

  (88) 0x511b XOR	%RCX,%RDX

  (88) 0x511e MOV	%RDX,%RCX

  (88) 0x5121 SHR	$0x12,%RCX

  (88) 0x5125 XOR	%RDX,%RCX

  (88) 0x5128 VCVTUSI2SS	%RCX,%XMM15,%XMM2

  (88) 0x512e VFMADD231SS	%XMM2,%XMM1,%XMM0

  (88) 0x5133 VMULSS	0x3ecd(%RIP),%XMM1,%XMM1

  (88) 0x513b DEC	%RAX

  (88) 0x513e JE	54b0

  (88) 0x5144 CMP	$0x270,%RBX

  (88) 0x514b JB	50e0

  (88) 0x514d VPBROADCASTQ	%R13,%ZMM2

  (88) 0x5153 XOR	%ECX,%ECX

  (88) 0x5155 VPBROADCASTQ	0x3ee1(%RIP),%ZMM14

  (88) 0x515f VPBROADCASTQ	0x3edf(%RIP),%ZMM15

  (88) 0x5169 VPBROADCASTQ	0x3edd(%RIP),%ZMM16

  (88) 0x5173 VPBROADCASTQ	0x3edb(%RIP),%ZMM17

  (88) 0x517d NOPL	(%RAX)

    (89) 0x5180 VMOVDQU64	0x5c0(%RSP,%RCX,8),%ZMM3

    (89) 0x5188 VMOVDQU64	0x600(%RSP,%RCX,8),%ZMM4

    (89) 0x5190 VMOVDQU64	0x640(%RSP,%RCX,8),%ZMM5

    (89) 0x5198 VALIGNQ	$0x7,%ZMM2,%ZMM3,%ZMM6

    (89) 0x519f VMOVDQU64	0x680(%RSP,%RCX,8),%ZMM2

    (89) 0x51a7 VALIGNQ	$0x7,%ZMM3,%ZMM4,%ZMM7

    (89) 0x51ae VALIGNQ	$0x7,%ZMM4,%ZMM5,%ZMM8

    (89) 0x51b5 VALIGNQ	$0x7,%ZMM5,%ZMM2,%ZMM9

    (89) 0x51bc VPANDQ	%ZMM15,%ZMM3,%ZMM10

    (89) 0x51c2 VPANDQ	%ZMM15,%ZMM4,%ZMM11

    (89) 0x51c8 VPANDQ	%ZMM15,%ZMM5,%ZMM12

    (89) 0x51ce VPANDQ	%ZMM15,%ZMM2,%ZMM13

    (89) 0x51d4 VPTERNLOGQ	$-0x8,%ZMM14,%ZMM6,%ZMM10

    (89) 0x51db VPTERNLOGQ	$-0x8,%ZMM14,%ZMM7,%ZMM11

    (89) 0x51e2 VPTERNLOGQ	$-0x8,%ZMM14,%ZMM8,%ZMM12

    (89) 0x51e9 VPTERNLOGQ	$-0x8,%ZMM14,%ZMM9,%ZMM13

    (89) 0x51f0 VPSRLQ	$0x1,%ZMM10,%ZMM6

    (89) 0x51f7 VPSRLQ	$0x1,%ZMM11,%ZMM7

    (89) 0x51fe VPSRLQ	$0x1,%ZMM12,%ZMM8

    (89) 0x5205 VPSRLQ	$0x1,%ZMM13,%ZMM9

    (89) 0x520c VPXORQ	0x1220(%RSP,%RCX,8),%ZMM6,%ZMM6

    (89) 0x5217 VPXORQ	0x1260(%RSP,%RCX,8),%ZMM7,%ZMM7

    (89) 0x5222 VPXORQ	0x12a0(%RSP,%RCX,8),%ZMM8,%ZMM8

    (89) 0x522d VPXORQ	0x12e0(%RSP,%RCX,8),%ZMM9,%ZMM9

    (89) 0x5238 VPTESTMQ	%ZMM16,%ZMM3,%K1

    (89) 0x523e VPTESTMQ	%ZMM16,%ZMM4,%K2

    (89) 0x5244 VPTESTMQ	%ZMM16,%ZMM5,%K3

    (89) 0x524a VPTESTMQ	%ZMM16,%ZMM2,%K4

    (89) 0x5250 VPXORQ	%ZMM17,%ZMM6,%ZMM6{%K1}

    (89) 0x5256 VPXORQ	%ZMM17,%ZMM7,%ZMM7{%K2}

    (89) 0x525c VPXORQ	%ZMM17,%ZMM8,%ZMM8{%K3}

    (89) 0x5262 VPXORQ	%ZMM17,%ZMM9,%ZMM9{%K4}

    (89) 0x5268 VMOVDQU64	%ZMM6,0x5b8(%RSP,%RCX,8)

    (89) 0x5273 VMOVDQU64	%ZMM7,0x5f8(%RSP,%RCX,8)

    (89) 0x527e VMOVDQU64	%ZMM8,0x638(%RSP,%RCX,8)

    (89) 0x5289 VMOVDQU64	%ZMM9,0x678(%RSP,%RCX,8)

    (89) 0x5294 ADD	$0x20,%RCX

    (89) 0x5298 CMP	$0xe0,%RCX

    (89) 0x529f JNE	5180

  (88) 0x52a5 VEXTRACTI32X4	$0x3,%ZMM2,%XMM2

  (88) 0x52ac VPEXTRQ	$0x1,%XMM2,%RSI

  (88) 0x52b2 AND	$-0x80000000,%RSI

  (88) 0x52b9 MOV	0xcc0(%RSP),%RDX

  (88) 0x52c1 MOV	0xcc8(%RSP),%RCX

  (88) 0x52c9 MOV	%EDX,%EDI

  (88) 0x52cb AND	$0x7ffffffe,%EDI

  (88) 0x52d1 OR	%RSI,%RDI

  (88) 0x52d4 SHR	$0x1,%RDI

  (88) 0x52d7 XOR	0x1920(%RSP),%RDI

  (88) 0x52df MOV	%EDX,%ESI

  (88) 0x52e1 AND	$0x1,%ESI

  (88) 0x52e4 NEG	%ESI

  (88) 0x52e6 AND	%R12D,%ESI

  (88) 0x52e9 XOR	%RDI,%RSI

  (88) 0x52ec MOV	%RSI,0xcb8(%RSP)

  (88) 0x52f4 AND	$-0x80000000,%RDX

  (88) 0x52fb MOV	%ECX,%ESI

  (88) 0x52fd AND	$0x7ffffffe,%ESI

  (88) 0x5303 OR	%RDX,%RSI

  (88) 0x5306 SHR	$0x1,%RSI

  (88) 0x5309 XOR	0x1928(%RSP),%RSI

  (88) 0x5311 MOV	%ECX,%EDX

  (88) 0x5313 AND	$0x1,%EDX

  (88) 0x5316 NEG	%EDX

  (88) 0x5318 AND	%R12D,%EDX

  (88) 0x531b XOR	%RSI,%RDX

  (88) 0x531e MOV	%RDX,0xcc0(%RSP)

  (88) 0x5326 AND	$-0x80000000,%RCX

  (88) 0x532d MOV	0xcd0(%RSP),%RDX

  (88) 0x5335 MOV	%EDX,%ESI

  (88) 0x5337 VPBROADCASTQ	%RDX,%XMM2

  (88) 0x533d AND	$0x7ffffffe,%EDX

  (88) 0x5343 OR	%RCX,%RDX

  (88) 0x5346 SHR	$0x1,%RDX

  (88) 0x5349 XOR	0x1930(%RSP),%RDX

  (88) 0x5351 AND	$0x1,%ESI

  (88) 0x5354 NEG	%ESI

  (88) 0x5356 AND	%R12D,%ESI

  (88) 0x5359 XOR	%RDX,%RSI

  (88) 0x535c MOV	%RSI,0xcc8(%RSP)

  (88) 0x5364 MOV	$0xe8,%ECX

  (88) 0x5369 VPBROADCASTQ	0x3cce(%RIP),%XMM7

  (88) 0x5372 VPBROADCASTQ	0x3ccd(%RIP),%XMM8

  (88) 0x537b VPBROADCASTQ	0x3ccc(%RIP),%XMM9

  (88) 0x5384 VPBROADCASTQ	0x3ccb(%RIP),%XMM10

  (88) 0x538d NOPL	(%RAX)

    (90) 0x5390 VMOVDQU	0x598(%RSP,%RCX,8),%XMM3

    (90) 0x5399 VMOVDQU	0x5a8(%RSP,%RCX,8),%XMM4

    (90) 0x53a2 VPALIGNR	$0x8,%XMM2,%XMM3,%XMM2

    (90) 0x53a8 VMOVDQU	0x5b8(%RSP,%RCX,8),%XMM5

    (90) 0x53b1 VPAND	%XMM3,%XMM8,%XMM6

    (90) 0x53b5 VPTERNLOGQ	$-0x8,%XMM7,%XMM2,%XMM6

    (90) 0x53bc VPSRLQ	$0x1,%XMM6,%XMM2

    (90) 0x53c1 VPXOR	-0x188(%RSP,%RCX,8),%XMM2,%XMM2

    (90) 0x53ca VPTESTMQ	%XMM9,%XMM3,%K1

    (90) 0x53d0 VPXORQ	%XMM10,%XMM2,%XMM2{%K1}

    (90) 0x53d6 VMOVDQU	%XMM2,0x590(%RSP,%RCX,8)

    (90) 0x53df VPALIGNR	$0x8,%XMM3,%XMM4,%XMM2

    (90) 0x53e5 VPAND	%XMM4,%XMM8,%XMM3

    (90) 0x53e9 VPTERNLOGQ	$-0x8,%XMM7,%XMM2,%XMM3

    (90) 0x53f0 VPSRLQ	$0x1,%XMM3,%XMM2

    (90) 0x53f5 VPXOR	-0x178(%RSP,%RCX,8),%XMM2,%XMM2

    (90) 0x53fe VPTESTMQ	%XMM9,%XMM4,%K1

    (90) 0x5404 VPXORQ	%XMM10,%XMM2,%XMM2{%K1}

    (90) 0x540a VMOVDQU	%XMM2,0x5a0(%RSP,%RCX,8)

    (90) 0x5413 VPALIGNR	$0x8,%XMM4,%XMM5,%XMM2

    (90) 0x5419 VPAND	%XMM5,%XMM8,%XMM3

    (90) 0x541d VPTERNLOGQ	$-0x8,%XMM7,%XMM2,%XMM3

    (90) 0x5424 VPSRLQ	$0x1,%XMM3,%XMM2

    (90) 0x5429 VPXOR	-0x168(%RSP,%RCX,8),%XMM2,%XMM2

    (90) 0x5432 VPTESTMQ	%XMM9,%XMM5,%K1

    (90) 0x5438 VPXORQ	%XMM10,%XMM2,%XMM2{%K1}

    (90) 0x543e VMOVDQU	%XMM2,0x5b0(%RSP,%RCX,8)

    (90) 0x5447 ADD	$0x6,%RCX

    (90) 0x544b VMOVDQA	%XMM5,%XMM2

    (90) 0x544f CMP	$0x274,%RCX

    (90) 0x5456 JNE	5390

  (88) 0x545c MOV	0x1930(%RSP),%RCX

  (88) 0x5464 MOV	$-0x80000000,%RDX

  (88) 0x546b AND	%RDX,%RCX

  (88) 0x546e MOV	0x5b8(%RSP),%R13

  (88) 0x5476 MOV	%R13D,%EDX

  (88) 0x5479 AND	$0x7ffffffe,%EDX

  (88) 0x547f OR	%RCX,%RDX

  (88) 0x5482 SHR	$0x1,%RDX

  (88) 0x5485 XOR	0x1218(%RSP),%RDX

  (88) 0x548d MOV	%R13D,%ECX

  (88) 0x5490 AND	$0x1,%ECX

  (88) 0x5493 NEG	%ECX

  (88) 0x5495 AND	%R12D,%ECX

  (88) 0x5498 XOR	%RDX,%RCX

  (88) 0x549b MOV	%RCX,0x1930(%RSP)

  (88) 0x54a3 XOR	%EBX,%EBX

  (88) 0x54a5 JMP	50e0

0x54b0 VDIVSS	%XMM1,%XMM0,%XMM0

0x54b4 VUCOMISS	0x3b58(%RIP),%XMM0

0x54bc JAE	5554

0x54c2 MOV	0x1a8(%RSP),%RAX

0x54ca VMOVSS	%XMM0,(%RAX,%R9,4)

0x54d0 INC	%R9

0x54d3 CMP	0x470(%RSP),%R9

0x54db JNE	48b0

0x54e6 VXORPS	%XMM1,%XMM1,%XMM1

0x54ea VMOVAPS	%XMM2,%XMM0

0x54ee MOV	%R8,0x30(%RSP)

0x54f3 MOV	%R9,0x2c0(%RSP)

0x54fb VZEROUPPER

0x54fe CALL	10a0 <nextafterf@plt>

0x5503 VMOVSS	0x3b09(%RIP),%XMM2

0x550b MOV	0x2c0(%RSP),%R9

0x5513 MOV	0x30(%RSP),%R8

0x5518 JMP	4cb6

0x551d VXORPS	%XMM1,%XMM1,%XMM1

0x5521 VMOVAPS	%XMM2,%XMM0

0x5525 MOV	%R8,0x30(%RSP)

0x552a MOV	%R9,0x2c0(%RSP)

0x5532 VZEROUPPER

0x5535 CALL	10a0 <nextafterf@plt>

0x553a VMOVSS	0x3ad2(%RIP),%XMM2

0x5542 MOV	0x2c0(%RSP),%R9

0x554a MOV	0x30(%RSP),%R8

0x554f JMP	50b6

0x5554 VXORPS	%XMM1,%XMM1,%XMM1

0x5558 VMOVSS	0x3ab4(%RIP),%XMM0

0x5560 MOV	%R8,0x30(%RSP)

0x5565 MOV	%R9,0x2c0(%RSP)

0x556d VZEROUPPER

0x5570 CALL	10a0 <nextafterf@plt>

0x5575 MOV	0x2c0(%RSP),%R9

0x557d MOV	0x30(%RSP),%R8

0x5582 JMP	54c2

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath: 1661 - 1661

--------------------------------------------------------------------------------

1661:   { return __builtin_nextafterf(__x, __y); }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc: 401 - 3370

--------------------------------------------------------------------------------

401:       for (size_t __k = 0; __k < (__n - __m); ++__k)

402:         {

403: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

404: 			   | (_M_x[__k + 1] & __lower_mask));

405: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

406: 		       ^ ((__y & 0x01) ? __a : 0));

407:         }

408:

409:       for (size_t __k = (__n - __m); __k < (__n - 1); ++__k)

410: 	{

411: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

412: 			   | (_M_x[__k + 1] & __lower_mask));

413: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

414: 		       ^ ((__y & 0x01) ? __a : 0));

415: 	}

416:

417:       _UIntType __y = ((_M_x[__n - 1] & __upper_mask)

418: 		       | (_M_x[0] & __lower_mask));

419:       _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1)

420: 		       ^ ((__y & 0x01) ? __a : 0));

[...]

455:       if (_M_p >= state_size)

456: 	_M_gen_rand();

457:

458:       // Calculate o(x(i)).

459:       result_type __z = _M_x[_M_p++];

460:       __z ^= (__z >> __u) & __d;

461:       __z ^= (__z << __s) & __b;

462:       __z ^= (__z << __t) & __c;

463:       __z ^= (__z >> __l);

[...]

3364:       for (size_t __k = __m; __k != 0; --__k)

3365: 	{

3366: 	  __sum += _RealType(__urng() - __urng.min()) * __tmp;

3367: 	  __tmp *= __r;

3368: 	}

3369:       __ret = __sum / __tmp;

3370:       if (__builtin_expect(__ret >= _RealType(1), 0))

/home/eoseret/llm-attention/attention_v2.cpp: 164 - 167

--------------------------------------------------------------------------------

164:       for (size_t i = 0; i < elemsW; ++i) {

165:          h_WQ[i] = dist(rng);

166:          h_WK[i] = dist(rng);

167:          h_WV[i] = dist(rng);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.24
CQA speedup if FP arith vectorized	2.29
CQA speedup if fully vectorized	4.96
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	micro-operation queue,
Function	main
Source	cmath:1661-1661,random.tcc:3369-3370,attention_v2.cpp:164-167
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.17
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	4.89
CQA cycles if fully vectorized	2.25
Front-end cycles	11.17
P0 cycles	6.00
P1 cycles	0.40
P2 cycles	5.33
P3 cycles	5.33
P4 cycles	6.00
P5 cycles	0.40
P6 cycles	4.00
P7 cycles	6.00
P8 cycles	6.00
P9 cycles	6.00
P10 cycles	0.20
P11 cycles	5.33
DIV/SQRT cycles	9.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	67.00
Nb loads	16.00
Nb stores	9.00
Nb stack references	5.00
FLOP/cycle	0.27
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.33
Bytes prefetched	0.00
Bytes loaded	100.00
Bytes stored	60.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	35.14
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	81.25
Vector-efficiency ratio all	14.36
Vector-efficiency ratio load	8.13
Vector-efficiency ratio store	10.42
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	21.48

Metric	Value
CQA speedup if no scalar integer	1.24
CQA speedup if FP arith vectorized	2.29
CQA speedup if fully vectorized	4.96
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	micro-operation queue,
Function	main
Source	cmath:1661-1661,random.tcc:3369-3370,attention_v2.cpp:164-167
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.17
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	4.89
CQA cycles if fully vectorized	2.25
Front-end cycles	11.17
P0 cycles	6.00
P1 cycles	0.40
P2 cycles	5.33
P3 cycles	5.33
P4 cycles	6.00
P5 cycles	0.40
P6 cycles	4.00
P7 cycles	6.00
P8 cycles	6.00
P9 cycles	6.00
P10 cycles	0.20
P11 cycles	5.33
DIV/SQRT cycles	9.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	60.00
Nb uops	67.00
Nb loads	16.00
Nb stores	9.00
Nb stack references	5.00
FLOP/cycle	0.27
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.33
Bytes prefetched	0.00
Bytes loaded	100.00
Bytes stored	60.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	35.14
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	81.25
Vector-efficiency ratio all	14.36
Vector-efficiency ratio load	8.13
Vector-efficiency ratio store	10.42
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	21.48

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:164-167
Module	attention-clang-gnr512

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:401-420,455-463,3364-3370
/home/eoseret/llm-attention/attention_v2.cpp:164-167

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 64 paths individually, rerun with max-paths=64
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 64 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.17 to 9.00 cycles (1.24x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 11.17 to 2.25 cycles (4.96x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

nextafterf@plt: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISS: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370
VZEROUPPER: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

3: divide

The binary loop is loading 100 bytes (25 single precision FP elements). The binary loop is storing 60 bytes (15 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	60
nb uops	67
loop length	317
used x86 registers	5
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.17 cycles
front end	11.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.00	0.40	5.33	5.33	6.00	0.40	4.00	6.00	6.00	6.00	0.20	5.33
cycles	6.00	0.40	5.33	5.33	6.00	0.40	4.00	6.00	6.00	6.00	0.20	5.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

9.00

Cycles summary

Front-end	11.17
Dispatch	6.00
DIV/SQRT	9.00
Overall L1	11.17

Vectorization ratios

INT

all	25%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	40%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	76%

INT+FP

all	35%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	81%

Vector efficiency ratios

INT

all	15%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	13%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	20%

INT+FP

all	14%
load	8%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.17 cycles. At this rate:

4% of peak load performance is reached (8.96 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.37 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 48b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS 0x4755(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
JMP 4934 <main+0x10b4>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
VDIVSS %XMM1,%XMM0,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	11-12	3	scal (6.3%)
VMOVSS 0x4368(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VUCOMISS %XMM2,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
JAE 54e6 <main+0x1c66>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSS %XMM0,(%R15,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPS %XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
JMP 4d34 <main+0x14b4>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
VDIVSS %XMM1,%XMM0,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	11-12	3	scal (6.3%)
VMOVSS 0x3f68(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VUCOMISS %XMM2,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
JAE 551d <main+0x1c9d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x1b0(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPS %XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
JMP 5144 <main+0x18c4>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
VDIVSS %XMM1,%XMM0,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	11-12	3	scal (6.3%)
VUCOMISS 0x3b58(%RIP),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (6.3%)
JAE 5554 <main+0x1cd4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x1a8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
INC %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP 0x470(%RSP),%R9	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JNE 48b0 <main+0x1030>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPS %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOV %R8,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,0x2c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 10a0 <nextafterf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSS 0x3b09(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x2c0(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 4cb6 <main+0x1436>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPS %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOV %R8,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,0x2c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 10a0 <nextafterf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSS 0x3ad2(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x2c0(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 50b6 <main+0x1836>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSS 0x3ab4(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %R8,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,0x2c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 10a0 <nextafterf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x2c0(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 54c2 <main+0x1c42>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	main
Source file and lines	attention_v2.cpp:164-167
Module	attention-clang-gnr512

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:401-420,455-463,3364-3370
/home/eoseret/llm-attention/attention_v2.cpp:164-167

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 64 paths individually, rerun with max-paths=64
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.17 to 9.00 cycles (1.24x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

nextafterf@plt: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISS: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370
VZEROUPPER: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

3: divide

The binary loop is loading 100 bytes (25 single precision FP elements). The binary loop is storing 60 bytes (15 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	60
nb uops	67
loop length	317
used x86 registers	5
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	11.17 cycles
front end	11.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.00	0.40	5.33	5.33	6.00	0.40	4.00	6.00	6.00	6.00	0.20	5.33
cycles	6.00	0.40	5.33	5.33	6.00	0.40	4.00	6.00	6.00	6.00	0.20	5.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

9.00

Cycles summary

Front-end	11.17
Dispatch	6.00
DIV/SQRT	9.00
Overall L1	11.17

Vectorization ratios

INT

all	25%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	40%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	76%

INT+FP

all	35%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	81%

Vector efficiency ratios

INT

all	15%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	13%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	20%

INT+FP

all	14%
load	8%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	21%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.17 cycles. At this rate:

4% of peak load performance is reached (8.96 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.37 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 48b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS 0x4755(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
JMP 4934 <main+0x10b4>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
VDIVSS %XMM1,%XMM0,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	11-12	3	scal (6.3%)
VMOVSS 0x4368(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VUCOMISS %XMM2,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
JAE 54e6 <main+0x1c66>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSS %XMM0,(%R15,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPS %XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
JMP 4d34 <main+0x14b4>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
VDIVSS %XMM1,%XMM0,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	11-12	3	scal (6.3%)
VMOVSS 0x3f68(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VUCOMISS %XMM2,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
JAE 551d <main+0x1c9d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x1b0(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %R8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPS %XMM2,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
JMP 5144 <main+0x18c4>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
VDIVSS %XMM1,%XMM0,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	11-12	3	scal (6.3%)
VUCOMISS 0x3b58(%RIP),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (6.3%)
JAE 5554 <main+0x1cd4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x1a8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
INC %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP 0x470(%RSP),%R9	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JNE 48b0 <main+0x1030>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPS %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOV %R8,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,0x2c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 10a0 <nextafterf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSS 0x3b09(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x2c0(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 4cb6 <main+0x1436>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPS %XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
MOV %R8,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,0x2c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 10a0 <nextafterf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSS 0x3ad2(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x2c0(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 50b6 <main+0x1836>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSS 0x3ab4(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %R8,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,0x2c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 10a0 <nextafterf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x2c0(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 54c2 <main+0x1c42>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

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Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code