OV - attention-clang-gnr512 - Loop 64 - attention-clang-gnr512

	Loop Id: 64	Module: attention-clang-gnr512	Source: attention_v2.cpp:27-33	Coverage: 5.89%

0x5e55 VCVTSD2SS	%XMM0,%XMM0,%XMM0

0x5e59 VDIVSS	0x3a4(%RSP),%XMM0,%XMM0

0x5e62 MOV	0x2c0(%RSP),%RCX

0x5e6a MOV	0x30(%RSP),%RDI

0x5e6f LEA	(%RCX,%RDI,1),%R8D

0x5e73 MOV	0xb0(%RSP),%RCX

0x5e7b VMOVSS	%XMM0,(%RCX,%R8,4)

0x5e81 INC	%RDI

0x5e84 CMP	0x98(%RSP),%RDI

0x5e8c JE	5e04

0x5e92 VPXOR	%XMM0,%XMM0,%XMM0

0x5e96 CMPL	$0x4,0x38(%RSP)

0x5e9b MOV	%RDI,0x30(%RSP)

0x5ea0 JB	5ebf

0x5ea2 MOV	%EDI,%R8D

0x5ea5 ADD	0xa8(%RSP),%R8D

0x5ead SETB	%R8B

0x5eb1 OR	0x200(%RSP),%R8B

0x5eb9 JE	6031

0x5ebf XOR	%R9D,%R9D

0x5ec2 TESTB	$0x3,0x60(%RSP)

0x5ec7 JE	5f2b

0x5ec9 MOV	0x80(%RSP),%R13

0x5ed1 MOV	%R13,%R10

0x5ed4 IMUL	%R9,%R10

0x5ed8 ADD	0x30(%RSP),%R10

0x5edd MOV	0x1f0(%RSP),%R11

0x5ee5 MOV	%R9,%R8

0x5ee8 MOV	0x88(%RSP),%RSI

0x5ef0 MOV	0x70(%RSP),%RDI

0x5ef5 NOPW	%CS:(%RAX,%RAX,1)

  (66) 0x5f00 LEA	(%RAX,%R8,1),%EBX

  (66) 0x5f04 VMOVSS	(%RSI,%RBX,4),%XMM1

  (66) 0x5f09 VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (66) 0x5f0d MOV	%R10D,%EBX

  (66) 0x5f10 VMOVSS	(%RDI,%RBX,4),%XMM2

  (66) 0x5f15 VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (66) 0x5f19 VFMADD231SD	%XMM2,%XMM1,%XMM0

  (66) 0x5f1e INC	%R8

  (66) 0x5f21 ADD	%R13,%R10

  (66) 0x5f24 DEC	%R11

  (66) 0x5f27 JNE	5f00

0x5f29 JMP	5f3b

0x5f2b MOV	%R9,%R8

0x5f2e MOV	0x88(%RSP),%RSI

0x5f36 MOV	0x70(%RSP),%RDI

0x5f3b MOV	0x38(%RSP),%RCX

0x5f40 SUB	%RCX,%R9

0x5f43 CMP	$-0x4,%R9

0x5f47 MOV	0x458(%RSP),%RDX

0x5f4f JA	5e55

0x5f55 LEA	0x3(%R8),%R9

0x5f59 MOV	0x80(%RSP),%R13

0x5f61 IMUL	%R13,%R9

0x5f65 MOV	0x30(%RSP),%RBX

0x5f6a ADD	%RBX,%R9

0x5f6d LEA	0x2(%R8),%R10

0x5f71 IMUL	%R13,%R10

0x5f75 ADD	%RBX,%R10

0x5f78 MOV	%R13,%R11

0x5f7b IMUL	%R8,%R11

0x5f7f ADD	%RBX,%R11

0x5f82 LEA	0x1(%R8),%RBX

0x5f86 IMUL	%R13,%RBX

0x5f8a ADD	0x30(%RSP),%RBX

0x5f8f NOP

  (65) 0x5f90 LEA	(%RAX,%R8,1),%R13D

  (65) 0x5f94 VMOVSS	(%RSI,%R13,4),%XMM1

  (65) 0x5f9a VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (65) 0x5f9e MOV	%R11D,%R13D

  (65) 0x5fa1 VMOVSS	(%RDI,%R13,4),%XMM2

  (65) 0x5fa7 VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (65) 0x5fab LEA	0x1(%RAX,%R8,1),%R13D

  (65) 0x5fb0 VMOVSS	(%RSI,%R13,4),%XMM3

  (65) 0x5fb6 VCVTSS2SD	%XMM3,%XMM3,%XMM3

  (65) 0x5fba VFMADD213SD	%XMM0,%XMM1,%XMM2

  (65) 0x5fbf MOV	%EBX,%R13D

  (65) 0x5fc2 VMOVSS	(%RDI,%R13,4),%XMM0

  (65) 0x5fc8 VCVTSS2SD	%XMM0,%XMM0,%XMM0

  (65) 0x5fcc VFMADD213SD	%XMM2,%XMM3,%XMM0

  (65) 0x5fd1 LEA	0x2(%RAX,%R8,1),%R13D

  (65) 0x5fd6 VMOVSS	(%RSI,%R13,4),%XMM1

  (65) 0x5fdc VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (65) 0x5fe0 MOV	%R10D,%R13D

  (65) 0x5fe3 VMOVSS	(%RDI,%R13,4),%XMM2

  (65) 0x5fe9 VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (65) 0x5fed LEA	0x3(%RAX,%R8,1),%R13D

  (65) 0x5ff2 VMOVSS	(%RSI,%R13,4),%XMM3

  (65) 0x5ff8 VCVTSS2SD	%XMM3,%XMM3,%XMM3

  (65) 0x5ffc VFMADD213SD	%XMM0,%XMM1,%XMM2

  (65) 0x6001 MOV	%R9D,%R13D

  (65) 0x6004 VMOVSS	(%RDI,%R13,4),%XMM0

  (65) 0x600a VCVTSS2SD	%XMM0,%XMM0,%XMM0

  (65) 0x600e VFMADD213SD	%XMM2,%XMM3,%XMM0

  (65) 0x6013 ADD	$0x4,%R8

  (65) 0x6017 ADD	%RDX,%R9

  (65) 0x601a ADD	%RDX,%R10

  (65) 0x601d ADD	%RDX,%R11

  (65) 0x6020 ADD	%RDX,%RBX

  (65) 0x6023 CMP	%R8,%RCX

  (65) 0x6026 JNE	5f90

0x602c JMP	5e55

0x6031 CMPL	$0x20,0x38(%RSP)

0x6036 JAE	604d

0x6038 XOR	%R8D,%R8D

0x603b MOV	0x88(%RSP),%RCX

0x6043 MOV	0x70(%RSP),%RDX

0x6048 JMP	6136

0x604d VPXOR	%XMM0,%XMM0,%XMM0

0x6051 XOR	%R8D,%R8D

0x6054 VPXOR	%XMM1,%XMM1,%XMM1

0x6058 VXORPS	%XMM2,%XMM2,%XMM2

0x605c VXORPS	%XMM3,%XMM3,%XMM3

0x6060 MOV	0x88(%RSP),%RCX

0x6068 MOV	0x448(%RSP),%RSI

0x6070 MOV	0x70(%RSP),%RDX

  (67) 0x6075 LEA	(%RAX,%R8,1),%R9D

  (67) 0x6079 VCVTPS2PD	(%RCX,%R9,4),%ZMM4

  (67) 0x6080 VCVTPS2PD	0x20(%RCX,%R9,4),%ZMM5

  (67) 0x6088 VCVTPS2PD	0x40(%RCX,%R9,4),%ZMM6

  (67) 0x6090 VCVTPS2PD	0x60(%RCX,%R9,4),%ZMM7

  (67) 0x6098 LEA	(%RDI,%R8,1),%R9D

  (67) 0x609c VCVTPS2PD	(%RDX,%R9,4),%ZMM8

  (67) 0x60a3 VCVTPS2PD	0x20(%RDX,%R9,4),%ZMM9

  (67) 0x60ab VFMADD231PD	%ZMM8,%ZMM4,%ZMM0

  (67) 0x60b1 VFMADD231PD	%ZMM9,%ZMM5,%ZMM1

  (67) 0x60b7 VCVTPS2PD	0x40(%RDX,%R9,4),%ZMM4

  (67) 0x60bf VFMADD231PD	%ZMM4,%ZMM6,%ZMM2

  (67) 0x60c5 VCVTPS2PD	0x60(%RDX,%R9,4),%ZMM4

  (67) 0x60cd VFMADD231PD	%ZMM4,%ZMM7,%ZMM3

  (67) 0x60d3 ADD	$0x20,%R8

  (67) 0x60d7 CMP	%R8,%RSI

  (67) 0x60da JNE	6075

0x60dc VADDPD	%ZMM0,%ZMM1,%ZMM0

0x60e2 VADDPD	%ZMM2,%ZMM3,%ZMM1

0x60e8 VADDPD	%ZMM0,%ZMM1,%ZMM0

0x60ee VEXTRACTF64X4	$0x1,%ZMM0,%YMM1

0x60f5 VADDPD	%ZMM1,%ZMM0,%ZMM0

0x60fb VEXTRACTF128	$0x1,%YMM0,%XMM1

0x6101 VADDPD	%XMM1,%XMM0,%XMM0

0x6105 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x610a VADDSD	%XMM1,%XMM0,%XMM0

0x610e CMP	%ESI,0x38(%RSP)

0x6112 JE	5e55

0x6118 MOV	%RSI,%R8

0x611b MOV	%RSI,%R9

0x611e TESTB	$0x1c,0x60(%RSP)

0x6123 MOV	0x88(%RSP),%RCX

0x612b MOV	0x70(%RSP),%RDX

0x6130 JE	5ec2

0x6136 VMOVQ	%XMM0,%XMM0

0x613a MOV	0x250(%RSP),%RSI

0x6142 MOV	0x30(%RSP),%RDI

  (68) 0x6147 LEA	(%RAX,%R8,1),%R9D

  (68) 0x614b VCVTPS2PD	(%RCX,%R9,4),%YMM1

  (68) 0x6151 LEA	(%RDI,%R8,1),%R9D

  (68) 0x6155 VCVTPS2PD	(%RDX,%R9,4),%YMM2

  (68) 0x615b VFMADD231PD	%YMM2,%YMM1,%YMM0

  (68) 0x6160 ADD	$0x4,%R8

  (68) 0x6164 CMP	%R8,%RSI

  (68) 0x6167 JNE	6147

0x6169 VEXTRACTF128	$0x1,%YMM0,%XMM1

0x616f VADDPD	%XMM1,%XMM0,%XMM0

0x6173 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x6178 VADDSD	%XMM1,%XMM0,%XMM0

0x617c MOV	%RSI,%R9

0x617f CMP	%ESI,0x38(%RSP)

0x6183 JE	5e55

0x6189 JMP	5ec2

/home/eoseret/llm-attention/attention_v2.cpp: 27 - 33

--------------------------------------------------------------------------------

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.41
CQA speedup if FP arith vectorized	1.04
CQA speedup if fully vectorized	1.52
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.46
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.50
CQA cycles if no scalar integer	6.83
CQA cycles if FP arith vectorized	15.87
CQA cycles if fully vectorized	10.85
Front-end cycles	16.50
P0 cycles	9.80
P1 cycles	9.90
P2 cycles	11.33
P3 cycles	11.33
P4 cycles	1.00
P5 cycles	9.70
P6 cycles	9.80
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	9.80
P11 cycles	11.33
DIV/SQRT cycles	3.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	98.00
Nb uops	99.00
Nb loads	34.00
Nb stores	2.00
Nb stack references	16.00
FLOP/cycle	2.36
Nb FLOP add-sub	38.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.48
Bytes prefetched	0.00
Bytes loaded	227.00
Bytes stored	12.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	29.63
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	42.86
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	41.67
Vector-efficiency ratio all	21.12
Vector-efficiency ratio load	9.74
Vector-efficiency ratio store	9.38
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	39.29
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	16.80

Metric	Value
CQA speedup if no scalar integer	2.41
CQA speedup if FP arith vectorized	1.04
CQA speedup if fully vectorized	1.52
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.46
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.50
CQA cycles if no scalar integer	6.83
CQA cycles if FP arith vectorized	15.87
CQA cycles if fully vectorized	10.85
Front-end cycles	16.50
P0 cycles	9.80
P1 cycles	9.90
P2 cycles	11.33
P3 cycles	11.33
P4 cycles	1.00
P5 cycles	9.70
P6 cycles	9.80
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	9.80
P11 cycles	11.33
DIV/SQRT cycles	3.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	98.00
Nb uops	99.00
Nb loads	34.00
Nb stores	2.00
Nb stack references	16.00
FLOP/cycle	2.36
Nb FLOP add-sub	38.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.48
Bytes prefetched	0.00
Bytes loaded	227.00
Bytes stored	12.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	29.63
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	42.86
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	41.67
Vector-efficiency ratio all	21.12
Vector-efficiency ratio load	9.74
Vector-efficiency ratio store	9.38
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	39.29
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	16.80

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-clang-gnr512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:27-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:27,30,33.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=23
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 23 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.50 to 6.83 cycles (2.41x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 21% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 16.50 to 10.85 cycles (1.52x speedup).

Details

29% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
42% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
41% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:30
- /home/eoseret/llm-attention/attention_v2.cpp:30

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 4 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 39 FP arithmetical operations:

38: addition or subtraction
1: divide

The binary loop is loading 227 bytes (28 double precision FP elements). The binary loop is storing 12 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.16 FP operations per loaded or stored byte.

General properties

nb instructions	98
nb uops	99
loop length	491
used x86 registers	12
used mmx registers	0
used xmm registers	4
used ymm registers	2
used zmm registers	4
nb stack references	16

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.50 cycles
front end	16.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	9.80	9.90	11.33	11.33	1.00	9.70	9.80	1.00	1.00	1.00	9.80	11.33
cycles	9.80	9.90	11.33	11.33	1.00	9.70	9.80	1.00	1.00	1.00	9.80	11.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

3.00

Cycles summary

Front-end	16.50
Dispatch	11.33
DIV/SQRT	3.00
Overall L1	16.50

Vectorization ratios

INT

all	8%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	72%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	87%

INT+FP

all	29%
load	0%
store	0%
mul	0%
add-sub	42%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	41%

Vector efficiency ratios

INT

all	12%
load	9%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	38%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	59%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	26%

INT+FP

all	21%
load	9%
store	9%
mul	12%
add-sub	39%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.50 cycles. At this rate:

7% of peak load performance is reached (13.76 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.73 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 16.50 to 11.33 cycles (1.46x speedup).

ASM code

In the binary file, the address of the loop is: 5e92

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VDIVSS 0x3a4(%RSP),%XMM0,%XMM0	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	11-12	3	scal (6.3%)
MOV 0x2c0(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RCX,%RDI,1),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV 0xb0(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RCX,%R8,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP 0x98(%RSP),%RDI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 5e04 <main+0x2584>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CMPL $0x4,0x38(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
MOV %RDI,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JB 5ebf <main+0x263f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDI,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD 0xa8(%RSP),%R8D	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
SETB %R8B	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
OR 0x200(%RSP),%R8B	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	N/A
JE 6031 <main+0x27b1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
TESTB $0x3,0x60(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	2	0.33	scal (1.6%)
JE 5f2b <main+0x26ab>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x80(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R13,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
IMUL %R9,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD 0x30(%RSP),%R10	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV 0x1f0(%RSP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x88(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x70(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 5f3b <main+0x26bb>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x88(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x70(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x38(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %RCX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMP $-0x4,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x458(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JA 5e55 <main+0x25d5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x3(%R8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x80(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
IMUL %R13,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOV 0x30(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RBX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
LEA 0x2(%R8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RBX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R13,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
IMUL %R8,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RBX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
LEA 0x1(%R8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13,%RBX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD 0x30(%RSP),%RBX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 5e55 <main+0x25d5>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
CMPL $0x20,0x38(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JAE 604d <main+0x27cd>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x88(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x70(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 6136 <main+0x28b6>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPXOR %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV 0x88(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x448(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x70(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDPD %ZMM0,%ZMM1,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM2,%ZMM3,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM0,%ZMM1,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM0,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
CMP %ESI,0x38(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JE 5e55 <main+0x25d5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
TESTB $0x1c,0x60(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	2	0.33	scal (1.6%)
MOV 0x88(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x70(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JE 5ec2 <main+0x2642>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVQ %XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV 0x250(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
MOV %RSI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %ESI,0x38(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JE 5e55 <main+0x25d5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 5ec2 <main+0x2642>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-clang-gnr512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:27-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:27,30,33.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=23
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.50 to 6.83 cycles (2.41x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

29% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
42% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
41% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:30
- /home/eoseret/llm-attention/attention_v2.cpp:30

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 39 FP arithmetical operations:

38: addition or subtraction
1: divide

The binary loop is loading 227 bytes (28 double precision FP elements). The binary loop is storing 12 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.16 FP operations per loaded or stored byte.

General properties

nb instructions	98
nb uops	99
loop length	491
used x86 registers	12
used mmx registers	0
used xmm registers	4
used ymm registers	2
used zmm registers	4
nb stack references	16

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.50 cycles
front end	16.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	9.80	9.90	11.33	11.33	1.00	9.70	9.80	1.00	1.00	1.00	9.80	11.33
cycles	9.80	9.90	11.33	11.33	1.00	9.70	9.80	1.00	1.00	1.00	9.80	11.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

3.00

Cycles summary

Front-end	16.50
Dispatch	11.33
DIV/SQRT	3.00
Overall L1	16.50

Vectorization ratios

INT

all	8%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	72%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	87%

INT+FP

all	29%
load	0%
store	0%
mul	0%
add-sub	42%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	41%

Vector efficiency ratios

INT

all	12%
load	9%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	38%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	59%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	26%

INT+FP

all	21%
load	9%
store	9%
mul	12%
add-sub	39%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.50 cycles. At this rate:

7% of peak load performance is reached (13.76 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.73 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 5e92

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VDIVSS 0x3a4(%RSP),%XMM0,%XMM0	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	11-12	3	scal (6.3%)
MOV 0x2c0(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RCX,%RDI,1),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV 0xb0(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RCX,%R8,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP 0x98(%RSP),%RDI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JE 5e04 <main+0x2584>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CMPL $0x4,0x38(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
MOV %RDI,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JB 5ebf <main+0x263f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDI,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD 0xa8(%RSP),%R8D	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
SETB %R8B	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
OR 0x200(%RSP),%R8B	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	N/A
JE 6031 <main+0x27b1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
TESTB $0x3,0x60(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	2	0.33	scal (1.6%)
JE 5f2b <main+0x26ab>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x80(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R13,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
IMUL %R9,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD 0x30(%RSP),%R10	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV 0x1f0(%RSP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x88(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x70(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 5f3b <main+0x26bb>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x88(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x70(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x38(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %RCX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMP $-0x4,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x458(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JA 5e55 <main+0x25d5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x3(%R8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x80(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
IMUL %R13,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOV 0x30(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RBX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
LEA 0x2(%R8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RBX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R13,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
IMUL %R8,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RBX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
LEA 0x1(%R8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13,%RBX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD 0x30(%RSP),%RBX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 5e55 <main+0x25d5>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
CMPL $0x20,0x38(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JAE 604d <main+0x27cd>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x88(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x70(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 6136 <main+0x28b6>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPXOR %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV 0x88(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x448(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x70(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDPD %ZMM0,%ZMM1,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM2,%ZMM3,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM0,%ZMM1,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM0,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
CMP %ESI,0x38(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JE 5e55 <main+0x25d5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
TESTB $0x1c,0x60(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	2	0.33	scal (1.6%)
MOV 0x88(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x70(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JE 5ec2 <main+0x2642>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVQ %XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV 0x250(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
MOV %RSI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %ESI,0x38(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JE 5e55 <main+0x25d5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 5ec2 <main+0x2642>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code