OV - attention-clang-gnr512 - Loop 60 - attention-clang-gnr512

	Loop Id: 60	Module: attention-clang-gnr512	Source: attention_v2.cpp:52-53	Coverage: 0.13%

0x6f0d VMOVAPS	%YMM2,0x140(%RSP)    [1]

0x6f16 VMOVUPS	(%RDI,%RBX,4),%YMM0    [2]

0x6f1b VSUBPS	0x40(%RSP),%YMM0,%YMM0    [1]

0x6f21 VMOVAPS	%YMM0,0x2c0(%RSP)    [1]

0x6f2a VEXTRACTF128	$0x1,%YMM0,%XMM0

0x6f30 VMOVAPS	%XMM0,0x200(%RSP)    [1]

0x6f39 MOV	%R9,%R13

0x6f3c VZEROUPPER

0x6f3f CALL	1160 <expf@plt>

0x6f44 VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x6f4d VMOVSHDUP	0x200(%RSP),%XMM0    [1]

0x6f56 CALL	1160 <expf@plt>

0x6f5b VMOVAPS	0xc0(%RSP),%XMM1    [1]

0x6f64 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x6f6a VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x6f73 VPERMILPD	$0x1,0x200(%RSP),%XMM0    [1]

0x6f7e CALL	1160 <expf@plt>

0x6f83 VMOVAPS	0xc0(%RSP),%XMM1    [1]

0x6f8c VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x6f92 VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x6f9b VPSHUFD	$-0x1,0x200(%RSP),%XMM0    [1]

0x6fa5 CALL	1160 <expf@plt>

0x6faa VMOVAPS	0xc0(%RSP),%XMM1    [1]

0x6fb3 VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x6fb9 VMOVAPS	%XMM0,0x200(%RSP)    [1]

0x6fc2 VMOVAPS	0x2c0(%RSP),%YMM0    [1]

0x6fcb VZEROUPPER

0x6fce CALL	1160 <expf@plt>

0x6fd3 VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x6fdc VMOVSHDUP	0x2c0(%RSP),%XMM0    [1]

0x6fe5 CALL	1160 <expf@plt>

0x6fea VMOVAPS	0xc0(%RSP),%XMM1    [1]

0x6ff3 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x6ff9 VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x7002 VPERMILPD	$0x1,0x2c0(%RSP),%XMM0    [1]

0x700d CALL	1160 <expf@plt>

0x7012 VMOVAPS	0xc0(%RSP),%XMM1    [1]

0x701b VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x7021 VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x702a VPSHUFD	$-0x1,0x2c0(%RSP),%XMM0    [1]

0x7034 CALL	1160 <expf@plt>

0x7039 VMOVAPS	0x140(%RSP),%YMM2    [1]

0x7042 MOV	%R13,%R9

0x7045 MOV	0x30(%RSP),%RDI    [1]

0x704a VMOVAPS	0xc0(%RSP),%XMM1    [1]

0x7053 VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x7059 VINSERTF128	$0x1,0x200(%RSP),%YMM0,%YMM0    [1]

0x7064 VADDPS	%YMM2,%YMM0,%YMM2

0x7068 ADD	$0x8,%RBX

0x706c CMP	%RBX,%R13

0x706f JNE	6f0d

/home/eoseret/llm-attention/attention_v2.cpp: 52 - 53

--------------------------------------------------------------------------------

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.20
CQA speedup if FP arith vectorized	1.18
CQA speedup if fully vectorized	4.86
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:52-53
Source loop unroll info	unrolled by 64
Source loop unroll confidence level	max
Unroll/vectorization loop type	intermediate
Unroll factor	8
CQA cycles	10.83
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	9.19
CQA cycles if fully vectorized	2.23
Front-end cycles	10.83
P0 cycles	1.50
P1 cycles	4.00
P2 cycles	6.00
P3 cycles	6.00
P4 cycles	9.00
P5 cycles	9.00
P6 cycles	0.50
P7 cycles	9.00
P8 cycles	9.00
P9 cycles	9.00
P10 cycles	0.00
P11 cycles	6.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	51.00
Nb uops	65.00
Nb loads	18.00
Nb stores	10.00
Nb stack references	6.00
FLOP/cycle	1.48
Nb FLOP add-sub	16.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	49.48
Bytes prefetched	0.00
Bytes loaded	344.00
Bytes stored	192.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	81.58
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	53.33
Vector-efficiency ratio all	25.66
Vector-efficiency ratio load	29.41
Vector-efficiency ratio store	30.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.67

Metric	Value
CQA speedup if no scalar integer	1.20
CQA speedup if FP arith vectorized	1.18
CQA speedup if fully vectorized	4.86
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:52-53
Source loop unroll info	unrolled by 64
Source loop unroll confidence level	max
Unroll/vectorization loop type	intermediate
Unroll factor	8
CQA cycles	10.83
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	9.19
CQA cycles if fully vectorized	2.23
Front-end cycles	10.83
P0 cycles	1.50
P1 cycles	4.00
P2 cycles	6.00
P3 cycles	6.00
P4 cycles	9.00
P5 cycles	9.00
P6 cycles	0.50
P7 cycles	9.00
P8 cycles	9.00
P9 cycles	9.00
P10 cycles	0.00
P11 cycles	6.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	51.00
Nb uops	65.00
Nb loads	18.00
Nb stores	10.00
Nb stack references	6.00
FLOP/cycle	1.48
Nb FLOP add-sub	16.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	49.48
Bytes prefetched	0.00
Bytes loaded	344.00
Bytes stored	192.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	81.58
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	53.33
Vector-efficiency ratio all	25.66
Vector-efficiency ratio load	29.41
Vector-efficiency ratio store	30.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.67

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:52-53
Module	attention-clang-gnr512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:52-53.

It is intermediate loop of related source loop which is unrolled by 64 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.83 to 9.00 cycles (1.20x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is partially vectorized. Only 25% of vector register length is used (average across all SSE/AVX instructions).

Details

81% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

53% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

expf@plt: 8 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VINSERTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
VPERMILPD: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
VPSHUFD: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
VZEROUPPER: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
VINSERTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

2 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

16: addition or subtraction

The binary loop is loading 344 bytes (86 single precision FP elements). The binary loop is storing 192 bytes (48 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	51
nb uops	65
loop length	360
used x86 registers	5
used mmx registers	0
used xmm registers	2
used ymm registers	2
used zmm registers	0
nb stack references	6

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.83 cycles
front end	10.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.50	4.00	6.00	6.00	9.00	9.00	0.50	9.00	9.00	9.00	0.00	6.00
cycles	1.50	4.00	6.00	6.00	9.00	9.00	0.50	9.00	9.00	9.00	0.00	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	10.83
Dispatch	9.00
Data deps.	2.00
Overall L1	10.83

Vectorization ratios

INT

all	80%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	80%

all	81%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

INT+FP

all	81%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	53%

Vector efficiency ratios

INT

all	22%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	22%

all	26%
load	30%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

INT+FP

all	25%
load	29%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.83 cycles. At this rate:

16% of peak load performance is reached (31.75 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (17.72 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 10.83 to 9.00 cycles (1.20x speedup).

ASM code

In the binary file, the address of the loop is: 6f0d

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVAPS %YMM2,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS (%RDI,%RBX,4),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPS 0x40(%RSP),%YMM0,%YMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (50.0%)
VMOVAPS %YMM0,0x2c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x200(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV %R9,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x200(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x200(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x200(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x200(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPS 0x2c0(%RSP),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x2c0(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x2c0(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x2c0(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x140(%RSP),%YMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
MOV %R13,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x30(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0x200(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	3	0.33	vect (25.0%)
VADDPS %YMM2,%YMM0,%YMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x8,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RBX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 6f0d <main+0x368d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:52-53
Module	attention-clang-gnr512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:52-53.

It is intermediate loop of related source loop which is unrolled by 64 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.83 to 9.00 cycles (1.20x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Unrolling/vectorization cost

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is partially vectorized. Only 25% of vector register length is used (average across all SSE/AVX instructions).

Details

81% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

53% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

expf@plt: 8 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VINSERTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
VPERMILPD: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
VPSHUFD: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
VZEROUPPER: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
VINSERTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

2 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

16: addition or subtraction

The binary loop is loading 344 bytes (86 single precision FP elements). The binary loop is storing 192 bytes (48 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	51
nb uops	65
loop length	360
used x86 registers	5
used mmx registers	0
used xmm registers	2
used ymm registers	2
used zmm registers	0
nb stack references	6

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.83 cycles
front end	10.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.50	4.00	6.00	6.00	9.00	9.00	0.50	9.00	9.00	9.00	0.00	6.00
cycles	1.50	4.00	6.00	6.00	9.00	9.00	0.50	9.00	9.00	9.00	0.00	6.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	10.83
Dispatch	9.00
Data deps.	2.00
Overall L1	10.83

Vectorization ratios

INT

all	80%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	80%

all	81%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

INT+FP

all	81%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	53%

Vector efficiency ratios

INT

all	22%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	22%

all	26%
load	30%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

INT+FP

all	25%
load	29%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.83 cycles. At this rate:

16% of peak load performance is reached (31.75 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (17.72 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 6f0d

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVAPS %YMM2,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS (%RDI,%RBX,4),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPS 0x40(%RSP),%YMM0,%YMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (50.0%)
VMOVAPS %YMM0,0x2c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x200(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV %R9,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x200(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x200(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x200(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x200(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPS 0x2c0(%RSP),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x2c0(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x2c0(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x2c0(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x140(%RSP),%YMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
MOV %R13,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x30(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0x200(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	3	0.33	vect (25.0%)
VADDPS %YMM2,%YMM0,%YMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x8,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %RBX,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 6f0d <main+0x368d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code