OV - attention-clang-gnr512 - Loop 52 - attention-clang-gnr512

	Loop Id: 52	Module: attention-clang-gnr512	Source: attention_v2.cpp:27-33	Coverage: 1.07%

0x7687 VCVTSD2SS	%XMM0,%XMM0,%XMM0

0x768b MOV	0x30(%RSP),%RCX

0x7690 LEA	(%RCX,%RDI,1),%R8D

0x7694 MOV	0x1e8(%RSP),%R9

0x769c VMOVSS	%XMM0,(%R9,%R8,4)

0x76a2 INC	%RDI

0x76a5 CMP	0x38(%RSP),%RDI

0x76aa MOV	0x60(%RSP),%R8

0x76af JE	763d

0x76b1 VXORPS	%XMM0,%XMM0,%XMM0

0x76b5 CMP	$0x4,%R13D

0x76b9 JB	76d8

0x76bb MOV	%EDI,%R8D

0x76be ADD	0x3c0(%RSP),%R8D

0x76c6 SETB	%R8B

0x76ca OR	0x2c0(%RSP),%R8B

0x76d2 JE	7849

0x76d8 XOR	%R9D,%R9D

0x76db MOV	0x460(%RSP),%R11

0x76e3 TEST	%R11,%R11

0x76e6 JE	773b

0x76e8 MOV	0x60(%RSP),%R13

0x76ed MOV	%R13,%R10

0x76f0 IMUL	%R9,%R10

0x76f4 ADD	%RDI,%R10

0x76f7 MOV	%R9,%R8

0x76fa MOV	0x90(%RSP),%RSI

0x7702 MOV	0x78(%RSP),%RDX

0x7707 NOPW	(%RAX,%RAX,1)

  (54) 0x7710 LEA	(%RAX,%R8,1),%EBX

  (54) 0x7714 VMOVSS	(%RDX,%RBX,4),%XMM1

  (54) 0x7719 VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (54) 0x771d MOV	%R10D,%EBX

  (54) 0x7720 VMOVSS	(%RSI,%RBX,4),%XMM2

  (54) 0x7725 VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (54) 0x7729 VFMADD231SD	%XMM2,%XMM1,%XMM0

  (54) 0x772e INC	%R8

  (54) 0x7731 ADD	%R13,%R10

  (54) 0x7734 DEC	%R11

  (54) 0x7737 JNE	7710

0x7739 JMP	774b

0x773b MOV	%R9,%R8

0x773e MOV	0x90(%RSP),%RSI

0x7746 MOV	0x78(%RSP),%RDX

0x774b MOV	0x98(%RSP),%R13

0x7753 SUB	%R13,%R9

0x7756 CMP	$-0x4,%R9

0x775a MOV	0x2b8(%RSP),%RCX

0x7762 JA	7687

0x7768 LEA	0x3(%R8),%R9

0x776c MOV	0x60(%RSP),%R13

0x7771 IMUL	%R13,%R9

0x7775 ADD	%RDI,%R9

0x7778 LEA	0x2(%R8),%R10

0x777c IMUL	%R13,%R10

0x7780 ADD	%RDI,%R10

0x7783 MOV	%R13,%R11

0x7786 IMUL	%R8,%R11

0x778a ADD	%RDI,%R11

0x778d LEA	0x1(%R8),%RBX

0x7791 IMUL	%R13,%RBX

0x7795 ADD	%RDI,%RBX

0x7798 NOPL	(%RAX,%RAX,1)

  (53) 0x77a0 LEA	(%RAX,%R8,1),%R13D

  (53) 0x77a4 VMOVSS	(%RDX,%R13,4),%XMM1

  (53) 0x77aa VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (53) 0x77ae MOV	%R11D,%R13D

  (53) 0x77b1 VMOVSS	(%RSI,%R13,4),%XMM2

  (53) 0x77b7 VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (53) 0x77bb LEA	0x1(%RAX,%R8,1),%R13D

  (53) 0x77c0 VMOVSS	(%RDX,%R13,4),%XMM3

  (53) 0x77c6 VCVTSS2SD	%XMM3,%XMM3,%XMM3

  (53) 0x77ca VFMADD213SD	%XMM0,%XMM1,%XMM2

  (53) 0x77cf MOV	%EBX,%R13D

  (53) 0x77d2 VMOVSS	(%RSI,%R13,4),%XMM0

  (53) 0x77d8 VCVTSS2SD	%XMM0,%XMM0,%XMM0

  (53) 0x77dc VFMADD213SD	%XMM2,%XMM3,%XMM0

  (53) 0x77e1 LEA	0x2(%RAX,%R8,1),%R13D

  (53) 0x77e6 VMOVSS	(%RDX,%R13,4),%XMM1

  (53) 0x77ec VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (53) 0x77f0 MOV	%R10D,%R13D

  (53) 0x77f3 VMOVSS	(%RSI,%R13,4),%XMM2

  (53) 0x77f9 VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (53) 0x77fd LEA	0x3(%RAX,%R8,1),%R13D

  (53) 0x7802 VMOVSS	(%RDX,%R13,4),%XMM3

  (53) 0x7808 VCVTSS2SD	%XMM3,%XMM3,%XMM3

  (53) 0x780c VFMADD213SD	%XMM0,%XMM1,%XMM2

  (53) 0x7811 MOV	%R9D,%R13D

  (53) 0x7814 VMOVSS	(%RSI,%R13,4),%XMM0

  (53) 0x781a MOV	0x98(%RSP),%R13

  (53) 0x7822 VCVTSS2SD	%XMM0,%XMM0,%XMM0

  (53) 0x7826 VFMADD213SD	%XMM2,%XMM3,%XMM0

  (53) 0x782b ADD	$0x4,%R8

  (53) 0x782f ADD	%RCX,%R9

  (53) 0x7832 ADD	%RCX,%R10

  (53) 0x7835 ADD	%RCX,%R11

  (53) 0x7838 ADD	%RCX,%RBX

  (53) 0x783b CMP	%R8,%R13

  (53) 0x783e JNE	77a0

0x7844 JMP	7687

0x7849 CMP	$0x20,%R13D

0x784d JAE	7864

0x784f XOR	%R8D,%R8D

0x7852 MOV	0x90(%RSP),%RCX

0x785a MOV	0x78(%RSP),%RDX

0x785f JMP	794f

0x7864 VXORPS	%XMM0,%XMM0,%XMM0

0x7868 XOR	%R8D,%R8D

0x786b VXORPS	%XMM1,%XMM1,%XMM1

0x786f VXORPS	%XMM2,%XMM2,%XMM2

0x7873 VXORPS	%XMM3,%XMM3,%XMM3

0x7877 MOV	0x440(%RSP),%R10

0x787f MOV	0x90(%RSP),%RCX

0x7887 MOV	0x78(%RSP),%RDX

  (55) 0x788c LEA	(%RAX,%R8,1),%R9D

  (55) 0x7890 VCVTPS2PD	(%RDX,%R9,4),%ZMM4

  (55) 0x7897 VCVTPS2PD	0x20(%RDX,%R9,4),%ZMM5

  (55) 0x789f VCVTPS2PD	0x40(%RDX,%R9,4),%ZMM6

  (55) 0x78a7 VCVTPS2PD	0x60(%RDX,%R9,4),%ZMM7

  (55) 0x78af LEA	(%RDI,%R8,1),%R9D

  (55) 0x78b3 VCVTPS2PD	(%RCX,%R9,4),%ZMM8

  (55) 0x78ba VCVTPS2PD	0x20(%RCX,%R9,4),%ZMM9

  (55) 0x78c2 VFMADD231PD	%ZMM8,%ZMM4,%ZMM0

  (55) 0x78c8 VFMADD231PD	%ZMM9,%ZMM5,%ZMM1

  (55) 0x78ce VCVTPS2PD	0x40(%RCX,%R9,4),%ZMM4

  (55) 0x78d6 VFMADD231PD	%ZMM4,%ZMM6,%ZMM2

  (55) 0x78dc VCVTPS2PD	0x60(%RCX,%R9,4),%ZMM4

  (55) 0x78e4 VFMADD231PD	%ZMM4,%ZMM7,%ZMM3

  (55) 0x78ea ADD	$0x20,%R8

  (55) 0x78ee CMP	%R8,%R10

  (55) 0x78f1 JNE	788c

0x78f3 VADDPD	%ZMM0,%ZMM1,%ZMM0

0x78f9 VADDPD	%ZMM2,%ZMM3,%ZMM1

0x78ff VADDPD	%ZMM0,%ZMM1,%ZMM0

0x7905 VEXTRACTF64X4	$0x1,%ZMM0,%YMM1

0x790c VADDPD	%ZMM1,%ZMM0,%ZMM0

0x7912 VEXTRACTF128	$0x1,%YMM0,%XMM1

0x7918 VADDPD	%XMM1,%XMM0,%XMM0

0x791c VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x7921 VADDSD	%XMM1,%XMM0,%XMM0

0x7925 CMP	%R10D,%R13D

0x7928 JE	7687

0x792e MOV	%R10,%R8

0x7931 MOV	%R10,%R9

0x7934 TESTB	$0x1c,0x80(%RSP)

0x793c MOV	0x90(%RSP),%RCX

0x7944 MOV	0x78(%RSP),%RDX

0x7949 JE	76db

0x794f VMOVQ	%XMM0,%XMM0

0x7953 MOV	0x450(%RSP),%R10

  (56) 0x795b LEA	(%RAX,%R8,1),%R9D

  (56) 0x795f VCVTPS2PD	(%RDX,%R9,4),%YMM1

  (56) 0x7965 LEA	(%RDI,%R8,1),%R9D

  (56) 0x7969 VCVTPS2PD	(%RCX,%R9,4),%YMM2

  (56) 0x796f VFMADD231PD	%YMM2,%YMM1,%YMM0

  (56) 0x7974 ADD	$0x4,%R8

  (56) 0x7978 CMP	%R8,%R10

  (56) 0x797b JNE	795b

0x797d VEXTRACTF128	$0x1,%YMM0,%XMM1

0x7983 VADDPD	%XMM1,%XMM0,%XMM0

0x7987 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x798c VADDSD	%XMM1,%XMM0,%XMM0

0x7990 MOV	%R10,%R9

0x7993 CMP	%R10D,%R13D

0x7996 JE	7687

0x799c JMP	76db

/home/eoseret/llm-attention/attention_v2.cpp: 27 - 33

--------------------------------------------------------------------------------

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.50
CQA speedup if FP arith vectorized	1.04
CQA speedup if fully vectorized	1.37
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.63
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.83
CQA cycles if no scalar integer	6.33
CQA cycles if FP arith vectorized	15.29
CQA cycles if fully vectorized	11.54
Front-end cycles	15.83
P0 cycles	9.70
P1 cycles	9.70
P2 cycles	8.00
P3 cycles	8.00
P4 cycles	0.50
P5 cycles	9.50
P6 cycles	9.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	9.60
P11 cycles	8.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	94.00
Nb uops	95.00
Nb loads	24.00
Nb stores	1.00
Nb stack references	14.00
FLOP/cycle	2.40
Nb FLOP add-sub	38.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.24
Bytes prefetched	0.00
Bytes loaded	174.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	39.02
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	60.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	24.43
Vector-efficiency ratio load	11.41
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.52

Metric	Value
CQA speedup if no scalar integer	2.50
CQA speedup if FP arith vectorized	1.04
CQA speedup if fully vectorized	1.37
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.63
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.83
CQA cycles if no scalar integer	6.33
CQA cycles if FP arith vectorized	15.29
CQA cycles if fully vectorized	11.54
Front-end cycles	15.83
P0 cycles	9.70
P1 cycles	9.70
P2 cycles	8.00
P3 cycles	8.00
P4 cycles	0.50
P5 cycles	9.50
P6 cycles	9.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	9.60
P11 cycles	8.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	94.00
Nb uops	95.00
Nb loads	24.00
Nb stores	1.00
Nb stack references	14.00
FLOP/cycle	2.40
Nb FLOP add-sub	38.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.24
Bytes prefetched	0.00
Bytes loaded	174.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	39.02
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	60.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	24.43
Vector-efficiency ratio load	11.41
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.52

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-clang-gnr512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:27-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:27,30,33.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=23
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 23 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.83 to 6.33 cycles (2.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 24% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 15.83 to 11.54 cycles (1.37x speedup).

Details

39% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
60% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:30
- /home/eoseret/llm-attention/attention_v2.cpp:30

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 4 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 38 FP arithmetical operations:

38: addition or subtraction

The binary loop is loading 174 bytes (21 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.21 FP operations per loaded or stored byte.

General properties

nb instructions	94
nb uops	95
loop length	452
used x86 registers	12
used mmx registers	0
used xmm registers	4
used ymm registers	2
used zmm registers	4
nb stack references	14

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.83 cycles
front end	15.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	9.70	9.70	8.00	8.00	0.50	9.50	9.50	0.50	0.50	0.50	9.60	8.00
cycles	9.70	9.70	8.00	8.00	0.50	9.50	9.50	0.50	0.50	0.50	9.60	8.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.83
Dispatch	9.70
Overall L1	15.83

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	80%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	90%

INT+FP

all	39%
load	0%
store	0%
mul	0%
add-sub	60%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

INT

all	11%
load	11%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	38%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	59%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	26%

INT+FP

all	24%
load	11%
store	6%
mul	12%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.83 cycles. At this rate:

5% of peak load performance is reached (10.99 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.25 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 15.83 to 9.70 cycles (1.63x speedup).

ASM code

In the binary file, the address of the loop is: 76b1

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
MOV 0x30(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RCX,%RDI,1),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV 0x1e8(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%R9,%R8,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP 0x38(%RSP),%RDI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV 0x60(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 763d <main+0x3dbd>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CMP $0x4,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 76d8 <main+0x3e58>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDI,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD 0x3c0(%RSP),%R8D	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
SETB %R8B	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
OR 0x2c0(%RSP),%R8B	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	N/A
JE 7849 <main+0x3fc9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x460(%RSP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
TEST %R11,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 773b <main+0x3ebb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x60(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R13,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R9,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDI,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x90(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x78(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 774b <main+0x3ecb>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x90(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x78(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x98(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %R13,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP $-0x4,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x2b8(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JA 7687 <main+0x3e07>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x3(%R8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x60(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R13,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDI,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x2(%R8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDI,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R13,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
IMUL %R8,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
LEA 0x1(%R8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13,%RBX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 7687 <main+0x3e07>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
CMP $0x20,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 7864 <main+0x3fe4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x90(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 794f <main+0x40cf>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV 0x440(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x90(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDPD %ZMM0,%ZMM1,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM2,%ZMM3,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM0,%ZMM1,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM0,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
CMP %R10D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 7687 <main+0x3e07>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R10,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TESTB $0x1c,0x80(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	2	0.33	scal (1.6%)
MOV 0x90(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JE 76db <main+0x3e5b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVQ %XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV 0x450(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
MOV %R10,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JE 7687 <main+0x3e07>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 76db <main+0x3e5b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-clang-gnr512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:27-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:27,30,33.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=23
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 15.83 to 6.33 cycles (2.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

39% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
60% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:30
- /home/eoseret/llm-attention/attention_v2.cpp:30

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 38 FP arithmetical operations:

38: addition or subtraction

The binary loop is loading 174 bytes (21 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.21 FP operations per loaded or stored byte.

General properties

nb instructions	94
nb uops	95
loop length	452
used x86 registers	12
used mmx registers	0
used xmm registers	4
used ymm registers	2
used zmm registers	4
nb stack references	14

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.83 cycles
front end	15.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	9.70	9.70	8.00	8.00	0.50	9.50	9.50	0.50	0.50	0.50	9.60	8.00
cycles	9.70	9.70	8.00	8.00	0.50	9.50	9.50	0.50	0.50	0.50	9.60	8.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.83
Dispatch	9.70
Overall L1	15.83

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	80%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	90%

INT+FP

all	39%
load	0%
store	0%
mul	0%
add-sub	60%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Vector efficiency ratios

INT

all	11%
load	11%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	38%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	59%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	26%

INT+FP

all	24%
load	11%
store	6%
mul	12%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.83 cycles. At this rate:

5% of peak load performance is reached (10.99 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.25 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 76b1

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
MOV 0x30(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RCX,%RDI,1),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV 0x1e8(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%R9,%R8,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP 0x38(%RSP),%RDI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV 0x60(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 763d <main+0x3dbd>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CMP $0x4,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 76d8 <main+0x3e58>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDI,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD 0x3c0(%RSP),%R8D	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
SETB %R8B	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
OR 0x2c0(%RSP),%R8B	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	N/A
JE 7849 <main+0x3fc9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x460(%RSP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
TEST %R11,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 773b <main+0x3ebb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x60(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R13,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R9,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDI,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x90(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x78(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 774b <main+0x3ecb>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x90(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x78(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x98(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %R13,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP $-0x4,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x2b8(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JA 7687 <main+0x3e07>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x3(%R8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x60(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R13,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDI,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x2(%R8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %RDI,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R13,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
IMUL %R8,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
LEA 0x1(%R8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13,%RBX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RDI,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 7687 <main+0x3e07>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
CMP $0x20,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 7864 <main+0x3fe4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x90(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 794f <main+0x40cf>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV 0x440(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x90(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDPD %ZMM0,%ZMM1,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM2,%ZMM3,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VADDPD %ZMM0,%ZMM1,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VEXTRACTF64X4 $0x1,%ZMM0,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
VADDPD %ZMM1,%ZMM0,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
CMP %R10D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 7687 <main+0x3e07>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R10,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R10,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TESTB $0x1c,0x80(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	2	0.33	scal (1.6%)
MOV 0x90(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JE 76db <main+0x3e5b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVQ %XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV 0x450(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
MOV %R10,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R10D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JE 7687 <main+0x3e07>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 76db <main+0x3e5b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code