OV - attention-clang-gnr512 - Loop 49 - attention-clang-gnr512

	Loop Id: 49	Module: attention-clang-gnr512	Source: attention_v2.cpp:55-56	Coverage: 1.63%

0x7155 VMOVUPS	(%RDI,%R13,4),%ZMM0    [2]

0x715c VSUBPS	0x4c0(%RSP),%ZMM0,%ZMM0    [1]

0x7164 VMOVAPS	%ZMM0,0x200(%RSP)    [1]

0x716c VEXTRACTF32X4	$0x3,%ZMM0,%XMM0

0x7173 VMOVAPS	%XMM0,0x140(%RSP)    [1]

0x717c VZEROUPPER

0x717f CALL	1160 <expf@plt>

0x7184 VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x718d VMOVSHDUP	0x140(%RSP),%XMM0    [1]

0x7196 CALL	1160 <expf@plt>

0x719b VMOVAPS	0xc0(%RSP),%XMM1    [1]

0x71a4 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x71aa VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x71b3 VPERMILPD	$0x1,0x140(%RSP),%XMM0    [1]

0x71be CALL	1160 <expf@plt>

0x71c3 VMOVAPS	0xc0(%RSP),%XMM1    [1]

0x71cc VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x71d2 VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x71db VPSHUFD	$-0x1,0x140(%RSP),%XMM0    [1]

0x71e5 CALL	1160 <expf@plt>

0x71ea VMOVAPS	0xc0(%RSP),%XMM1    [1]

0x71f3 VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x71f9 VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x7202 VMOVAPS	0x200(%RSP),%ZMM0    [1]

0x720a VEXTRACTF32X4	$0x2,%ZMM0,%XMM0

0x7211 VMOVAPS	%XMM0,0x140(%RSP)    [1]

0x721a VZEROUPPER

0x721d CALL	1160 <expf@plt>

0x7222 VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x7228 VMOVSHDUP	0x140(%RSP),%XMM0    [1]

0x7231 CALL	1160 <expf@plt>

0x7236 VMOVAPS	0x40(%RSP),%XMM1    [1]

0x723c VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x7242 VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x7248 VPERMILPD	$0x1,0x140(%RSP),%XMM0    [1]

0x7253 CALL	1160 <expf@plt>

0x7258 VMOVAPS	0x40(%RSP),%XMM1    [1]

0x725e VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x7264 VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x726a VPSHUFD	$-0x1,0x140(%RSP),%XMM0    [1]

0x7274 CALL	1160 <expf@plt>

0x7279 VMOVAPS	0x40(%RSP),%XMM1    [1]

0x727f VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x7285 VINSERTF128	$0x1,0xc0(%RSP),%YMM0,%YMM0    [1]

0x7290 VMOVAPS	%YMM0,0xc0(%RSP)    [1]

0x7299 VMOVAPS	0x200(%RSP),%ZMM0    [1]

0x72a1 VEXTRACTF128	$0x1,%YMM0,%XMM0

0x72a7 VMOVAPS	%XMM0,0x140(%RSP)    [1]

0x72b0 VZEROUPPER

0x72b3 CALL	1160 <expf@plt>

0x72b8 VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x72be VMOVSHDUP	0x140(%RSP),%XMM0    [1]

0x72c7 CALL	1160 <expf@plt>

0x72cc VMOVAPS	0x40(%RSP),%XMM1    [1]

0x72d2 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x72d8 VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x72de VPERMILPD	$0x1,0x140(%RSP),%XMM0    [1]

0x72e9 CALL	1160 <expf@plt>

0x72ee VMOVAPS	0x40(%RSP),%XMM1    [1]

0x72f4 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x72fa VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x7300 VPSHUFD	$-0x1,0x140(%RSP),%XMM0    [1]

0x730a CALL	1160 <expf@plt>

0x730f VMOVAPS	0x40(%RSP),%XMM1    [1]

0x7315 VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x731b VMOVAPS	%XMM0,0x140(%RSP)    [1]

0x7324 VMOVAPS	0x200(%RSP),%ZMM0    [1]

0x732c VZEROUPPER

0x732f CALL	1160 <expf@plt>

0x7334 VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x733a VMOVSHDUP	0x200(%RSP),%XMM0    [1]

0x7343 CALL	1160 <expf@plt>

0x7348 VMOVAPS	0x40(%RSP),%XMM1    [1]

0x734e VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x7354 VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x735a VPERMILPD	$0x1,0x200(%RSP),%XMM0    [1]

0x7365 CALL	1160 <expf@plt>

0x736a VMOVAPS	0x40(%RSP),%XMM1    [1]

0x7370 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x7376 VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x737c VPSHUFD	$-0x1,0x200(%RSP),%XMM0    [1]

0x7386 CALL	1160 <expf@plt>

0x738b MOV	0x258(%RSP),%RDX    [1]

0x7393 MOV	0x30(%RSP),%RDI    [1]

0x7398 VMOVAPS	0x40(%RSP),%XMM1    [1]

0x739e VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x73a4 VINSERTF128	$0x1,0x140(%RSP),%YMM0,%YMM0    [1]

0x73af VINSERTF64X4	$0x1,0xc0(%RSP),%ZMM0,%ZMM0    [1]

0x73b8 VDIVPS	0x500(%RSP),%ZMM0,%ZMM0    [1]

0x73c0 VMOVUPS	%ZMM0,(%RDX,%R13,4)    [3]

0x73c7 ADD	$0x10,%R13

0x73cb CMP	%R13,0x480(%RSP)    [1]

0x73d3 JNE	7155

/home/eoseret/llm-attention/attention_v2.cpp: 55 - 56

--------------------------------------------------------------------------------

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.11
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.85
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.11
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:55-56
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	21.00
CQA cycles if no scalar integer	19.00
CQA cycles if FP arith vectorized	21.00
CQA cycles if fully vectorized	11.38
Front-end cycles	21.00
P0 cycles	5.33
P1 cycles	5.67
P2 cycles	12.00
P3 cycles	12.00
P4 cycles	18.00
P5 cycles	19.00
P6 cycles	1.00
P7 cycles	18.00
P8 cycles	18.00
P9 cycles	18.00
P10 cycles	0.00
P11 cycles	12.00
DIV/SQRT cycles	10.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	93.00
Nb uops	126.00
Nb loads	36.00
Nb stores	20.00
Nb stack references	9.00
FLOP/cycle	1.52
Nb FLOP add-sub	16.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	61.33
Bytes prefetched	0.00
Bytes loaded	856.00
Bytes stored	432.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	83.33
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	60.00
Vector-efficiency ratio all	30.21
Vector-efficiency ratio load	37.88
Vector-efficiency ratio store	33.75
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	18.33

Metric	Value
CQA speedup if no scalar integer	1.11
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.85
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.11
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:55-56
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	16
CQA cycles	21.00
CQA cycles if no scalar integer	19.00
CQA cycles if FP arith vectorized	21.00
CQA cycles if fully vectorized	11.38
Front-end cycles	21.00
P0 cycles	5.33
P1 cycles	5.67
P2 cycles	12.00
P3 cycles	12.00
P4 cycles	18.00
P5 cycles	19.00
P6 cycles	1.00
P7 cycles	18.00
P8 cycles	18.00
P9 cycles	18.00
P10 cycles	0.00
P11 cycles	12.00
DIV/SQRT cycles	10.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	93.00
Nb uops	126.00
Nb loads	36.00
Nb stores	20.00
Nb stack references	9.00
FLOP/cycle	1.52
Nb FLOP add-sub	16.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	61.33
Bytes prefetched	0.00
Bytes loaded	856.00
Bytes stored	432.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	83.33
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	60.00
Vector-efficiency ratio all	30.21
Vector-efficiency ratio load	37.88
Vector-efficiency ratio store	33.75
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	18.33

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:55-56
Module	attention-clang-gnr512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:55-56.

It is main loop of related source loop which is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 21.00 to 19.00 cycles (1.11x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 30% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 21.00 to 11.37 cycles (1.85x speedup).

Details

83% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

60% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

expf@plt: 16 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VDIVPS: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56
VINSERTF128: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
VINSERTF64X4: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56
VPERMILPD: 4 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
VPSHUFD: 4 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
VZEROUPPER: 4 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56

Vector unaligned load/store instructions

Detected 3 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56
VINSERTF128: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

2 AVX-512 instructions are processing arithmetic or math operations on single precision FP elements in vector mode (sixteen at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

16: addition or subtraction
16: divide

The binary loop is loading 856 bytes (214 single precision FP elements). The binary loop is storing 432 bytes (108 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	93
nb uops	126
loop length	644
used x86 registers	4
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	1
nb stack references	9

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	21.00 cycles
front end	21.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.33	5.67	12.00	12.00	18.00	19.00	1.00	18.00	18.00	18.00	0.00	12.00
cycles	5.33	5.67	12.00	12.00	18.00	19.00	1.00	18.00	18.00	18.00	0.00	12.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	10.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	21.00
Dispatch	19.00
DIV/SQRT	10.00
Data deps.	1.00
Overall L1	21.00

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	81%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	45%

INT+FP

all	83%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	60%

Vector efficiency ratios

INT

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	30%
load	39%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	15%

INT+FP

all	30%
load	37%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 21.00 cycles. At this rate:

21% of peak load performance is reached (40.76 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (20.57 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 21.00 to 19.00 cycles (1.11x speedup).

ASM code

In the binary file, the address of the loop is: 7155

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPS (%RDI,%R13,4),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPS 0x4c0(%RSP),%ZMM0,%ZMM0	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVAPS %ZMM0,0x200(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VEXTRACTF32X4 $0x3,%ZMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x140(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x140(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x140(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPS 0x200(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VEXTRACTF32X4 $0x2,%ZMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x140(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x140(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x140(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0xc0(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	3	0.33	vect (25.0%)
VMOVAPS %YMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPS 0x200(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x140(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x140(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x140(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPS 0x200(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x200(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x200(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x200(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x258(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0x140(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	3	0.33	vect (25.0%)
VINSERTF64X4 $0x1,0xc0(%RSP),%ZMM0,%ZMM0	2	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (50.0%)
VDIVPS 0x500(%RSP),%ZMM0,%ZMM0	4	2.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	17-18	10	vect (100.0%)
VMOVUPS %ZMM0,(%RDX,%R13,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x10,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R13,0x480(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JNE 7155 <main+0x38d5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:55-56
Module	attention-clang-gnr512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:55-56.

It is main loop of related source loop which is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

83% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

60% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

expf@plt: 16 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VDIVPS: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56
VINSERTF128: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
VINSERTF64X4: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56
VPERMILPD: 4 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
VPSHUFD: 4 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
VZEROUPPER: 4 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56

Vector unaligned load/store instructions

Detected 3 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56
VINSERTF128: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:56
- /home/eoseret/llm-attention/attention_v2.cpp:56

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

2 AVX-512 instructions are processing arithmetic or math operations on single precision FP elements in vector mode (sixteen at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

16: addition or subtraction
16: divide

The binary loop is loading 856 bytes (214 single precision FP elements). The binary loop is storing 432 bytes (108 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	93
nb uops	126
loop length	644
used x86 registers	4
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	1
nb stack references	9

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	21.00 cycles
front end	21.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.33	5.67	12.00	12.00	18.00	19.00	1.00	18.00	18.00	18.00	0.00	12.00
cycles	5.33	5.67	12.00	12.00	18.00	19.00	1.00	18.00	18.00	18.00	0.00	12.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	10.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	21.00
Dispatch	19.00
DIV/SQRT	10.00
Data deps.	1.00
Overall L1	21.00

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	81%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	45%

INT+FP

all	83%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	60%

Vector efficiency ratios

INT

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	30%
load	39%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	15%

INT+FP

all	30%
load	37%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 21.00 cycles. At this rate:

21% of peak load performance is reached (40.76 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (20.57 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 7155

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPS (%RDI,%R13,4),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPS 0x4c0(%RSP),%ZMM0,%ZMM0	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VMOVAPS %ZMM0,0x200(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VEXTRACTF32X4 $0x3,%ZMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x140(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x140(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x140(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPS 0x200(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VEXTRACTF32X4 $0x2,%ZMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x140(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x140(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x140(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0xc0(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	3	0.33	vect (25.0%)
VMOVAPS %YMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPS 0x200(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x140(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x140(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x140(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPS 0x200(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x200(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x200(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x200(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x258(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0x140(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	3	0.33	vect (25.0%)
VINSERTF64X4 $0x1,0xc0(%RSP),%ZMM0,%ZMM0	2	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (50.0%)
VDIVPS 0x500(%RSP),%ZMM0,%ZMM0	4	2.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	17-18	10	vect (100.0%)
VMOVUPS %ZMM0,(%RDX,%R13,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x10,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R13,0x480(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JNE 7155 <main+0x38d5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code