OV - attention-clang-gnr512 - Loop 47 - attention-clang-gnr512

	Loop Id: 47	Module: attention-clang-gnr512	Source: attention_v2.cpp:52-53	Coverage: 0.13%

0x6409 VMOVAPS	%ZMM1,0x1980(%RSP)    [1]

0x6411 VMOVUPS	-0xc0(%RBX,%R13,4),%ZMM0    [2]

0x6419 VMOVUPS	-0x80(%RBX,%R13,4),%ZMM1    [2]

0x6421 VMOVUPS	-0x40(%RBX,%R13,4),%ZMM2    [2]

0x6429 VMOVUPS	(%RBX,%R13,4),%ZMM3    [2]

0x6430 VMOVAPS	0x1940(%RSP),%ZMM4    [1]

0x6438 VSUBPS	%ZMM4,%ZMM0,%ZMM5

0x643e VMOVAPS	%ZMM5,0xc0(%RSP)    [1]

0x6446 VSUBPS	%ZMM4,%ZMM1,%ZMM0

0x644c VMOVAPS	%ZMM0,0x140(%RSP)    [1]

0x6454 VSUBPS	%ZMM4,%ZMM2,%ZMM0

0x645a VMOVAPS	%ZMM0,0x200(%RSP)    [1]

0x6462 VSUBPS	%ZMM4,%ZMM3,%ZMM0

0x6468 VMOVAPS	%ZMM0,0x2c0(%RSP)    [1]

0x6470 VEXTRACTF32X4	$0x3,%ZMM5,%XMM0

0x6477 VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x647d VZEROUPPER

0x6480 CALL	1160 <expf@plt>

0x6485 VMOVAPS	%XMM0,0x1c0(%RSP)    [1]

0x648e VMOVSHDUP	0x40(%RSP),%XMM0    [1]

0x6494 CALL	1160 <expf@plt>

0x6499 VMOVAPS	0x1c0(%RSP),%XMM1    [1]

0x64a2 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x64a8 VMOVAPS	%XMM0,0x1c0(%RSP)    [1]

0x64b1 VPERMILPD	$0x1,0x40(%RSP),%XMM0    [1]

0x64b9 CALL	1160 <expf@plt>

0x64be VMOVAPS	0x1c0(%RSP),%XMM1    [1]

0x64c7 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x64cd VMOVAPS	%XMM0,0x1c0(%RSP)    [1]

0x64d6 VPSHUFD	$-0x1,0x40(%RSP),%XMM0    [1]

0x64dd CALL	1160 <expf@plt>

0x64e2 VMOVAPS	0x1c0(%RSP),%XMM1    [1]

0x64eb VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x64f1 VMOVAPS	%XMM0,0x1c0(%RSP)    [1]

0x64fa VMOVAPS	0xc0(%RSP),%ZMM0    [1]

0x6502 VEXTRACTF32X4	$0x2,%ZMM0,%XMM0

0x6509 VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x650f VZEROUPPER

0x6512 CALL	1160 <expf@plt>

0x6517 VMOVAPS	%XMM0,0x120(%RSP)    [1]

0x6520 VMOVSHDUP	0x40(%RSP),%XMM0    [1]

0x6526 CALL	1160 <expf@plt>

0x652b VMOVAPS	0x120(%RSP),%XMM1    [1]

0x6534 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x653a VMOVAPS	%XMM0,0x120(%RSP)    [1]

0x6543 VPERMILPD	$0x1,0x40(%RSP),%XMM0    [1]

0x654b CALL	1160 <expf@plt>

0x6550 VMOVAPS	0x120(%RSP),%XMM1    [1]

0x6559 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x655f VMOVAPS	%XMM0,0x120(%RSP)    [1]

0x6568 VPSHUFD	$-0x1,0x40(%RSP),%XMM0    [1]

0x656f CALL	1160 <expf@plt>

0x6574 VMOVAPS	0x120(%RSP),%XMM1    [1]

0x657d VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x6583 VINSERTF128	$0x1,0x1c0(%RSP),%YMM0,%YMM0    [1]

0x658e VMOVAPS	%YMM0,0x1c0(%RSP)    [1]

0x6597 VMOVAPS	0xc0(%RSP),%ZMM0    [1]

0x659f VEXTRACTF128	$0x1,%YMM0,%XMM0

0x65a5 VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x65ab VZEROUPPER

0x65ae CALL	1160 <expf@plt>

0x65b3 VMOVAPS	%XMM0,0x120(%RSP)    [1]

0x65bc VMOVSHDUP	0x40(%RSP),%XMM0    [1]

0x65c2 CALL	1160 <expf@plt>

0x65c7 VMOVAPS	0x120(%RSP),%XMM1    [1]

0x65d0 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x65d6 VMOVAPS	%XMM0,0x120(%RSP)    [1]

0x65df VPERMILPD	$0x1,0x40(%RSP),%XMM0    [1]

0x65e7 CALL	1160 <expf@plt>

0x65ec VMOVAPS	0x120(%RSP),%XMM1    [1]

0x65f5 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x65fb VMOVAPS	%XMM0,0x120(%RSP)    [1]

0x6604 VPSHUFD	$-0x1,0x40(%RSP),%XMM0    [1]

0x660b CALL	1160 <expf@plt>

0x6610 VMOVAPS	0x120(%RSP),%XMM1    [1]

0x6619 VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x661f VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x6625 VMOVAPS	0xc0(%RSP),%ZMM0    [1]

0x662d VZEROUPPER

0x6630 CALL	1160 <expf@plt>

0x6635 VMOVAPS	%XMM0,0x120(%RSP)    [1]

0x663e VMOVSHDUP	0xc0(%RSP),%XMM0    [1]

0x6647 CALL	1160 <expf@plt>

0x664c VMOVAPS	0x120(%RSP),%XMM1    [1]

0x6655 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x665b VMOVAPS	%XMM0,0x120(%RSP)    [1]

0x6664 VPERMILPD	$0x1,0xc0(%RSP),%XMM0    [1]

0x666f CALL	1160 <expf@plt>

0x6674 VMOVAPS	0x120(%RSP),%XMM1    [1]

0x667d VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x6683 VMOVAPS	%XMM0,0x120(%RSP)    [1]

0x668c VPSHUFD	$-0x1,0xc0(%RSP),%XMM0    [1]

0x6696 CALL	1160 <expf@plt>

0x669b VMOVAPS	0x120(%RSP),%XMM1    [1]

0x66a4 VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x66aa VINSERTF128	$0x1,0x40(%RSP),%YMM0,%YMM0    [1]

0x66b2 VINSERTF64X4	$0x1,0x1c0(%RSP),%ZMM0,%ZMM0    [1]

0x66bb VMOVAPS	0x480(%RSP),%ZMM1    [1]

0x66c3 VADDPS	%ZMM1,%ZMM0,%ZMM1

0x66c9 VMOVAPS	%ZMM1,0x480(%RSP)    [1]

0x66d1 VMOVAPS	0x140(%RSP),%ZMM0    [1]

0x66d9 VEXTRACTF32X4	$0x3,%ZMM0,%XMM0

0x66e0 VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x66e9 VZEROUPPER

0x66ec CALL	1160 <expf@plt>

0x66f1 VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x66f7 VMOVSHDUP	0xc0(%RSP),%XMM0    [1]

0x6700 CALL	1160 <expf@plt>

0x6705 VMOVAPS	0x40(%RSP),%XMM1    [1]

0x670b VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x6711 VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x6717 VPERMILPD	$0x1,0xc0(%RSP),%XMM0    [1]

0x6722 CALL	1160 <expf@plt>

0x6727 VMOVAPS	0x40(%RSP),%XMM1    [1]

0x672d VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x6733 VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x6739 VPSHUFD	$-0x1,0xc0(%RSP),%XMM0    [1]

0x6743 CALL	1160 <expf@plt>

0x6748 VMOVAPS	0x40(%RSP),%XMM1    [1]

0x674e VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x6754 VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x675a VMOVAPS	0x140(%RSP),%ZMM0    [1]

0x6762 VEXTRACTF32X4	$0x2,%ZMM0,%XMM0

0x6769 VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x6772 VZEROUPPER

0x6775 CALL	1160 <expf@plt>

0x677a VMOVAPS	%XMM0,0x1c0(%RSP)    [1]

0x6783 VMOVSHDUP	0xc0(%RSP),%XMM0    [1]

0x678c CALL	1160 <expf@plt>

0x6791 VMOVAPS	0x1c0(%RSP),%XMM1    [1]

0x679a VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x67a0 VMOVAPS	%XMM0,0x1c0(%RSP)    [1]

0x67a9 VPERMILPD	$0x1,0xc0(%RSP),%XMM0    [1]

0x67b4 CALL	1160 <expf@plt>

0x67b9 VMOVAPS	0x1c0(%RSP),%XMM1    [1]

0x67c2 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x67c8 VMOVAPS	%XMM0,0x1c0(%RSP)    [1]

0x67d1 VPSHUFD	$-0x1,0xc0(%RSP),%XMM0    [1]

0x67db CALL	1160 <expf@plt>

0x67e0 VMOVAPS	0x1c0(%RSP),%XMM1    [1]

0x67e9 VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x67ef VINSERTF128	$0x1,0x40(%RSP),%YMM0,%YMM0    [1]

0x67f7 VMOVAPS	%YMM0,0x40(%RSP)    [1]

0x67fd VMOVAPS	0x140(%RSP),%ZMM0    [1]

0x6805 VEXTRACTF128	$0x1,%YMM0,%XMM0

0x680b VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x6814 VZEROUPPER

0x6817 CALL	1160 <expf@plt>

0x681c VMOVAPS	%XMM0,0x1c0(%RSP)    [1]

0x6825 VMOVSHDUP	0xc0(%RSP),%XMM0    [1]

0x682e CALL	1160 <expf@plt>

0x6833 VMOVAPS	0x1c0(%RSP),%XMM1    [1]

0x683c VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x6842 VMOVAPS	%XMM0,0x1c0(%RSP)    [1]

0x684b VPERMILPD	$0x1,0xc0(%RSP),%XMM0    [1]

0x6856 CALL	1160 <expf@plt>

0x685b VMOVAPS	0x1c0(%RSP),%XMM1    [1]

0x6864 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x686a VMOVAPS	%XMM0,0x1c0(%RSP)    [1]

0x6873 VPSHUFD	$-0x1,0xc0(%RSP),%XMM0    [1]

0x687d CALL	1160 <expf@plt>

0x6882 VMOVAPS	0x1c0(%RSP),%XMM1    [1]

0x688b VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x6891 VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x689a VMOVAPS	0x140(%RSP),%ZMM0    [1]

0x68a2 VZEROUPPER

0x68a5 CALL	1160 <expf@plt>

0x68aa VMOVAPS	%XMM0,0x1c0(%RSP)    [1]

0x68b3 VMOVSHDUP	0x140(%RSP),%XMM0    [1]

0x68bc CALL	1160 <expf@plt>

0x68c1 VMOVAPS	0x1c0(%RSP),%XMM1    [1]

0x68ca VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x68d0 VMOVAPS	%XMM0,0x1c0(%RSP)    [1]

0x68d9 VPERMILPD	$0x1,0x140(%RSP),%XMM0    [1]

0x68e4 CALL	1160 <expf@plt>

0x68e9 VMOVAPS	0x1c0(%RSP),%XMM1    [1]

0x68f2 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x68f8 VMOVAPS	%XMM0,0x1c0(%RSP)    [1]

0x6901 VPSHUFD	$-0x1,0x140(%RSP),%XMM0    [1]

0x690b CALL	1160 <expf@plt>

0x6910 VMOVAPS	0x1c0(%RSP),%XMM1    [1]

0x6919 VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x691f VINSERTF128	$0x1,0xc0(%RSP),%YMM0,%YMM0    [1]

0x692a VINSERTF64X4	$0x1,0x40(%RSP),%ZMM0,%ZMM0    [1]

0x6933 VMOVAPS	0x500(%RSP),%ZMM1    [1]

0x693b VADDPS	%ZMM1,%ZMM0,%ZMM1

0x6941 VMOVAPS	%ZMM1,0x500(%RSP)    [1]

0x6949 VMOVAPS	0x200(%RSP),%ZMM0    [1]

0x6951 VEXTRACTF32X4	$0x3,%ZMM0,%XMM0

0x6958 VMOVAPS	%XMM0,0x140(%RSP)    [1]

0x6961 VZEROUPPER

0x6964 CALL	1160 <expf@plt>

0x6969 VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x6972 VMOVSHDUP	0x140(%RSP),%XMM0    [1]

0x697b CALL	1160 <expf@plt>

0x6980 VMOVAPS	0xc0(%RSP),%XMM1    [1]

0x6989 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x698f VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x6998 VPERMILPD	$0x1,0x140(%RSP),%XMM0    [1]

0x69a3 CALL	1160 <expf@plt>

0x69a8 VMOVAPS	0xc0(%RSP),%XMM1    [1]

0x69b1 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x69b7 VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x69c0 VPSHUFD	$-0x1,0x140(%RSP),%XMM0    [1]

0x69ca CALL	1160 <expf@plt>

0x69cf VMOVAPS	0xc0(%RSP),%XMM1    [1]

0x69d8 VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x69de VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x69e7 VMOVAPS	0x200(%RSP),%ZMM0    [1]

0x69ef VEXTRACTF32X4	$0x2,%ZMM0,%XMM0

0x69f6 VMOVAPS	%XMM0,0x140(%RSP)    [1]

0x69ff VZEROUPPER

0x6a02 CALL	1160 <expf@plt>

0x6a07 VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x6a0d VMOVSHDUP	0x140(%RSP),%XMM0    [1]

0x6a16 CALL	1160 <expf@plt>

0x6a1b VMOVAPS	0x40(%RSP),%XMM1    [1]

0x6a21 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x6a27 VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x6a2d VPERMILPD	$0x1,0x140(%RSP),%XMM0    [1]

0x6a38 CALL	1160 <expf@plt>

0x6a3d VMOVAPS	0x40(%RSP),%XMM1    [1]

0x6a43 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x6a49 VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x6a4f VPSHUFD	$-0x1,0x140(%RSP),%XMM0    [1]

0x6a59 CALL	1160 <expf@plt>

0x6a5e VMOVAPS	0x40(%RSP),%XMM1    [1]

0x6a64 VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x6a6a VINSERTF128	$0x1,0xc0(%RSP),%YMM0,%YMM0    [1]

0x6a75 VMOVAPS	%YMM0,0xc0(%RSP)    [1]

0x6a7e VMOVAPS	0x200(%RSP),%ZMM0    [1]

0x6a86 VEXTRACTF128	$0x1,%YMM0,%XMM0

0x6a8c VMOVAPS	%XMM0,0x140(%RSP)    [1]

0x6a95 VZEROUPPER

0x6a98 CALL	1160 <expf@plt>

0x6a9d VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x6aa3 VMOVSHDUP	0x140(%RSP),%XMM0    [1]

0x6aac CALL	1160 <expf@plt>

0x6ab1 VMOVAPS	0x40(%RSP),%XMM1    [1]

0x6ab7 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x6abd VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x6ac3 VPERMILPD	$0x1,0x140(%RSP),%XMM0    [1]

0x6ace CALL	1160 <expf@plt>

0x6ad3 VMOVAPS	0x40(%RSP),%XMM1    [1]

0x6ad9 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x6adf VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x6ae5 VPSHUFD	$-0x1,0x140(%RSP),%XMM0    [1]

0x6aef CALL	1160 <expf@plt>

0x6af4 VMOVAPS	0x40(%RSP),%XMM1    [1]

0x6afa VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x6b00 VMOVAPS	%XMM0,0x140(%RSP)    [1]

0x6b09 VMOVAPS	0x200(%RSP),%ZMM0    [1]

0x6b11 VZEROUPPER

0x6b14 CALL	1160 <expf@plt>

0x6b19 VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x6b1f VMOVSHDUP	0x200(%RSP),%XMM0    [1]

0x6b28 CALL	1160 <expf@plt>

0x6b2d VMOVAPS	0x40(%RSP),%XMM1    [1]

0x6b33 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x6b39 VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x6b3f VPERMILPD	$0x1,0x200(%RSP),%XMM0    [1]

0x6b4a CALL	1160 <expf@plt>

0x6b4f VMOVAPS	0x40(%RSP),%XMM1    [1]

0x6b55 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x6b5b VMOVAPS	%XMM0,0x40(%RSP)    [1]

0x6b61 VPSHUFD	$-0x1,0x200(%RSP),%XMM0    [1]

0x6b6b CALL	1160 <expf@plt>

0x6b70 VMOVAPS	0x40(%RSP),%XMM1    [1]

0x6b76 VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x6b7c VINSERTF128	$0x1,0x140(%RSP),%YMM0,%YMM0    [1]

0x6b87 VINSERTF64X4	$0x1,0xc0(%RSP),%ZMM0,%ZMM0    [1]

0x6b90 VMOVAPS	0x4c0(%RSP),%ZMM1    [1]

0x6b98 VADDPS	%ZMM1,%ZMM0,%ZMM1

0x6b9e VMOVAPS	%ZMM1,0x4c0(%RSP)    [1]

0x6ba6 VMOVAPS	0x2c0(%RSP),%ZMM0    [1]

0x6bae VEXTRACTF32X4	$0x3,%ZMM0,%XMM0

0x6bb5 VMOVAPS	%XMM0,0x200(%RSP)    [1]

0x6bbe VZEROUPPER

0x6bc1 CALL	1160 <expf@plt>

0x6bc6 VMOVAPS	%XMM0,0x140(%RSP)    [1]

0x6bcf VMOVSHDUP	0x200(%RSP),%XMM0    [1]

0x6bd8 CALL	1160 <expf@plt>

0x6bdd VMOVAPS	0x140(%RSP),%XMM1    [1]

0x6be6 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x6bec VMOVAPS	%XMM0,0x140(%RSP)    [1]

0x6bf5 VPERMILPD	$0x1,0x200(%RSP),%XMM0    [1]

0x6c00 CALL	1160 <expf@plt>

0x6c05 VMOVAPS	0x140(%RSP),%XMM1    [1]

0x6c0e VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x6c14 VMOVAPS	%XMM0,0x140(%RSP)    [1]

0x6c1d VPSHUFD	$-0x1,0x200(%RSP),%XMM0    [1]

0x6c27 CALL	1160 <expf@plt>

0x6c2c VMOVAPS	0x140(%RSP),%XMM1    [1]

0x6c35 VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x6c3b VMOVAPS	%XMM0,0x140(%RSP)    [1]

0x6c44 VMOVAPS	0x2c0(%RSP),%ZMM0    [1]

0x6c4c VEXTRACTF32X4	$0x2,%ZMM0,%XMM0

0x6c53 VMOVAPS	%XMM0,0x200(%RSP)    [1]

0x6c5c VZEROUPPER

0x6c5f CALL	1160 <expf@plt>

0x6c64 VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x6c6d VMOVSHDUP	0x200(%RSP),%XMM0    [1]

0x6c76 CALL	1160 <expf@plt>

0x6c7b VMOVAPS	0xc0(%RSP),%XMM1    [1]

0x6c84 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x6c8a VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x6c93 VPERMILPD	$0x1,0x200(%RSP),%XMM0    [1]

0x6c9e CALL	1160 <expf@plt>

0x6ca3 VMOVAPS	0xc0(%RSP),%XMM1    [1]

0x6cac VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x6cb2 VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x6cbb VPSHUFD	$-0x1,0x200(%RSP),%XMM0    [1]

0x6cc5 CALL	1160 <expf@plt>

0x6cca VMOVAPS	0xc0(%RSP),%XMM1    [1]

0x6cd3 VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x6cd9 VINSERTF128	$0x1,0x140(%RSP),%YMM0,%YMM0    [1]

0x6ce4 VMOVAPS	%YMM0,0x140(%RSP)    [1]

0x6ced VMOVAPS	0x2c0(%RSP),%ZMM0    [1]

0x6cf5 VEXTRACTF128	$0x1,%YMM0,%XMM0

0x6cfb VMOVAPS	%XMM0,0x200(%RSP)    [1]

0x6d04 VZEROUPPER

0x6d07 CALL	1160 <expf@plt>

0x6d0c VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x6d15 VMOVSHDUP	0x200(%RSP),%XMM0    [1]

0x6d1e CALL	1160 <expf@plt>

0x6d23 VMOVAPS	0xc0(%RSP),%XMM1    [1]

0x6d2c VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x6d32 VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x6d3b VPERMILPD	$0x1,0x200(%RSP),%XMM0    [1]

0x6d46 CALL	1160 <expf@plt>

0x6d4b VMOVAPS	0xc0(%RSP),%XMM1    [1]

0x6d54 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x6d5a VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x6d63 VPSHUFD	$-0x1,0x200(%RSP),%XMM0    [1]

0x6d6d CALL	1160 <expf@plt>

0x6d72 VMOVAPS	0xc0(%RSP),%XMM1    [1]

0x6d7b VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x6d81 VMOVAPS	%XMM0,0x200(%RSP)    [1]

0x6d8a VMOVAPS	0x2c0(%RSP),%ZMM0    [1]

0x6d92 VZEROUPPER

0x6d95 CALL	1160 <expf@plt>

0x6d9a VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x6da3 VMOVSHDUP	0x2c0(%RSP),%XMM0    [1]

0x6dac CALL	1160 <expf@plt>

0x6db1 VMOVAPS	0xc0(%RSP),%XMM1    [1]

0x6dba VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x6dc0 VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x6dc9 VPERMILPD	$0x1,0x2c0(%RSP),%XMM0    [1]

0x6dd4 CALL	1160 <expf@plt>

0x6dd9 VMOVAPS	0xc0(%RSP),%XMM1    [1]

0x6de2 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x6de8 VMOVAPS	%XMM0,0xc0(%RSP)    [1]

0x6df1 VPSHUFD	$-0x1,0x2c0(%RSP),%XMM0    [1]

0x6dfb CALL	1160 <expf@plt>

0x6e00 VMOVAPS	0x1980(%RSP),%ZMM1    [1]

0x6e08 MOV	0x3f8(%RSP),%R10    [1]

0x6e10 VMOVAPS	0xc0(%RSP),%XMM2    [1]

0x6e19 VINSERTPS	$0x30,%XMM0,%XMM2,%XMM0

0x6e1f VINSERTF128	$0x1,0x200(%RSP),%YMM0,%YMM0    [1]

0x6e2a VINSERTF64X4	$0x1,0x140(%RSP),%ZMM0,%ZMM0    [1]

0x6e33 VADDPS	%ZMM1,%ZMM0,%ZMM1

0x6e39 ADD	$0x40,%R13

0x6e3d CMP	%R13,%R10

0x6e40 JNE	6409

/home/eoseret/llm-attention/attention_v2.cpp: 52 - 53

--------------------------------------------------------------------------------

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.07
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.78
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:52-53
Source loop unroll info	unrolled by 64
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	64
CQA cycles	81.17
CQA cycles if no scalar integer	76.00
CQA cycles if FP arith vectorized	81.17
CQA cycles if fully vectorized	45.50
Front-end cycles	81.17
P0 cycles	18.00
P1 cycles	18.00
P2 cycles	44.33
P3 cycles	44.33
P4 cycles	72.00
P5 cycles	76.00
P6 cycles	1.00
P7 cycles	72.00
P8 cycles	72.00
P9 cycles	72.00
P10 cycles	0.00
P11 cycles	44.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	364.00
Nb uops	487.00
Nb loads	133.00
Nb stores	80.00
Nb stack references	13.00
FLOP/cycle	1.58
Nb FLOP add-sub	128.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	62.39
Bytes prefetched	0.00
Bytes loaded	3336.00
Bytes stored	1728.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	83.78
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	60.00
Vector-efficiency ratio all	32.09
Vector-efficiency ratio load	37.88
Vector-efficiency ratio store	33.75
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.33

Metric	Value
CQA speedup if no scalar integer	1.07
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.78
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:52-53
Source loop unroll info	unrolled by 64
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	64
CQA cycles	81.17
CQA cycles if no scalar integer	76.00
CQA cycles if FP arith vectorized	81.17
CQA cycles if fully vectorized	45.50
Front-end cycles	81.17
P0 cycles	18.00
P1 cycles	18.00
P2 cycles	44.33
P3 cycles	44.33
P4 cycles	72.00
P5 cycles	76.00
P6 cycles	1.00
P7 cycles	72.00
P8 cycles	72.00
P9 cycles	72.00
P10 cycles	0.00
P11 cycles	44.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	364.00
Nb uops	487.00
Nb loads	133.00
Nb stores	80.00
Nb stack references	13.00
FLOP/cycle	1.58
Nb FLOP add-sub	128.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	62.39
Bytes prefetched	0.00
Bytes loaded	3336.00
Bytes stored	1728.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	83.78
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	60.00
Vector-efficiency ratio all	32.09
Vector-efficiency ratio load	37.88
Vector-efficiency ratio store	33.75
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.33

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:52-53
Module	attention-clang-gnr512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:52-53.

It is main loop of related source loop which is unrolled by 64 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 81.17 to 76.00 cycles (1.07x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 32% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 81.17 to 45.50 cycles (1.78x speedup).

Details

83% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

60% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

expf@plt: 64 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VINSERTF128: 8 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
VINSERTF64X4: 4 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
VPERMILPD: 16 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
VPSHUFD: 16 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
VZEROUPPER: 16 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53

Vector unaligned load/store instructions

Detected 12 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 4 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
VINSERTF128: 8 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

8 AVX-512 instructions are processing arithmetic or math operations on single precision FP elements in vector mode (sixteen at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 128 FP arithmetical operations:

128: addition or subtraction

The binary loop is loading 3336 bytes (834 single precision FP elements). The binary loop is storing 1728 bytes (432 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	364
nb uops	487
loop length	2621
used x86 registers	4
used mmx registers	0
used xmm registers	3
used ymm registers	1
used zmm registers	6
nb stack references	13

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	81.17 cycles
front end	81.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	18.00	18.00	44.33	44.33	72.00	76.00	1.00	72.00	72.00	72.00	0.00	44.33
cycles	18.00	18.00	44.33	44.33	72.00	76.00	1.00	72.00	72.00	72.00	0.00	44.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	81.17
Dispatch	76.00
Data deps.	1.00
Overall L1	81.17

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	81%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	45%

INT+FP

all	83%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	60%

Vector efficiency ratios

INT

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	32%
load	39%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	32%
load	37%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 81.17 cycles. At this rate:

21% of peak load performance is reached (41.10 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (21.29 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 81.17 to 76.00 cycles (1.07x speedup).

ASM code

In the binary file, the address of the loop is: 6409

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVAPS %ZMM1,0x1980(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPS -0xc0(%RBX,%R13,4),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPS -0x80(%RBX,%R13,4),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPS -0x40(%RBX,%R13,4),%ZMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPS (%RBX,%R13,4),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVAPS 0x1940(%RSP),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPS %ZMM4,%ZMM0,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPS %ZMM5,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VSUBPS %ZMM4,%ZMM1,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPS %ZMM0,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VSUBPS %ZMM4,%ZMM2,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPS %ZMM0,0x200(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VSUBPS %ZMM4,%ZMM3,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPS %ZMM0,0x2c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VEXTRACTF32X4 $0x3,%ZMM5,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x40(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1c0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x40(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1c0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x40(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1c0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPS 0xc0(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VEXTRACTF32X4 $0x2,%ZMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x120(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x40(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x120(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x120(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x40(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x120(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x120(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x40(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x120(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0x1c0(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	3	0.33	vect (25.0%)
VMOVAPS %YMM0,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPS 0xc0(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x120(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x40(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x120(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x120(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x40(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x120(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x120(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x40(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x120(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPS 0xc0(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x120(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0xc0(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x120(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x120(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0xc0(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x120(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x120(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0xc0(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x120(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0x40(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	3	0.33	vect (25.0%)
VINSERTF64X4 $0x1,0x1c0(%RSP),%ZMM0,%ZMM0	2	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (50.0%)
VMOVAPS 0x480(%RSP),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPS %ZMM1,%ZMM0,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPS %ZMM1,0x480(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVAPS 0x140(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VEXTRACTF32X4 $0x3,%ZMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0xc0(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0xc0(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0xc0(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPS 0x140(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VEXTRACTF32X4 $0x2,%ZMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0xc0(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1c0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0xc0(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1c0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0xc0(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1c0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0x40(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	3	0.33	vect (25.0%)
VMOVAPS %YMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPS 0x140(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0xc0(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1c0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0xc0(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1c0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0xc0(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1c0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPS 0x140(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x140(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1c0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x140(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1c0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x140(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1c0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0xc0(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	3	0.33	vect (25.0%)
VINSERTF64X4 $0x1,0x40(%RSP),%ZMM0,%ZMM0	2	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (50.0%)
VMOVAPS 0x500(%RSP),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPS %ZMM1,%ZMM0,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPS %ZMM1,0x500(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVAPS 0x200(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VEXTRACTF32X4 $0x3,%ZMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x140(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x140(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x140(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPS 0x200(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VEXTRACTF32X4 $0x2,%ZMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x140(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x140(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x140(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0xc0(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	3	0.33	vect (25.0%)
VMOVAPS %YMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPS 0x200(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x140(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x140(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x140(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPS 0x200(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x200(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x200(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x200(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0x140(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	3	0.33	vect (25.0%)
VINSERTF64X4 $0x1,0xc0(%RSP),%ZMM0,%ZMM0	2	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (50.0%)
VMOVAPS 0x4c0(%RSP),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPS %ZMM1,%ZMM0,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPS %ZMM1,0x4c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVAPS 0x2c0(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VEXTRACTF32X4 $0x3,%ZMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x200(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x200(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x140(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x200(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x140(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x200(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x140(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPS 0x2c0(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VEXTRACTF32X4 $0x2,%ZMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x200(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x200(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x200(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x200(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0x140(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	3	0.33	vect (25.0%)
VMOVAPS %YMM0,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPS 0x2c0(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x200(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x200(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x200(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x200(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x200(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPS 0x2c0(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x2c0(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x2c0(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x2c0(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1980(%RSP),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV 0x3f8(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVAPS 0xc0(%RSP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM2,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0x200(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	3	0.33	vect (25.0%)
VINSERTF64X4 $0x1,0x140(%RSP),%ZMM0,%ZMM0	2	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (50.0%)
VADDPS %ZMM1,%ZMM0,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
ADD $0x40,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R13,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 6409 <main+0x2b89>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:52-53
Module	attention-clang-gnr512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:52-53.

It is main loop of related source loop which is unrolled by 64 (including vectorization).

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

83% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

60% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

expf@plt: 64 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VINSERTF128: 8 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
VINSERTF64X4: 4 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
VPERMILPD: 16 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
VPSHUFD: 16 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
VZEROUPPER: 16 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53

Vector unaligned load/store instructions

Detected 12 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 4 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
VINSERTF128: 8 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

8 AVX-512 instructions are processing arithmetic or math operations on single precision FP elements in vector mode (sixteen at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 128 FP arithmetical operations:

128: addition or subtraction

The binary loop is loading 3336 bytes (834 single precision FP elements). The binary loop is storing 1728 bytes (432 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	364
nb uops	487
loop length	2621
used x86 registers	4
used mmx registers	0
used xmm registers	3
used ymm registers	1
used zmm registers	6
nb stack references	13

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	81.17 cycles
front end	81.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	18.00	18.00	44.33	44.33	72.00	76.00	1.00	72.00	72.00	72.00	0.00	44.33
cycles	18.00	18.00	44.33	44.33	72.00	76.00	1.00	72.00	72.00	72.00	0.00	44.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	81.17
Dispatch	76.00
Data deps.	1.00
Overall L1	81.17

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	81%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	45%

INT+FP

all	83%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	60%

Vector efficiency ratios

INT

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	32%
load	39%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	32%
load	37%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 81.17 cycles. At this rate:

21% of peak load performance is reached (41.10 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (21.29 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 6409

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVAPS %ZMM1,0x1980(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPS -0xc0(%RBX,%R13,4),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPS -0x80(%RBX,%R13,4),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPS -0x40(%RBX,%R13,4),%ZMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPS (%RBX,%R13,4),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVAPS 0x1940(%RSP),%ZMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VSUBPS %ZMM4,%ZMM0,%ZMM5	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPS %ZMM5,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VSUBPS %ZMM4,%ZMM1,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPS %ZMM0,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VSUBPS %ZMM4,%ZMM2,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPS %ZMM0,0x200(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VSUBPS %ZMM4,%ZMM3,%ZMM0	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPS %ZMM0,0x2c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VEXTRACTF32X4 $0x3,%ZMM5,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x40(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1c0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x40(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1c0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x40(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1c0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPS 0xc0(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VEXTRACTF32X4 $0x2,%ZMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x120(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x40(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x120(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x120(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x40(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x120(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x120(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x40(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x120(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0x1c0(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	3	0.33	vect (25.0%)
VMOVAPS %YMM0,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPS 0xc0(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x120(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x40(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x120(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x120(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x40(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x120(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x120(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x40(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x120(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPS 0xc0(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x120(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0xc0(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x120(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x120(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0xc0(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x120(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x120(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0xc0(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x120(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0x40(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	3	0.33	vect (25.0%)
VINSERTF64X4 $0x1,0x1c0(%RSP),%ZMM0,%ZMM0	2	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (50.0%)
VMOVAPS 0x480(%RSP),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPS %ZMM1,%ZMM0,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPS %ZMM1,0x480(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVAPS 0x140(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VEXTRACTF32X4 $0x3,%ZMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0xc0(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0xc0(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0xc0(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPS 0x140(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VEXTRACTF32X4 $0x2,%ZMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0xc0(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1c0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0xc0(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1c0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0xc0(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1c0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0x40(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	3	0.33	vect (25.0%)
VMOVAPS %YMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPS 0x140(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0xc0(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1c0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0xc0(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1c0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0xc0(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1c0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPS 0x140(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x140(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1c0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x140(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1c0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x140(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1c0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0xc0(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	3	0.33	vect (25.0%)
VINSERTF64X4 $0x1,0x40(%RSP),%ZMM0,%ZMM0	2	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (50.0%)
VMOVAPS 0x500(%RSP),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPS %ZMM1,%ZMM0,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPS %ZMM1,0x500(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVAPS 0x200(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VEXTRACTF32X4 $0x3,%ZMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x140(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x140(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x140(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPS 0x200(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VEXTRACTF32X4 $0x2,%ZMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x140(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x140(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x140(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0xc0(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	3	0.33	vect (25.0%)
VMOVAPS %YMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPS 0x200(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x140(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x140(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x140(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPS 0x200(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x200(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x200(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x200(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x40(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0x140(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	3	0.33	vect (25.0%)
VINSERTF64X4 $0x1,0xc0(%RSP),%ZMM0,%ZMM0	2	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (50.0%)
VMOVAPS 0x4c0(%RSP),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VADDPS %ZMM1,%ZMM0,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
VMOVAPS %ZMM1,0x4c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVAPS 0x2c0(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VEXTRACTF32X4 $0x3,%ZMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x200(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x200(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x140(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x200(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x140(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x200(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x140(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPS 0x2c0(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VEXTRACTF32X4 $0x2,%ZMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x200(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x200(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x200(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x200(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0x140(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	3	0.33	vect (25.0%)
VMOVAPS %YMM0,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPS 0x2c0(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x200(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x200(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x200(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x200(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x200(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPS 0x2c0(%RSP),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x2c0(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x2c0(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xc0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x2c0(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1980(%RSP),%ZMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
MOV 0x3f8(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVAPS 0xc0(%RSP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM2,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0x200(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	3	0.33	vect (25.0%)
VINSERTF64X4 $0x1,0x140(%RSP),%ZMM0,%ZMM0	2	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	vect (50.0%)
VADDPS %ZMM1,%ZMM0,%ZMM1	1	0.50	0	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (100.0%)
ADD $0x40,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R13,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 6409 <main+0x2b89>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

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Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code