OV - attention-clang-gnr512 - Loop 41 - attention-clang-gnr512

	Loop Id: 41	Module: attention-clang-gnr512	Source: random.tcc:330-336 [...]	Coverage: 0.13%

0x42e0 MOV	%RCX,%RDX

0x42e3 SHR	$0x1e,%RDX

0x42e7 XOR	%RCX,%RDX

0x42ea IMUL	$0x6c078965,%RDX,%RCX

0x42f1 LEA	-0x6(%RAX,%RCX,1),%RCX

0x42f6 MOV	%ECX,%EDX

0x42f8 MOV	%RDX,0x588(%RSP,%RAX,8)    [1]

0x4300 MOV	%ECX,%EDX

0x4302 SHR	$0x1e,%EDX

0x4305 XOR	%RCX,%RDX

0x4308 IMUL	$0x6c078965,%RDX,%RCX

0x430f LEA	-0x5(%RAX,%RCX,1),%RCX

0x4314 MOV	%ECX,%EDX

0x4316 MOV	%RDX,0x590(%RSP,%RAX,8)    [1]

0x431e MOV	%ECX,%EDX

0x4320 SHR	$0x1e,%EDX

0x4323 XOR	%RCX,%RDX

0x4326 IMUL	$0x6c078965,%RDX,%RCX

0x432d LEA	-0x4(%RAX,%RCX,1),%RCX

0x4332 MOV	%ECX,%EDX

0x4334 MOV	%RDX,0x598(%RSP,%RAX,8)    [1]

0x433c MOV	%ECX,%EDX

0x433e SHR	$0x1e,%EDX

0x4341 XOR	%RCX,%RDX

0x4344 IMUL	$0x6c078965,%RDX,%RCX

0x434b LEA	-0x3(%RAX,%RCX,1),%RCX

0x4350 MOV	%ECX,%EDX

0x4352 MOV	%RDX,0x5a0(%RSP,%RAX,8)    [1]

0x435a MOV	%ECX,%EDX

0x435c SHR	$0x1e,%EDX

0x435f XOR	%RCX,%RDX

0x4362 IMUL	$0x6c078965,%RDX,%RCX

0x4369 LEA	-0x2(%RAX,%RCX,1),%RCX

0x436e MOV	%ECX,%EDX

0x4370 MOV	%RDX,0x5a8(%RSP,%RAX,8)    [1]

0x4378 MOV	%ECX,%EDX

0x437a SHR	$0x1e,%EDX

0x437d XOR	%RCX,%RDX

0x4380 IMUL	$0x6c078965,%RDX,%RCX

0x4387 LEA	-0x1(%RAX,%RCX,1),%RCX

0x438c MOV	%ECX,%EDX

0x438e MOV	%RDX,0x5b0(%RSP,%RAX,8)    [1]

0x4396 MOV	%ECX,%EDX

0x4398 SHR	$0x1e,%EDX

0x439b XOR	%ECX,%EDX

0x439d IMUL	$0x6c078965,%EDX,%ECX

0x43a3 ADD	%EAX,%ECX

0x43a5 MOV	%RCX,0x5b8(%RSP,%RAX,8)    [1]

0x43ad ADD	$0x7,%RAX

0x43b1 CMP	$0x276,%RAX

0x43b7 JNE	42e0

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.h: 140 - 140

--------------------------------------------------------------------------------

140: 	    __res %= __m;

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc: 330 - 336

--------------------------------------------------------------------------------

330:       for (size_t __i = 1; __i < state_size; ++__i)

331: 	{

332: 	  _UIntType __x = _M_x[__i - 1];

333: 	  __x ^= __x >> (__w - 2);

334: 	  __x *= __f;

335: 	  __x += __detail::__mod<_UIntType, __n>(__i);

336: 	  _M_x[__i] = __detail::__mod<_UIntType,

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	16.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.75
Bottlenecks	P1,
Function	main
Source	random.h:140-140,random.tcc:330-336
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.60
CQA cycles if no scalar integer	14.60
CQA cycles if FP arith vectorized	14.60
CQA cycles if fully vectorized	0.91
Front-end cycles	8.33
P0 cycles	4.00
P1 cycles	14.60
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	3.50
P5 cycles	4.00
P6 cycles	4.00
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	4.00
P11 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	51.00
Nb uops	50.00
Nb loads	0.00
Nb stores	7.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.84
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	56.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	9.01
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.10

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	16.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.75
Bottlenecks	P1,
Function	main
Source	random.h:140-140,random.tcc:330-336
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.60
CQA cycles if no scalar integer	14.60
CQA cycles if FP arith vectorized	14.60
CQA cycles if fully vectorized	0.91
Front-end cycles	8.33
P0 cycles	4.00
P1 cycles	14.60
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	3.50
P5 cycles	4.00
P6 cycles	4.00
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	3.50
P10 cycles	4.00
P11 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	51.00
Nb uops	50.00
Nb loads	0.00
Nb stores	7.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.84
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	56.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	9.01
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.10

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	random.tcc:330-336
Module	attention-clang-gnr512

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.h:140
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:330-336

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 14.60 to 0.91 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 56 bytes.

General properties

nb instructions	51
nb uops	50
loop length	221
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.33 cycles
front end	8.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.00	13.00	0.00	0.00	3.50	4.00	4.00	3.50	3.50	3.50	4.00	0.00
cycles	4.00	14.60	0.00	0.00	3.50	4.00	4.00	3.50	3.50	3.50	4.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	8.33
Dispatch	14.60
Data deps.	0.00
Overall L1	14.60

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.60 cycles. At this rate:

2% of peak store performance is reached (3.84 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42e0

Instruction	Nb FU	P0	P1	P4	P5	P6	P7	P8	P9	P10	Latency	Recip. throughput	Vectorization
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x1e,%RDX	1	0.50	0	0	0	0.50	0	0	0	0	0-2	0.50	scal (12.5%)
XOR %RCX,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
LEA -0x6(%RAX,%RCX,1),%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x588(%RSP,%RAX,8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x1e,%EDX	1	0.50	0	0	0	0.50	0	0	0	0	0-2	0.50	scal (6.3%)
XOR %RCX,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
LEA -0x5(%RAX,%RCX,1),%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x590(%RSP,%RAX,8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x1e,%EDX	1	0.50	0	0	0	0.50	0	0	0	0	0-2	0.50	scal (6.3%)
XOR %RCX,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
LEA -0x4(%RAX,%RCX,1),%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x598(%RSP,%RAX,8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x1e,%EDX	1	0.50	0	0	0	0.50	0	0	0	0	0-2	0.50	scal (6.3%)
XOR %RCX,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
LEA -0x3(%RAX,%RCX,1),%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x5a0(%RSP,%RAX,8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x1e,%EDX	1	0.50	0	0	0	0.50	0	0	0	0	0-2	0.50	scal (6.3%)
XOR %RCX,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
LEA -0x2(%RAX,%RCX,1),%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x5a8(%RSP,%RAX,8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x1e,%EDX	1	0.50	0	0	0	0.50	0	0	0	0	0-2	0.50	scal (6.3%)
XOR %RCX,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
LEA -0x1(%RAX,%RCX,1),%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x5b0(%RSP,%RAX,8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x1e,%EDX	1	0.50	0	0	0	0.50	0	0	0	0	0-2	0.50	scal (6.3%)
XOR %ECX,%EDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	scal (6.3%)
IMUL $0x6c078965,%EDX,%ECX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
ADD %EAX,%ECX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1	0.20	N/A
MOV %RCX,0x5b8(%RSP,%RAX,8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
ADD $0x7,%RAX	1	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x276,%RAX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1	0.20	N/A
JNE 42e0 <main+0xa60>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	random.tcc:330-336
Module	attention-clang-gnr512

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.h:140
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:330-336

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 56 bytes.

General properties

nb instructions	51
nb uops	50
loop length	221
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	8.33 cycles
front end	8.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.00	13.00	0.00	0.00	3.50	4.00	4.00	3.50	3.50	3.50	4.00	0.00
cycles	4.00	14.60	0.00	0.00	3.50	4.00	4.00	3.50	3.50	3.50	4.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	8.33
Dispatch	14.60
Data deps.	0.00
Overall L1	14.60

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.60 cycles. At this rate:

2% of peak store performance is reached (3.84 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 42e0

Instruction	Nb FU	P0	P1	P4	P5	P6	P7	P8	P9	P10	Latency	Recip. throughput	Vectorization
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x1e,%RDX	1	0.50	0	0	0	0.50	0	0	0	0	0-2	0.50	scal (12.5%)
XOR %RCX,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
LEA -0x6(%RAX,%RCX,1),%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x588(%RSP,%RAX,8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x1e,%EDX	1	0.50	0	0	0	0.50	0	0	0	0	0-2	0.50	scal (6.3%)
XOR %RCX,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
LEA -0x5(%RAX,%RCX,1),%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x590(%RSP,%RAX,8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x1e,%EDX	1	0.50	0	0	0	0.50	0	0	0	0	0-2	0.50	scal (6.3%)
XOR %RCX,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
LEA -0x4(%RAX,%RCX,1),%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x598(%RSP,%RAX,8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x1e,%EDX	1	0.50	0	0	0	0.50	0	0	0	0	0-2	0.50	scal (6.3%)
XOR %RCX,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
LEA -0x3(%RAX,%RCX,1),%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x5a0(%RSP,%RAX,8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x1e,%EDX	1	0.50	0	0	0	0.50	0	0	0	0	0-2	0.50	scal (6.3%)
XOR %RCX,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
LEA -0x2(%RAX,%RCX,1),%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x5a8(%RSP,%RAX,8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x1e,%EDX	1	0.50	0	0	0	0.50	0	0	0	0	0-2	0.50	scal (6.3%)
XOR %RCX,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
LEA -0x1(%RAX,%RCX,1),%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x5b0(%RSP,%RAX,8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x1e,%EDX	1	0.50	0	0	0	0.50	0	0	0	0	0-2	0.50	scal (6.3%)
XOR %ECX,%EDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	scal (6.3%)
IMUL $0x6c078965,%EDX,%ECX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
ADD %EAX,%ECX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1	0.20	N/A
MOV %RCX,0x5b8(%RSP,%RAX,8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
ADD $0x7,%RAX	1	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x276,%RAX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1	0.20	N/A
JNE 42e0 <main+0xa60>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code