OV - attention-gnr-256 - Loop 47

	Loop Id: 47	Module: attention-gnr-256	Source: attention_v2.cpp:164-167 [...]	Coverage: 0.32%

0x4044a0 CMP	$0x270,%RDX

0x4044a7 JB	404720

0x4044ad XOR	%EAX,%EAX

0x4044af VPBROADCASTQ	0xace8(%RIP),%YMM4

0x4044b8 VPBROADCASTQ	0xace7(%RIP),%YMM5

0x4044c1 VPBROADCASTQ	0xace6(%RIP),%YMM6

0x4044ca VPBROADCASTQ	0xace5(%RIP),%YMM7

0x4044d3 NOPW	%CS:(%RAX,%RAX,1)

  (48) 0x4044e0 VPBROADCASTQ	%R10,%YMM1

  (48) 0x4044e6 MOV	0x3b8(%RSP,%RAX,1),%R10

  (48) 0x4044ee VMOVDQU	0x3a0(%RSP,%RAX,1),%YMM0

  (48) 0x4044f7 VPSRLQ	$0x1,%YMM0,%YMM2

  (48) 0x4044fc VPAND	%YMM4,%YMM2,%YMM2

  (48) 0x404500 VPBLENDD	$-0x40,%YMM1,%YMM0,%YMM1

  (48) 0x404506 VPSRLQ	$0x1,%YMM1,%YMM1

  (48) 0x40450b VPERMQ	$-0x6d,%YMM1,%YMM1

  (48) 0x404511 VPAND	%YMM5,%YMM1,%YMM1

  (48) 0x404515 VPTERNLOGQ	$0x56,0x1000(%RSP,%RAX,1),%YMM2,%YMM1

  (48) 0x404521 VPTESTMQ	%YMM6,%YMM0,%K1

  (48) 0x404527 VPXORQ	%YMM7,%YMM1,%YMM1{%K1}

  (48) 0x40452d VMOVDQU	%YMM1,0x398(%RSP,%RAX,1)

  (48) 0x404536 ADD	$0x20,%RAX

  (48) 0x40453a CMP	$0x700,%RAX

  (48) 0x404540 JNE	4044e0

0x404542 MOV	0xaa8(%RSP),%RAX

0x40454a VMOVDQU	0xaa0(%RSP),%XMM1

0x404553 VPSRLQ	$0x1,%XMM1,%XMM2

0x404558 VEXTRACTI128	$0x1,%YMM0,%XMM0

0x40455e VPUNPCKHQDQ	0xaa0(%RSP){1to2},%XMM0,%XMM0

0x404569 VPANDQ	0xac2d(%RIP){1to2},%XMM2,%XMM2

0x404573 VPSRLQ	$0x1,%XMM0,%XMM0

0x404578 VPANDQ	0xac26(%RIP){1to2},%XMM0,%XMM0

0x404582 VPTERNLOGQ	$0x56,0x1700(%RSP),%XMM2,%XMM0

0x40458e VPTESTMQ	0xac18(%RIP){1to0},%XMM1,%K1

0x404598 VPXORQ	0xac16(%RIP){1to2},%XMM0,%XMM0{%K1}

0x4045a2 VMOVDQU	%XMM0,0xa98(%RSP)

0x4045ab MOV	0xab0(%RSP),%ECX

0x4045b2 MOV	%ECX,%EDX

0x4045b4 SHR	$0x1,%EDX

0x4045b6 AND	$0x3fffffff,%EDX

0x4045bc SHR	$0x1,%RAX

0x4045bf AND	%R8,%RAX

0x4045c2 ADD	%RDX,%RAX

0x4045c5 XOR	0x1710(%RSP),%RAX

0x4045cd AND	$0x1,%ECX

0x4045d0 NEG	%ECX

0x4045d2 AND	%EDI,%ECX

0x4045d4 XOR	%RAX,%RCX

0x4045d7 MOV	%RCX,0xaa8(%RSP)

0x4045df MOV	$-0xc,%RAX

0x4045e6 NOPW	%CS:(%RAX,%RAX,1)

  (49) 0x4045f0 VMOVDQU	0xb18(%RSP,%RAX,8),%YMM0

  (49) 0x4045f9 VMOVDQU	0xb38(%RSP,%RAX,8),%YMM1

  (49) 0x404602 VPSRLQ	$0x1,%YMM0,%YMM2

  (49) 0x404607 VPAND	%YMM4,%YMM2,%YMM2

  (49) 0x40460b VPSRLQ	$0x1,0xb10(%RSP,%RAX,8),%YMM3

  (49) 0x404617 VPAND	%YMM5,%YMM3,%YMM3

  (49) 0x40461b VPTERNLOGQ	$0x56,0x3f8(%RSP,%RAX,8),%YMM2,%YMM3

  (49) 0x404627 VMOVDQU	0xb58(%RSP,%RAX,8),%YMM2

  (49) 0x404630 VPTESTMQ	%YMM6,%YMM0,%K1

  (49) 0x404636 VPXORQ	%YMM7,%YMM3,%YMM3{%K1}

  (49) 0x40463c VMOVDQU	%YMM3,0xb10(%RSP,%RAX,8)

  (49) 0x404645 VPSRLQ	$0x1,%YMM1,%YMM0

  (49) 0x40464a VPAND	%YMM4,%YMM0,%YMM0

  (49) 0x40464e VPSRLQ	$0x1,0xb30(%RSP,%RAX,8),%YMM3

  (49) 0x40465a VPAND	%YMM5,%YMM3,%YMM3

  (49) 0x40465e VPTERNLOGQ	$0x56,0x418(%RSP,%RAX,8),%YMM0,%YMM3

  (49) 0x40466a VPTESTMQ	%YMM6,%YMM1,%K1

  (49) 0x404670 VPXORQ	%YMM7,%YMM3,%YMM3{%K1}

  (49) 0x404676 VMOVDQU	%YMM3,0xb30(%RSP,%RAX,8)

  (49) 0x40467f VPSRLQ	$0x1,%YMM2,%YMM0

  (49) 0x404684 VPAND	%YMM4,%YMM0,%YMM0

  (49) 0x404688 VPSRLQ	$0x1,0xb50(%RSP,%RAX,8),%YMM1

  (49) 0x404694 VPAND	%YMM5,%YMM1,%YMM1

  (49) 0x404698 VPTERNLOGQ	$0x56,0x438(%RSP,%RAX,8),%YMM0,%YMM1

  (49) 0x4046a4 VPTESTMQ	%YMM6,%YMM2,%K1

  (49) 0x4046aa VPXORQ	%YMM7,%YMM1,%YMM1{%K1}

  (49) 0x4046b0 VMOVDQU	%YMM1,0xb50(%RSP,%RAX,8)

  (49) 0x4046b9 ADD	$0xc,%RAX

  (49) 0x4046bd CMP	$0x180,%RAX

  (49) 0x4046c3 JB	4045f0

0x4046c9 MOV	0x1710(%RSP),%RCX

0x4046d1 MOV	0x398(%RSP),%RAX

0x4046d9 MOV	%EAX,%EDX

0x4046db SHR	$0x1,%EDX

0x4046dd AND	$0x3fffffff,%EDX

0x4046e3 SHR	$0x1,%RCX

0x4046e6 AND	%R8,%RCX

0x4046e9 ADD	%RDX,%RCX

0x4046ec XOR	0xff8(%RSP),%RCX

0x4046f4 MOV	%EAX,%EDX

0x4046f6 AND	$0x1,%EDX

0x4046f9 NEG	%EDX

0x4046fb AND	%EDI,%EDX

0x4046fd XOR	%RCX,%RDX

0x404700 MOV	%RDX,0x1710(%RSP)

0x404708 MOV	$0x1,%EDX

0x40470d MOV	%RAX,%R10

0x404710 JMP	40472b

0x404720 MOV	0x398(%RSP,%RDX,8),%RAX

0x404728 INC	%RDX

0x40472b MOV	%RAX,%RCX

0x40472e SHR	$0xb,%RCX

0x404732 MOV	%ECX,%ECX

0x404734 XOR	%RAX,%RCX

0x404737 MOV	%ECX,%EAX

0x404739 SAL	$0x7,%EAX

0x40473c AND	$-0x62d3a980,%EAX

0x404741 XOR	%RCX,%RAX

0x404744 MOV	%EAX,%ECX

0x404746 SAL	$0xf,%ECX

0x404749 AND	$-0x103a0000,%ECX

0x40474f XOR	%RAX,%RCX

0x404752 MOV	%RCX,%RAX

0x404755 SHR	$0x12,%RAX

0x404759 XOR	%RCX,%RAX

0x40475c VCVTUSI2SS	%RAX,%XMM8,%XMM0

0x404762 VMULSS	0xa9ee(%RIP),%XMM0,%XMM0

0x40476a VUCOMISS	0xa9da(%RIP),%XMM0

0x404772 JAE	4049f2

0x404778 MOV	0x78(%RSP),%RAX

0x40477d VMOVSS	%XMM0,(%RAX,%R9,4)

0x404783 CMP	$0x270,%RDX

0x40478a JB	404a60

0x404790 XOR	%EAX,%EAX

0x404792 VPBROADCASTQ	0xaa05(%RIP),%YMM4

0x40479b VPBROADCASTQ	0xaa04(%RIP),%YMM5

0x4047a4 VPBROADCASTQ	0xaa03(%RIP),%YMM6

0x4047ad VPBROADCASTQ	0xaa02(%RIP),%YMM7

0x4047b6 NOPW	%CS:(%RAX,%RAX,1)

  (43) 0x4047c0 VPBROADCASTQ	%R10,%YMM1

  (43) 0x4047c6 MOV	0x3b8(%RSP,%RAX,1),%R10

  (43) 0x4047ce VMOVDQU	0x3a0(%RSP,%RAX,1),%YMM0

  (43) 0x4047d7 VPSRLQ	$0x1,%YMM0,%YMM2

  (43) 0x4047dc VPAND	%YMM4,%YMM2,%YMM2

  (43) 0x4047e0 VPBLENDD	$-0x40,%YMM1,%YMM0,%YMM1

  (43) 0x4047e6 VPSRLQ	$0x1,%YMM1,%YMM1

  (43) 0x4047eb VPERMQ	$-0x6d,%YMM1,%YMM1

  (43) 0x4047f1 VPAND	%YMM5,%YMM1,%YMM1

  (43) 0x4047f5 VPTERNLOGQ	$0x56,0x1000(%RSP,%RAX,1),%YMM2,%YMM1

  (43) 0x404801 VPTESTMQ	%YMM6,%YMM0,%K1

  (43) 0x404807 VPXORQ	%YMM7,%YMM1,%YMM1{%K1}

  (43) 0x40480d VMOVDQU	%YMM1,0x398(%RSP,%RAX,1)

  (43) 0x404816 ADD	$0x20,%RAX

  (43) 0x40481a CMP	$0x700,%RAX

  (43) 0x404820 JNE	4047c0

0x404822 MOV	0xaa8(%RSP),%RAX

0x40482a VMOVDQU	0xaa0(%RSP),%XMM1

0x404833 VPSRLQ	$0x1,%XMM1,%XMM2

0x404838 VEXTRACTI128	$0x1,%YMM0,%XMM0

0x40483e VPUNPCKHQDQ	0xaa0(%RSP){1to2},%XMM0,%XMM0

0x404849 VPANDQ	0xa94d(%RIP){1to2},%XMM2,%XMM2

0x404853 VPSRLQ	$0x1,%XMM0,%XMM0

0x404858 VPANDQ	0xa946(%RIP){1to2},%XMM0,%XMM0

0x404862 VPTERNLOGQ	$0x56,0x1700(%RSP),%XMM2,%XMM0

0x40486e VPTESTMQ	0xa938(%RIP){1to0},%XMM1,%K1

0x404878 VPXORQ	0xa936(%RIP){1to2},%XMM0,%XMM0{%K1}

0x404882 VMOVDQU	%XMM0,0xa98(%RSP)

0x40488b MOV	0xab0(%RSP),%ECX

0x404892 MOV	%ECX,%EDX

0x404894 SHR	$0x1,%EDX

0x404896 AND	$0x3fffffff,%EDX

0x40489c SHR	$0x1,%RAX

0x40489f AND	%R8,%RAX

0x4048a2 ADD	%RDX,%RAX

0x4048a5 XOR	0x1710(%RSP),%RAX

0x4048ad AND	$0x1,%ECX

0x4048b0 NEG	%ECX

0x4048b2 AND	%EDI,%ECX

0x4048b4 XOR	%RAX,%RCX

0x4048b7 MOV	%RCX,0xaa8(%RSP)

0x4048bf MOV	$-0xc,%RAX

0x4048c6 NOPW	%CS:(%RAX,%RAX,1)

  (44) 0x4048d0 VMOVDQU	0xb18(%RSP,%RAX,8),%YMM0

  (44) 0x4048d9 VMOVDQU	0xb38(%RSP,%RAX,8),%YMM1

  (44) 0x4048e2 VPSRLQ	$0x1,%YMM0,%YMM2

  (44) 0x4048e7 VPAND	%YMM4,%YMM2,%YMM2

  (44) 0x4048eb VPSRLQ	$0x1,0xb10(%RSP,%RAX,8),%YMM3

  (44) 0x4048f7 VPAND	%YMM5,%YMM3,%YMM3

  (44) 0x4048fb VPTERNLOGQ	$0x56,0x3f8(%RSP,%RAX,8),%YMM2,%YMM3

  (44) 0x404907 VMOVDQU	0xb58(%RSP,%RAX,8),%YMM2

  (44) 0x404910 VPTESTMQ	%YMM6,%YMM0,%K1

  (44) 0x404916 VPXORQ	%YMM7,%YMM3,%YMM3{%K1}

  (44) 0x40491c VMOVDQU	%YMM3,0xb10(%RSP,%RAX,8)

  (44) 0x404925 VPSRLQ	$0x1,%YMM1,%YMM0

  (44) 0x40492a VPAND	%YMM4,%YMM0,%YMM0

  (44) 0x40492e VPSRLQ	$0x1,0xb30(%RSP,%RAX,8),%YMM3

  (44) 0x40493a VPAND	%YMM5,%YMM3,%YMM3

  (44) 0x40493e VPTERNLOGQ	$0x56,0x418(%RSP,%RAX,8),%YMM0,%YMM3

  (44) 0x40494a VPTESTMQ	%YMM6,%YMM1,%K1

  (44) 0x404950 VPXORQ	%YMM7,%YMM3,%YMM3{%K1}

  (44) 0x404956 VMOVDQU	%YMM3,0xb30(%RSP,%RAX,8)

  (44) 0x40495f VPSRLQ	$0x1,%YMM2,%YMM0

  (44) 0x404964 VPAND	%YMM4,%YMM0,%YMM0

  (44) 0x404968 VPSRLQ	$0x1,0xb50(%RSP,%RAX,8),%YMM1

  (44) 0x404974 VPAND	%YMM5,%YMM1,%YMM1

  (44) 0x404978 VPTERNLOGQ	$0x56,0x438(%RSP,%RAX,8),%YMM0,%YMM1

  (44) 0x404984 VPTESTMQ	%YMM6,%YMM2,%K1

  (44) 0x40498a VPXORQ	%YMM7,%YMM1,%YMM1{%K1}

  (44) 0x404990 VMOVDQU	%YMM1,0xb50(%RSP,%RAX,8)

  (44) 0x404999 ADD	$0xc,%RAX

  (44) 0x40499d CMP	$0x180,%RAX

  (44) 0x4049a3 JB	4048d0

0x4049a9 MOV	0x1710(%RSP),%RCX

0x4049b1 MOV	0x398(%RSP),%RAX

0x4049b9 MOV	%EAX,%EDX

0x4049bb SHR	$0x1,%EDX

0x4049bd AND	$0x3fffffff,%EDX

0x4049c3 SHR	$0x1,%RCX

0x4049c6 AND	%R8,%RCX

0x4049c9 ADD	%RDX,%RCX

0x4049cc XOR	0xff8(%RSP),%RCX

0x4049d4 MOV	%EAX,%EDX

0x4049d6 AND	$0x1,%EDX

0x4049d9 NEG	%EDX

0x4049db AND	%EDI,%EDX

0x4049dd XOR	%RCX,%RDX

0x4049e0 MOV	%RDX,0x1710(%RSP)

0x4049e8 MOV	$0x1,%EDX

0x4049ed MOV	%RAX,%R10

0x4049f0 JMP	404a6b

0x4049f2 VXORPS	%XMM1,%XMM1,%XMM1

0x4049f6 VMOVSS	0xa74e(%RIP),%XMM0

0x4049fe MOV	%R9,0x30(%RSP)

0x404a03 MOV	%R10,0x28(%RSP)

0x404a08 MOV	%RDX,0x18(%RSP)

0x404a0d VZEROUPPER

0x404a10 CALL	4088d0 <nextafterf>

0x404a15 MOV	0x18(%RSP),%RDX

0x404a1a MOV	0x28(%RSP),%R10

0x404a1f MOV	0x30(%RSP),%R9

0x404a24 MOV	$0x7fffffffc0000000,%R8

0x404a2e MOV	$-0x66f74f21,%EDI

0x404a33 MOV	0xf8(%RSP),%RSI

0x404a3b MOV	0x78(%RSP),%RAX

0x404a40 VMOVSS	%XMM0,(%RAX,%R9,4)

0x404a46 CMP	$0x270,%RDX

0x404a4d JAE	404790

0x404a53 NOPW	%CS:(%RAX,%RAX,1)

0x404a60 MOV	0x398(%RSP,%RDX,8),%RAX

0x404a68 INC	%RDX

0x404a6b MOV	%RAX,%RCX

0x404a6e SHR	$0xb,%RCX

0x404a72 MOV	%ECX,%ECX

0x404a74 XOR	%RAX,%RCX

0x404a77 MOV	%ECX,%EAX

0x404a79 SAL	$0x7,%EAX

0x404a7c AND	$-0x62d3a980,%EAX

0x404a81 XOR	%RCX,%RAX

0x404a84 MOV	%EAX,%ECX

0x404a86 SAL	$0xf,%ECX

0x404a89 AND	$-0x103a0000,%ECX

0x404a8f XOR	%RAX,%RCX

0x404a92 MOV	%RCX,%RAX

0x404a95 SHR	$0x12,%RAX

0x404a99 XOR	%RCX,%RAX

0x404a9c VCVTUSI2SS	%RAX,%XMM8,%XMM0

0x404aa2 VMULSS	0xa6ae(%RIP),%XMM0,%XMM0

0x404aaa VUCOMISS	0xa69a(%RIP),%XMM0

0x404ab2 JAE	404d32

0x404ab8 MOV	0x70(%RSP),%RAX

0x404abd VMOVSS	%XMM0,(%RAX,%R9,4)

0x404ac3 CMP	$0x270,%RDX

0x404aca JB	404da0

0x404ad0 XOR	%EAX,%EAX

0x404ad2 VPBROADCASTQ	0xa6c5(%RIP),%YMM4

0x404adb VPBROADCASTQ	0xa6c4(%RIP),%YMM5

0x404ae4 VPBROADCASTQ	0xa6c3(%RIP),%YMM6

0x404aed VPBROADCASTQ	0xa6c2(%RIP),%YMM7

0x404af6 NOPW	%CS:(%RAX,%RAX,1)

  (45) 0x404b00 VPBROADCASTQ	%R10,%YMM1

  (45) 0x404b06 MOV	0x3b8(%RSP,%RAX,1),%R10

  (45) 0x404b0e VMOVDQU	0x3a0(%RSP,%RAX,1),%YMM0

  (45) 0x404b17 VPSRLQ	$0x1,%YMM0,%YMM2

  (45) 0x404b1c VPAND	%YMM4,%YMM2,%YMM2

  (45) 0x404b20 VPBLENDD	$-0x40,%YMM1,%YMM0,%YMM1

  (45) 0x404b26 VPSRLQ	$0x1,%YMM1,%YMM1

  (45) 0x404b2b VPERMQ	$-0x6d,%YMM1,%YMM1

  (45) 0x404b31 VPAND	%YMM5,%YMM1,%YMM1

  (45) 0x404b35 VPTERNLOGQ	$0x56,0x1000(%RSP,%RAX,1),%YMM2,%YMM1

  (45) 0x404b41 VPTESTMQ	%YMM6,%YMM0,%K1

  (45) 0x404b47 VPXORQ	%YMM7,%YMM1,%YMM1{%K1}

  (45) 0x404b4d VMOVDQU	%YMM1,0x398(%RSP,%RAX,1)

  (45) 0x404b56 ADD	$0x20,%RAX

  (45) 0x404b5a CMP	$0x700,%RAX

  (45) 0x404b60 JNE	404b00

0x404b62 MOV	0xaa8(%RSP),%RAX

0x404b6a VMOVDQU	0xaa0(%RSP),%XMM1

0x404b73 VPSRLQ	$0x1,%XMM1,%XMM2

0x404b78 VEXTRACTI128	$0x1,%YMM0,%XMM0

0x404b7e VPUNPCKHQDQ	0xaa0(%RSP){1to2},%XMM0,%XMM0

0x404b89 VPANDQ	0xa60d(%RIP){1to2},%XMM2,%XMM2

0x404b93 VPSRLQ	$0x1,%XMM0,%XMM0

0x404b98 VPANDQ	0xa606(%RIP){1to2},%XMM0,%XMM0

0x404ba2 VPTERNLOGQ	$0x56,0x1700(%RSP),%XMM2,%XMM0

0x404bae VPTESTMQ	0xa5f8(%RIP){1to0},%XMM1,%K1

0x404bb8 VPXORQ	0xa5f6(%RIP){1to2},%XMM0,%XMM0{%K1}

0x404bc2 VMOVDQU	%XMM0,0xa98(%RSP)

0x404bcb MOV	0xab0(%RSP),%ECX

0x404bd2 MOV	%ECX,%EDX

0x404bd4 SHR	$0x1,%EDX

0x404bd6 AND	$0x3fffffff,%EDX

0x404bdc SHR	$0x1,%RAX

0x404bdf AND	%R8,%RAX

0x404be2 ADD	%RDX,%RAX

0x404be5 XOR	0x1710(%RSP),%RAX

0x404bed AND	$0x1,%ECX

0x404bf0 NEG	%ECX

0x404bf2 AND	%EDI,%ECX

0x404bf4 XOR	%RAX,%RCX

0x404bf7 MOV	%RCX,0xaa8(%RSP)

0x404bff MOV	$-0xc,%RAX

0x404c06 NOPW	%CS:(%RAX,%RAX,1)

  (46) 0x404c10 VMOVDQU	0xb18(%RSP,%RAX,8),%YMM0

  (46) 0x404c19 VMOVDQU	0xb38(%RSP,%RAX,8),%YMM1

  (46) 0x404c22 VPSRLQ	$0x1,%YMM0,%YMM2

  (46) 0x404c27 VPAND	%YMM4,%YMM2,%YMM2

  (46) 0x404c2b VPSRLQ	$0x1,0xb10(%RSP,%RAX,8),%YMM3

  (46) 0x404c37 VPAND	%YMM5,%YMM3,%YMM3

  (46) 0x404c3b VPTERNLOGQ	$0x56,0x3f8(%RSP,%RAX,8),%YMM2,%YMM3

  (46) 0x404c47 VMOVDQU	0xb58(%RSP,%RAX,8),%YMM2

  (46) 0x404c50 VPTESTMQ	%YMM6,%YMM0,%K1

  (46) 0x404c56 VPXORQ	%YMM7,%YMM3,%YMM3{%K1}

  (46) 0x404c5c VMOVDQU	%YMM3,0xb10(%RSP,%RAX,8)

  (46) 0x404c65 VPSRLQ	$0x1,%YMM1,%YMM0

  (46) 0x404c6a VPAND	%YMM4,%YMM0,%YMM0

  (46) 0x404c6e VPSRLQ	$0x1,0xb30(%RSP,%RAX,8),%YMM3

  (46) 0x404c7a VPAND	%YMM5,%YMM3,%YMM3

  (46) 0x404c7e VPTERNLOGQ	$0x56,0x418(%RSP,%RAX,8),%YMM0,%YMM3

  (46) 0x404c8a VPTESTMQ	%YMM6,%YMM1,%K1

  (46) 0x404c90 VPXORQ	%YMM7,%YMM3,%YMM3{%K1}

  (46) 0x404c96 VMOVDQU	%YMM3,0xb30(%RSP,%RAX,8)

  (46) 0x404c9f VPSRLQ	$0x1,%YMM2,%YMM0

  (46) 0x404ca4 VPAND	%YMM4,%YMM0,%YMM0

  (46) 0x404ca8 VPSRLQ	$0x1,0xb50(%RSP,%RAX,8),%YMM1

  (46) 0x404cb4 VPAND	%YMM5,%YMM1,%YMM1

  (46) 0x404cb8 VPTERNLOGQ	$0x56,0x438(%RSP,%RAX,8),%YMM0,%YMM1

  (46) 0x404cc4 VPTESTMQ	%YMM6,%YMM2,%K1

  (46) 0x404cca VPXORQ	%YMM7,%YMM1,%YMM1{%K1}

  (46) 0x404cd0 VMOVDQU	%YMM1,0xb50(%RSP,%RAX,8)

  (46) 0x404cd9 ADD	$0xc,%RAX

  (46) 0x404cdd CMP	$0x180,%RAX

  (46) 0x404ce3 JB	404c10

0x404ce9 MOV	0x1710(%RSP),%RCX

0x404cf1 MOV	0x398(%RSP),%RAX

0x404cf9 MOV	%EAX,%EDX

0x404cfb SHR	$0x1,%EDX

0x404cfd AND	$0x3fffffff,%EDX

0x404d03 SHR	$0x1,%RCX

0x404d06 AND	%R8,%RCX

0x404d09 ADD	%RDX,%RCX

0x404d0c XOR	0xff8(%RSP),%RCX

0x404d14 MOV	%EAX,%EDX

0x404d16 AND	$0x1,%EDX

0x404d19 NEG	%EDX

0x404d1b AND	%EDI,%EDX

0x404d1d XOR	%RCX,%RDX

0x404d20 MOV	%RDX,0x1710(%RSP)

0x404d28 MOV	$0x1,%EDX

0x404d2d MOV	%RAX,%R10

0x404d30 JMP	404dab

0x404d32 VXORPS	%XMM1,%XMM1,%XMM1

0x404d36 VMOVSS	0xa40e(%RIP),%XMM0

0x404d3e MOV	%R9,0x30(%RSP)

0x404d43 MOV	%R10,0x28(%RSP)

0x404d48 MOV	%RDX,0x18(%RSP)

0x404d4d VZEROUPPER

0x404d50 CALL	4088d0 <nextafterf>

0x404d55 MOV	0x18(%RSP),%RDX

0x404d5a MOV	0x28(%RSP),%R10

0x404d5f MOV	0x30(%RSP),%R9

0x404d64 MOV	$0x7fffffffc0000000,%R8

0x404d6e MOV	$-0x66f74f21,%EDI

0x404d73 MOV	0xf8(%RSP),%RSI

0x404d7b MOV	0x70(%RSP),%RAX

0x404d80 VMOVSS	%XMM0,(%RAX,%R9,4)

0x404d86 CMP	$0x270,%RDX

0x404d8d JAE	404ad0

0x404d93 NOPW	%CS:(%RAX,%RAX,1)

0x404da0 MOV	0x398(%RSP,%RDX,8),%RAX

0x404da8 INC	%RDX

0x404dab MOV	%RAX,%RCX

0x404dae SHR	$0xb,%RCX

0x404db2 MOV	%ECX,%ECX

0x404db4 XOR	%RAX,%RCX

0x404db7 MOV	%ECX,%EAX

0x404db9 SAL	$0x7,%EAX

0x404dbc AND	$-0x62d3a980,%EAX

0x404dc1 XOR	%RCX,%RAX

0x404dc4 MOV	%EAX,%ECX

0x404dc6 SAL	$0xf,%ECX

0x404dc9 AND	$-0x103a0000,%ECX

0x404dcf XOR	%RAX,%RCX

0x404dd2 MOV	%RCX,%RAX

0x404dd5 SHR	$0x12,%RAX

0x404dd9 XOR	%RCX,%RAX

0x404ddc VCVTUSI2SS	%RAX,%XMM8,%XMM0

0x404de2 VMULSS	0xa36e(%RIP),%XMM0,%XMM0

0x404dea VUCOMISS	0xa35a(%RIP),%XMM0

0x404df2 JAE	404e11

0x404df4 MOV	0x68(%RSP),%RAX

0x404df9 VMOVSS	%XMM0,(%RAX,%R9,4)

0x404dff LEA	0x1(%R9),%RAX

0x404e03 CMP	%RSI,%R9

0x404e06 MOV	%RAX,%R9

0x404e09 JNE	4044a0

0x404e11 VXORPS	%XMM1,%XMM1,%XMM1

0x404e15 VMOVSS	0xa32f(%RIP),%XMM0

0x404e1d MOV	%R9,0x30(%RSP)

0x404e22 MOV	%R10,0x28(%RSP)

0x404e27 MOV	%RDX,0x18(%RSP)

0x404e2c VZEROUPPER

0x404e2f CALL	4088d0 <nextafterf>

0x404e34 MOV	0x18(%RSP),%RDX

0x404e39 MOV	0x28(%RSP),%R10

0x404e3e MOV	0x30(%RSP),%R9

0x404e43 MOV	$0x7fffffffc0000000,%R8

0x404e4d MOV	$-0x66f74f21,%EDI

0x404e52 MOV	0xf8(%RSP),%RSI

0x404e5a JMP	404df4

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath: 1661 - 1661

--------------------------------------------------------------------------------

1661:   { return __builtin_nextafterf(__x, __y); }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc: 401 - 3370

--------------------------------------------------------------------------------

401:       for (size_t __k = 0; __k < (__n - __m); ++__k)

402:         {

403: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

404: 			   | (_M_x[__k + 1] & __lower_mask));

405: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

406: 		       ^ ((__y & 0x01) ? __a : 0));

407:         }

408:

409:       for (size_t __k = (__n - __m); __k < (__n - 1); ++__k)

410: 	{

411: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

412: 			   | (_M_x[__k + 1] & __lower_mask));

413: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

414: 		       ^ ((__y & 0x01) ? __a : 0));

415: 	}

416:

417:       _UIntType __y = ((_M_x[__n - 1] & __upper_mask)

418: 		       | (_M_x[0] & __lower_mask));

419:       _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1)

420: 		       ^ ((__y & 0x01) ? __a : 0));

[...]

455:       if (_M_p >= state_size)

456: 	_M_gen_rand();

457:

458:       // Calculate o(x(i)).

459:       result_type __z = _M_x[_M_p++];

460:       __z ^= (__z >> __u) & __d;

461:       __z ^= (__z << __s) & __b;

462:       __z ^= (__z << __t) & __c;

463:       __z ^= (__z >> __l);

[...]

3366: 	  __sum += _RealType(__urng() - __urng.min()) * __tmp;

3367: 	  __tmp *= __r;

3368: 	}

3369:       __ret = __sum / __tmp;

3370:       if (__builtin_expect(__ret >= _RealType(1), 0))

/home/eoseret/llm-attention/attention_v2.cpp: 164 - 167

--------------------------------------------------------------------------------

164:       for (size_t i = 0; i < elemsW; ++i) {

165:          h_WQ[i] = dist(rng);

166:          h_WK[i] = dist(rng);

167:          h_WV[i] = dist(rng);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.94
CQA speedup if FP arith vectorized	2.13
CQA speedup if fully vectorized	10.25
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.59
Bottlenecks	micro-operation queue,
Function	main
Source	cmath:1661-1661,random.tcc:404-406,random.tcc:417-420,random.tcc:455-455,random.tcc:459-463,random.tcc:3366-3366,random.tcc:3369-3370,attention_v2.cpp:164-167
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	50.50
CQA cycles if no scalar integer	17.17
CQA cycles if FP arith vectorized	23.72
CQA cycles if fully vectorized	4.92
Front-end cycles	50.50
P0 cycles	31.83
P1 cycles	31.77
P2 cycles	26.67
P3 cycles	26.67
P4 cycles	13.00
P5 cycles	31.80
P6 cycles	31.80
P7 cycles	13.00
P8 cycles	13.00
P9 cycles	13.00
P10 cycles	31.80
P11 cycles	26.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	282.00
Nb uops	303.00
Nb loads	80.00
Nb stores	23.00
Nb stack references	15.00
FLOP/cycle	0.06
Nb FLOP add-sub	0.00
Nb FLOP mul	3.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.40
Bytes prefetched	0.00
Bytes loaded	640.00
Bytes stored	188.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	23.38
Vectorization ratio load	33.33
Vectorization ratio store	13.04
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	27.27
Vector-efficiency ratio all	13.76
Vector-efficiency ratio load	15.28
Vector-efficiency ratio store	12.77
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.38

Metric	Value
CQA speedup if no scalar integer	2.94
CQA speedup if FP arith vectorized	2.13
CQA speedup if fully vectorized	10.25
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.59
Bottlenecks	micro-operation queue,
Function	main
Source	cmath:1661-1661,random.tcc:404-406,random.tcc:417-420,random.tcc:455-455,random.tcc:459-463,random.tcc:3366-3366,random.tcc:3369-3370,attention_v2.cpp:164-167
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	50.50
CQA cycles if no scalar integer	17.17
CQA cycles if FP arith vectorized	23.72
CQA cycles if fully vectorized	4.92
Front-end cycles	50.50
P0 cycles	31.83
P1 cycles	31.77
P2 cycles	26.67
P3 cycles	26.67
P4 cycles	13.00
P5 cycles	31.80
P6 cycles	31.80
P7 cycles	13.00
P8 cycles	13.00
P9 cycles	13.00
P10 cycles	31.80
P11 cycles	26.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	282.00
Nb uops	303.00
Nb loads	80.00
Nb stores	23.00
Nb stack references	15.00
FLOP/cycle	0.06
Nb FLOP add-sub	0.00
Nb FLOP mul	3.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.40
Bytes prefetched	0.00
Bytes loaded	640.00
Bytes stored	188.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	23.38
Vectorization ratio load	33.33
Vectorization ratio store	13.04
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	27.27
Vector-efficiency ratio all	13.76
Vector-efficiency ratio load	15.28
Vector-efficiency ratio store	12.77
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.38

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:164-167
Module	attention-gnr-256

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:401-420,455-463,3366-3370
/home/eoseret/llm-attention/attention_v2.cpp:164-167

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 64 paths individually, rerun with max-paths=64
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 64 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 50.50 to 17.17 cycles (2.94x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

23% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

33% of SSE/AVX loads are used in vector version.
13% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
27% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

nextafterf: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTUSI2SS: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366
VPTERNLOGQ: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:405
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:405
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:405
VPTESTMQ: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:406
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:406
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:406
VUCOMISS: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370
VZEROUPPER: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

3: multiply

The binary loop is loading 640 bytes (160 single precision FP elements). The binary loop is storing 188 bytes (47 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	282
nb uops	303
loop length	1531
used x86 registers	9
used mmx registers	0
used xmm registers	4
used ymm registers	5
used zmm registers	0
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	50.50 cycles
front end	50.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	31.83	31.77	26.67	26.67	13.00	31.80	31.80	13.00	13.00	13.00	31.80	26.67
cycles	31.83	31.77	26.67	26.67	13.00	31.80	31.80	13.00	13.00	13.00	31.80	26.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	50.50
Dispatch	31.83
Overall L1	50.50

Vectorization ratios

INT

all	24%
load	40%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	17%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	23%
load	33%
store	13%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

Vector efficiency ratios

INT

all	14%
load	17%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	9%
load	6%
store	6%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	13%
load	15%
store	12%
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 50.50 cycles. At this rate:

6% of peak load performance is reached (12.67 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.72 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 50.50 to 31.83 cycles (1.59x speedup).

ASM code

In the binary file, the address of the loop is: 4044a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
CMP $0x270,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 404720 <main+0x1300>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ 0xace8(%RIP),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0xace7(%RIP),%YMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0xace6(%RIP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0xace5(%RIP),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xaa8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVDQU 0xaa0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VEXTRACTI128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPUNPCKHQDQ 0xaa0(%RSP){1to2},%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	scal (12.5%)
VPANDQ 0xac2d(%RIP){1to2},%XMM2,%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VPANDQ 0xac26(%RIP){1to2},%XMM0,%XMM0	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPTERNLOGQ $0x56,0x1700(%RSP),%XMM2,%XMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPTESTMQ 0xac18(%RIP){1to0},%XMM1,%K1	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (25.0%)
VPXORQ 0xac16(%RIP){1to2},%XMM0,%XMM0{%K1}	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVDQU %XMM0,0xa98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0xab0(%RSP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $0x3fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x1,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND %R8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR 0x1710(%RSP),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	N/A
AND $0x1,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
NEG %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
AND %EDI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RCX,0xaa8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $-0xc,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x1710(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x398(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $0x3fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x1,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
AND %R8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
XOR 0xff8(%RSP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	scal (12.5%)
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
NEG %EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %EDI,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RDX,0x1710(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JMP 40472b <main+0x130b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV 0x398(%RSP,%RDX,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0xb,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x7,%EAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $-0x62d3a980,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0xf,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
AND $-0x103a0000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x12,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
XOR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VCVTUSI2SS %RAX,%XMM8,%XMM0	3	0.50	0.50	0	0	0	2	0	0	0	0	0	0	8	2	scal (12.5%)
VMULSS 0xa9ee(%RIP),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VUCOMISS 0xa9da(%RIP),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (6.3%)
JAE 4049f2 <main+0x15d2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x78(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP $0x270,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 404a60 <main+0x1640>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ 0xaa05(%RIP),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0xaa04(%RIP),%YMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0xaa03(%RIP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0xaa02(%RIP),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xaa8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVDQU 0xaa0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VEXTRACTI128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPUNPCKHQDQ 0xaa0(%RSP){1to2},%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	scal (12.5%)
VPANDQ 0xa94d(%RIP){1to2},%XMM2,%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VPANDQ 0xa946(%RIP){1to2},%XMM0,%XMM0	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPTERNLOGQ $0x56,0x1700(%RSP),%XMM2,%XMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPTESTMQ 0xa938(%RIP){1to0},%XMM1,%K1	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (25.0%)
VPXORQ 0xa936(%RIP){1to2},%XMM0,%XMM0{%K1}	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVDQU %XMM0,0xa98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0xab0(%RSP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $0x3fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x1,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND %R8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR 0x1710(%RSP),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	N/A
AND $0x1,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
NEG %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
AND %EDI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RCX,0xaa8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $-0xc,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x1710(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x398(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $0x3fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x1,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
AND %R8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
XOR 0xff8(%RSP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	scal (12.5%)
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
NEG %EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %EDI,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RDX,0x1710(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JMP 404a6b <main+0x164b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSS 0xa74e(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %R9,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 4088d0 <nextafterf>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x18(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x7fffffffc0000000,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
MOV $-0x66f74f21,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV 0xf8(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP $0x270,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 404790 <main+0x1370>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x398(%RSP,%RDX,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0xb,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x7,%EAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $-0x62d3a980,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0xf,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
AND $-0x103a0000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x12,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
XOR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VCVTUSI2SS %RAX,%XMM8,%XMM0	3	0.50	0.50	0	0	0	2	0	0	0	0	0	0	8	2	scal (12.5%)
VMULSS 0xa6ae(%RIP),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VUCOMISS 0xa69a(%RIP),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (6.3%)
JAE 404d32 <main+0x1912>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x70(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP $0x270,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 404da0 <main+0x1980>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ 0xa6c5(%RIP),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0xa6c4(%RIP),%YMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0xa6c3(%RIP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0xa6c2(%RIP),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xaa8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVDQU 0xaa0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VEXTRACTI128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPUNPCKHQDQ 0xaa0(%RSP){1to2},%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	scal (12.5%)
VPANDQ 0xa60d(%RIP){1to2},%XMM2,%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VPANDQ 0xa606(%RIP){1to2},%XMM0,%XMM0	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPTERNLOGQ $0x56,0x1700(%RSP),%XMM2,%XMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPTESTMQ 0xa5f8(%RIP){1to0},%XMM1,%K1	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (25.0%)
VPXORQ 0xa5f6(%RIP){1to2},%XMM0,%XMM0{%K1}	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVDQU %XMM0,0xa98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0xab0(%RSP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $0x3fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x1,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND %R8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR 0x1710(%RSP),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	N/A
AND $0x1,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
NEG %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
AND %EDI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RCX,0xaa8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $-0xc,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x1710(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x398(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $0x3fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x1,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
AND %R8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
XOR 0xff8(%RSP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	scal (12.5%)
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
NEG %EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %EDI,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RDX,0x1710(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JMP 404dab <main+0x198b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSS 0xa40e(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %R9,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 4088d0 <nextafterf>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x18(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x7fffffffc0000000,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
MOV $-0x66f74f21,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV 0xf8(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x70(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP $0x270,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 404ad0 <main+0x16b0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x398(%RSP,%RDX,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0xb,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x7,%EAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $-0x62d3a980,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0xf,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
AND $-0x103a0000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x12,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
XOR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VCVTUSI2SS %RAX,%XMM8,%XMM0	3	0.50	0.50	0	0	0	2	0	0	0	0	0	0	8	2	scal (12.5%)
VMULSS 0xa36e(%RIP),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VUCOMISS 0xa35a(%RIP),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (6.3%)
JAE 404e11 <main+0x19f1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x68(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x1(%R9),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RSI,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 4044a0 <main+0x1080>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSS 0xa32f(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %R9,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 4088d0 <nextafterf>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x18(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x7fffffffc0000000,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
MOV $-0x66f74f21,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV 0xf8(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 404df4 <main+0x19d4>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

Function	main
Source file and lines	attention_v2.cpp:164-167
Module	attention-gnr-256

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:401-420,455-463,3366-3370
/home/eoseret/llm-attention/attention_v2.cpp:164-167

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 64 paths individually, rerun with max-paths=64
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

23% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

33% of SSE/AVX loads are used in vector version.
13% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
27% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

CALL instructions

Detected function call instructions.

Details

nextafterf: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTUSI2SS: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366
VPTERNLOGQ: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:405
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:405
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:405
VPTESTMQ: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:406
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:406
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:406
VUCOMISS: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370
VZEROUPPER: 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 3 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

3: multiply

The binary loop is loading 640 bytes (160 single precision FP elements). The binary loop is storing 188 bytes (47 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	282
nb uops	303
loop length	1531
used x86 registers	9
used mmx registers	0
used xmm registers	4
used ymm registers	5
used zmm registers	0
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	50.50 cycles
front end	50.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	31.83	31.77	26.67	26.67	13.00	31.80	31.80	13.00	13.00	13.00	31.80	26.67
cycles	31.83	31.77	26.67	26.67	13.00	31.80	31.80	13.00	13.00	13.00	31.80	26.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	50.50
Dispatch	31.83
Overall L1	50.50

Vectorization ratios

INT

all	24%
load	40%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	17%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	23%
load	33%
store	13%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	27%

Vector efficiency ratios

INT

all	14%
load	17%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	9%
load	6%
store	6%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	13%
load	15%
store	12%
mul	6%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 50.50 cycles. At this rate:

6% of peak load performance is reached (12.67 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.72 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4044a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
CMP $0x270,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 404720 <main+0x1300>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ 0xace8(%RIP),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0xace7(%RIP),%YMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0xace6(%RIP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0xace5(%RIP),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xaa8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVDQU 0xaa0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VEXTRACTI128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPUNPCKHQDQ 0xaa0(%RSP){1to2},%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	scal (12.5%)
VPANDQ 0xac2d(%RIP){1to2},%XMM2,%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VPANDQ 0xac26(%RIP){1to2},%XMM0,%XMM0	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPTERNLOGQ $0x56,0x1700(%RSP),%XMM2,%XMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPTESTMQ 0xac18(%RIP){1to0},%XMM1,%K1	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (25.0%)
VPXORQ 0xac16(%RIP){1to2},%XMM0,%XMM0{%K1}	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVDQU %XMM0,0xa98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0xab0(%RSP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $0x3fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x1,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND %R8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR 0x1710(%RSP),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	N/A
AND $0x1,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
NEG %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
AND %EDI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RCX,0xaa8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $-0xc,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x1710(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x398(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $0x3fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x1,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
AND %R8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
XOR 0xff8(%RSP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	scal (12.5%)
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
NEG %EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %EDI,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RDX,0x1710(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JMP 40472b <main+0x130b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV 0x398(%RSP,%RDX,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0xb,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x7,%EAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $-0x62d3a980,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0xf,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
AND $-0x103a0000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x12,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
XOR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VCVTUSI2SS %RAX,%XMM8,%XMM0	3	0.50	0.50	0	0	0	2	0	0	0	0	0	0	8	2	scal (12.5%)
VMULSS 0xa9ee(%RIP),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VUCOMISS 0xa9da(%RIP),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (6.3%)
JAE 4049f2 <main+0x15d2>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x78(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP $0x270,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 404a60 <main+0x1640>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ 0xaa05(%RIP),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0xaa04(%RIP),%YMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0xaa03(%RIP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0xaa02(%RIP),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xaa8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVDQU 0xaa0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VEXTRACTI128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPUNPCKHQDQ 0xaa0(%RSP){1to2},%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	scal (12.5%)
VPANDQ 0xa94d(%RIP){1to2},%XMM2,%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VPANDQ 0xa946(%RIP){1to2},%XMM0,%XMM0	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPTERNLOGQ $0x56,0x1700(%RSP),%XMM2,%XMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPTESTMQ 0xa938(%RIP){1to0},%XMM1,%K1	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (25.0%)
VPXORQ 0xa936(%RIP){1to2},%XMM0,%XMM0{%K1}	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVDQU %XMM0,0xa98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0xab0(%RSP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $0x3fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x1,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND %R8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR 0x1710(%RSP),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	N/A
AND $0x1,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
NEG %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
AND %EDI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RCX,0xaa8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $-0xc,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x1710(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x398(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $0x3fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x1,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
AND %R8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
XOR 0xff8(%RSP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	scal (12.5%)
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
NEG %EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %EDI,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RDX,0x1710(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JMP 404a6b <main+0x164b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSS 0xa74e(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %R9,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 4088d0 <nextafterf>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x18(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x7fffffffc0000000,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
MOV $-0x66f74f21,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV 0xf8(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP $0x270,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 404790 <main+0x1370>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x398(%RSP,%RDX,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0xb,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x7,%EAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $-0x62d3a980,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0xf,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
AND $-0x103a0000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x12,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
XOR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VCVTUSI2SS %RAX,%XMM8,%XMM0	3	0.50	0.50	0	0	0	2	0	0	0	0	0	0	8	2	scal (12.5%)
VMULSS 0xa6ae(%RIP),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VUCOMISS 0xa69a(%RIP),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (6.3%)
JAE 404d32 <main+0x1912>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x70(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP $0x270,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 404da0 <main+0x1980>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ 0xa6c5(%RIP),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0xa6c4(%RIP),%YMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0xa6c3(%RIP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0xa6c2(%RIP),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xaa8(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVDQU 0xaa0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM1,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VEXTRACTI128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPUNPCKHQDQ 0xaa0(%RSP){1to2},%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	scal (12.5%)
VPANDQ 0xa60d(%RIP){1to2},%XMM2,%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VPANDQ 0xa606(%RIP){1to2},%XMM0,%XMM0	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPTERNLOGQ $0x56,0x1700(%RSP),%XMM2,%XMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPTESTMQ 0xa5f8(%RIP){1to0},%XMM1,%K1	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (25.0%)
VPXORQ 0xa5f6(%RIP){1to2},%XMM0,%XMM0{%K1}	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVDQU %XMM0,0xa98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
MOV 0xab0(%RSP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $0x3fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x1,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND %R8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR 0x1710(%RSP),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	N/A
AND $0x1,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
NEG %ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
AND %EDI,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RCX,0xaa8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $-0xc,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x1710(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x398(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x1,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $0x3fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SHR $0x1,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
AND %R8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
ADD %RDX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
XOR 0xff8(%RSP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	scal (12.5%)
MOV %EAX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
NEG %EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %EDI,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RDX,0x1710(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JMP 404dab <main+0x198b>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSS 0xa40e(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %R9,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 4088d0 <nextafterf>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x18(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x7fffffffc0000000,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
MOV $-0x66f74f21,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV 0xf8(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x70(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP $0x270,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JAE 404ad0 <main+0x16b0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x398(%RSP,%RDX,8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0xb,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x7,%EAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $-0x62d3a980,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0xf,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
AND $-0x103a0000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x12,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
XOR %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VCVTUSI2SS %RAX,%XMM8,%XMM0	3	0.50	0.50	0	0	0	2	0	0	0	0	0	0	8	2	scal (12.5%)
VMULSS 0xa36e(%RIP),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VUCOMISS 0xa35a(%RIP),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (6.3%)
JAE 404e11 <main+0x19f1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x68(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RAX,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x1(%R9),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %RSI,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 4044a0 <main+0x1080>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSS 0xa32f(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %R9,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 4088d0 <nextafterf>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x18(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $0x7fffffffc0000000,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	scal (12.5%)
MOV $-0x66f74f21,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV 0xf8(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JMP 404df4 <main+0x19d4>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Masked instructions

Details

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Masked instructions

Details

Workaround

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code