OV - attention-gnr-256 - Loop 41

	Loop Id: 41	Module: attention-gnr-256	Source: attention_v2.cpp:27-33	Coverage: 1.07%

0x404f0c MOV	%R8D,%EDI

0x404f0f NOP

0x404f10 VCVTSD2SS	%XMM0,%XMM0,%XMM0

0x404f14 ADD	%EDX,%EDI

0x404f16 MOV	0x58(%RSP),%RCX

0x404f1b VMOVSS	%XMM0,(%RCX,%RDI,4)

0x404f20 LEA	0x1(%R8),%RSI

0x404f24 CMP	0x198(%RSP),%R8

0x404f2c MOV	%RSI,%R8

0x404f2f JE	404e90

0x404f35 VXORPS	%XMM0,%XMM0,%XMM0

0x404f39 CMPL	$0x8,0xc8(%RSP)

0x404f41 MOV	0x20(%RSP),%RCX

0x404f46 MOV	0x78(%RSP),%R9

0x404f4b VMOVDQU	0x300(%RSP),%YMM5

0x404f54 VPMOVSXBD	0xa20b(%RIP),%YMM6

0x404f5d VPMOVSXBD	0xa20a(%RIP),%YMM7

0x404f66 VPBROADCASTQ	0xa209(%RIP),%YMM8

0x404f6f VPMOVSXBQ	0xa1cc(%RIP),%YMM9

0x404f78 VPBROADCASTD	0xa1bf(%RIP),%YMM10

0x404f81 JB	405086

0x404f87 MOV	%R8D,%EDI

0x404f8a MOV	%EAX,%R11D

0x404f8d MOV	0x188(%RSP),%R10

0x404f95 NOPW	%CS:(%RAX,%RAX,1)

  (42) 0x404fa0 LEA	0x5(%R11),%ESI

  (42) 0x404fa4 VPBROADCASTD	%R11D,%XMM1

  (42) 0x404faa VPADDD	%YMM6,%YMM1,%YMM2

  (42) 0x404fae VPERMT2D	%YMM1,%YMM7,%YMM2

  (42) 0x404fb4 VPBROADCASTD	%ESI,%YMM3

  (42) 0x404fba VPBLENDD	$0x20,%YMM3,%YMM2,%YMM2

  (42) 0x404fc0 VPADDD	%YMM1,%YMM8,%YMM1

  (42) 0x404fc4 VPERMT2Q	%YMM1,%YMM9,%YMM2

  (42) 0x404fca VPSUBD	%YMM10,%YMM2,%YMM1

  (42) 0x404fcf LEA	(%RCX,%R14,1),%RSI

  (42) 0x404fd3 VPXOR	%XMM2,%XMM2,%XMM2

  (42) 0x404fd7 KXNORW	%K0,%K0,%K1

  (42) 0x404fdb VGATHERDPS	(%RSI,%YMM1,4),%YMM2{%K1}

  (42) 0x404fe2 LEA	(%R12,%RDI,1),%ESI

  (42) 0x404fe6 VPBROADCASTD	%ESI,%YMM1

  (42) 0x404fec LEA	(%R13,%RDI,1),%ESI

  (42) 0x404ff1 VPBROADCASTD	%EDI,%XMM3

  (42) 0x404ff7 VPADDD	%YMM5,%YMM3,%YMM4

  (42) 0x404ffb VPERMT2D	%YMM3,%YMM7,%YMM4

  (42) 0x405001 VPBLENDD	$0x20,%YMM1,%YMM4,%YMM1

  (42) 0x405007 VPBROADCASTD	%ESI,%YMM3

  (42) 0x40500d LEA	(%R15,%RDI,1),%ESI

  (42) 0x405011 VPBLENDD	$0x40,%YMM3,%YMM1,%YMM1

  (42) 0x405017 VPBROADCASTD	%ESI,%YMM3

  (42) 0x40501d VPBLENDD	$-0x80,%YMM3,%YMM1,%YMM1

  (42) 0x405023 VPSUBD	%YMM10,%YMM1,%YMM1

  (42) 0x405028 LEA	(%R9,%R14,1),%RSI

  (42) 0x40502c VPXOR	%XMM3,%XMM3,%XMM3

  (42) 0x405030 KXNORW	%K0,%K0,%K1

  (42) 0x405034 VGATHERDPS	(%RSI,%YMM1,4),%YMM3{%K1}

  (42) 0x40503b VCVTPS2PD	%XMM2,%YMM1

  (42) 0x40503f VEXTRACTF128	$0x1,%YMM2,%XMM2

  (42) 0x405045 VCVTPS2PD	%XMM2,%YMM2

  (42) 0x405049 VCVTPS2PD	%XMM3,%YMM4

  (42) 0x40504d VEXTRACTF128	$0x1,%YMM3,%XMM3

  (42) 0x405053 VCVTPS2PD	%XMM3,%YMM3

  (42) 0x405057 VMULPD	%YMM2,%YMM3,%YMM2

  (42) 0x40505b VFMADD231PD	%YMM4,%YMM1,%YMM2

  (42) 0x405060 VEXTRACTF128	$0x1,%YMM2,%XMM1

  (42) 0x405066 VADDPD	%XMM1,%XMM2,%XMM1

  (42) 0x40506a VSHUFPD	$0x1,%XMM1,%XMM1,%XMM2

  (42) 0x40506f VADDSD	%XMM2,%XMM1,%XMM1

  (42) 0x405073 VADDSD	%XMM1,%XMM0,%XMM0

  (42) 0x405077 ADD	$0x8,%R11D

  (42) 0x40507b ADD	%EBX,%EDI

  (42) 0x40507d DEC	%R10

  (42) 0x405080 JNE	404fa0

0x405086 MOV	0x1a0(%RSP),%RCX

0x40508e CMP	$0x6,%RCX

0x405092 MOV	0x238(%RSP),%R9

0x40509a JA	404f0c

/home/eoseret/llm-attention/attention_v2.cpp: 27 - 33

--------------------------------------------------------------------------------

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.38
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	9.43
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.50
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	5.50
CQA cycles if fully vectorized	0.58
Front-end cycles	5.50
P0 cycles	2.00
P1 cycles	2.10
P2 cycles	4.67
P3 cycles	4.67
P4 cycles	0.50
P5 cycles	4.00
P6 cycles	1.90
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	2.00
P11 cycles	4.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	29.00
Nb uops	33.00
Nb loads	14.00
Nb stores	1.00
Nb stack references	9.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.27
Bytes prefetched	0.00
Bytes loaded	124.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	33.33
Vectorization ratio load	36.36
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	14.29
Vector-efficiency ratio all	13.75
Vector-efficiency ratio load	14.20
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.61

Metric	Value
CQA speedup if no scalar integer	1.38
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	9.43
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.50
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	5.50
CQA cycles if fully vectorized	0.58
Front-end cycles	5.50
P0 cycles	2.00
P1 cycles	2.10
P2 cycles	4.67
P3 cycles	4.67
P4 cycles	0.50
P5 cycles	4.00
P6 cycles	1.90
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	2.00
P11 cycles	4.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	29.00
Nb uops	33.00
Nb loads	14.00
Nb stores	1.00
Nb stack references	9.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.27
Bytes prefetched	0.00
Bytes loaded	124.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	33.33
Vectorization ratio load	36.36
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	14.29
Vector-efficiency ratio all	13.75
Vector-efficiency ratio load	14.20
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.61

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-gnr-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:27-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:27,30-33.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.50 to 4.00 cycles (1.37x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33
VPMOVSXBD: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:27
- /home/eoseret/llm-attention/attention_v2.cpp:27
VPMOVSXBQ: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:27

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33
VPMOVSXBD: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:27
- /home/eoseret/llm-attention/attention_v2.cpp:27
VPMOVSXBQ: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:27

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 124 bytes. The binary loop is storing 4 bytes.

General properties

nb instructions	29
nb uops	33
loop length	174
used x86 registers	10
used mmx registers	0
used xmm registers	1
used ymm registers	6
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.50 cycles
front end	5.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.00	2.10	4.67	4.67	0.50	4.00	1.90	0.50	0.50	0.50	2.00	4.67
cycles	2.00	2.10	4.67	4.67	0.50	4.00	1.90	0.50	0.50	0.50	2.00	4.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.50
Dispatch	4.67
Overall L1	5.50

Vectorization ratios

INT

all	33%
load	36%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	33%
load	36%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

INT

all	13%
load	14%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	13%
load	14%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.50 cycles. At this rate:

11% of peak load performance is reached (22.55 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.73 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.50 to 4.67 cycles (1.18x speedup).

ASM code

In the binary file, the address of the loop is: 404f35

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV %R8D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
ADD %EDX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x58(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RCX,%RDI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x1(%R8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP 0x198(%RSP),%R8	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 404e90 <main+0x1a70>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CMPL $0x8,0xc8(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
MOV 0x20(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVDQU 0x300(%RSP),%YMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VPMOVSXBD 0xa20b(%RIP),%YMM6	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VPMOVSXBD 0xa20a(%RIP),%YMM7	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VPBROADCASTQ 0xa209(%RIP),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPMOVSXBQ 0xa1cc(%RIP),%YMM9	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (6.3%)
VPBROADCASTD 0xa1bf(%RIP),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
JB 405086 <main+0x1c66>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x188(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x1a0(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP $0x6,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x238(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JA 404f0c <main+0x1aec>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-gnr-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:27-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:27,30-33.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.50 to 4.00 cycles (1.37x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33
VPMOVSXBD: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:27
- /home/eoseret/llm-attention/attention_v2.cpp:27
VPMOVSXBQ: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:27

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33
VPMOVSXBD: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:27
- /home/eoseret/llm-attention/attention_v2.cpp:27
VPMOVSXBQ: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:27

Workaround

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 124 bytes. The binary loop is storing 4 bytes.

General properties

nb instructions	29
nb uops	33
loop length	174
used x86 registers	10
used mmx registers	0
used xmm registers	1
used ymm registers	6
used zmm registers	0
nb stack references	9

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.50 cycles
front end	5.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.00	2.10	4.67	4.67	0.50	4.00	1.90	0.50	0.50	0.50	2.00	4.67
cycles	2.00	2.10	4.67	4.67	0.50	4.00	1.90	0.50	0.50	0.50	2.00	4.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.50
Dispatch	4.67
Overall L1	5.50

Vectorization ratios

INT

all	33%
load	36%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	33%
load	36%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

INT

all	13%
load	14%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	13%
load	14%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.50 cycles. At this rate:

11% of peak load performance is reached (22.55 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.73 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 404f35

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV %R8D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
ADD %EDX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x58(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RCX,%RDI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x1(%R8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP 0x198(%RSP),%R8	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 404e90 <main+0x1a70>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CMPL $0x8,0xc8(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
MOV 0x20(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVDQU 0x300(%RSP),%YMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VPMOVSXBD 0xa20b(%RIP),%YMM6	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VPMOVSXBD 0xa20a(%RIP),%YMM7	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VPBROADCASTQ 0xa209(%RIP),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPMOVSXBQ 0xa1cc(%RIP),%YMM9	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (6.3%)
VPBROADCASTD 0xa1bf(%RIP),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
JB 405086 <main+0x1c66>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x188(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x1a0(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP $0x6,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x238(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JA 404f0c <main+0x1aec>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code