OV - attention-gnr-256 - Loop 38

	Loop Id: 38	Module: attention-gnr-256	Source: attention_v2.cpp:27-33	Coverage: 1.33%

0x40532c MOV	%R8D,%EDI

0x40532f NOP

0x405330 VCVTSD2SS	%XMM0,%XMM0,%XMM0

0x405334 ADD	%EDX,%EDI

0x405336 MOV	0xd0(%RSP),%RCX

0x40533e VMOVSS	%XMM0,(%RCX,%RDI,4)

0x405343 LEA	0x1(%R8),%RSI

0x405347 CMP	0x198(%RSP),%R8

0x40534f MOV	%RSI,%R8

0x405352 JE	4052b0

0x405358 VXORPS	%XMM0,%XMM0,%XMM0

0x40535c CMPL	$0x8,0xc8(%RSP)

0x405364 MOV	0x20(%RSP),%RCX

0x405369 MOV	0x70(%RSP),%R9

0x40536e VMOVDQU	0x300(%RSP),%YMM5

0x405377 VPMOVSXBD	0x9de8(%RIP),%YMM6

0x405380 VPMOVSXBD	0x9de7(%RIP),%YMM7

0x405389 VPBROADCASTQ	0x9de6(%RIP),%YMM8

0x405392 VPMOVSXBQ	0x9da9(%RIP),%YMM9

0x40539b VPBROADCASTD	0x9d9c(%RIP),%YMM10

0x4053a4 JB	4054a6

0x4053aa MOV	%R8D,%EDI

0x4053ad MOV	%EAX,%R11D

0x4053b0 MOV	0x188(%RSP),%R10

0x4053b8 NOPL	(%RAX,%RAX,1)

  (39) 0x4053c0 LEA	0x5(%R11),%ESI

  (39) 0x4053c4 VPBROADCASTD	%R11D,%XMM1

  (39) 0x4053ca VPADDD	%YMM6,%YMM1,%YMM2

  (39) 0x4053ce VPERMT2D	%YMM1,%YMM7,%YMM2

  (39) 0x4053d4 VPBROADCASTD	%ESI,%YMM3

  (39) 0x4053da VPBLENDD	$0x20,%YMM3,%YMM2,%YMM2

  (39) 0x4053e0 VPADDD	%YMM1,%YMM8,%YMM1

  (39) 0x4053e4 VPERMT2Q	%YMM1,%YMM9,%YMM2

  (39) 0x4053ea VPSUBD	%YMM10,%YMM2,%YMM1

  (39) 0x4053ef LEA	(%RCX,%R14,1),%RSI

  (39) 0x4053f3 VPXOR	%XMM2,%XMM2,%XMM2

  (39) 0x4053f7 KXNORW	%K0,%K0,%K1

  (39) 0x4053fb VGATHERDPS	(%RSI,%YMM1,4),%YMM2{%K1}

  (39) 0x405402 LEA	(%R12,%RDI,1),%ESI

  (39) 0x405406 VPBROADCASTD	%ESI,%YMM1

  (39) 0x40540c LEA	(%R13,%RDI,1),%ESI

  (39) 0x405411 VPBROADCASTD	%EDI,%XMM3

  (39) 0x405417 VPADDD	%YMM5,%YMM3,%YMM4

  (39) 0x40541b VPERMT2D	%YMM3,%YMM7,%YMM4

  (39) 0x405421 VPBLENDD	$0x20,%YMM1,%YMM4,%YMM1

  (39) 0x405427 VPBROADCASTD	%ESI,%YMM3

  (39) 0x40542d LEA	(%R15,%RDI,1),%ESI

  (39) 0x405431 VPBLENDD	$0x40,%YMM3,%YMM1,%YMM1

  (39) 0x405437 VPBROADCASTD	%ESI,%YMM3

  (39) 0x40543d VPBLENDD	$-0x80,%YMM3,%YMM1,%YMM1

  (39) 0x405443 VPSUBD	%YMM10,%YMM1,%YMM1

  (39) 0x405448 LEA	(%R9,%R14,1),%RSI

  (39) 0x40544c VPXOR	%XMM3,%XMM3,%XMM3

  (39) 0x405450 KXNORW	%K0,%K0,%K1

  (39) 0x405454 VGATHERDPS	(%RSI,%YMM1,4),%YMM3{%K1}

  (39) 0x40545b VCVTPS2PD	%XMM2,%YMM1

  (39) 0x40545f VEXTRACTF128	$0x1,%YMM2,%XMM2

  (39) 0x405465 VCVTPS2PD	%XMM2,%YMM2

  (39) 0x405469 VCVTPS2PD	%XMM3,%YMM4

  (39) 0x40546d VEXTRACTF128	$0x1,%YMM3,%XMM3

  (39) 0x405473 VCVTPS2PD	%XMM3,%YMM3

  (39) 0x405477 VMULPD	%YMM2,%YMM3,%YMM2

  (39) 0x40547b VFMADD231PD	%YMM4,%YMM1,%YMM2

  (39) 0x405480 VEXTRACTF128	$0x1,%YMM2,%XMM1

  (39) 0x405486 VADDPD	%XMM1,%XMM2,%XMM1

  (39) 0x40548a VSHUFPD	$0x1,%XMM1,%XMM1,%XMM2

  (39) 0x40548f VADDSD	%XMM2,%XMM1,%XMM1

  (39) 0x405493 VADDSD	%XMM1,%XMM0,%XMM0

  (39) 0x405497 ADD	$0x8,%R11D

  (39) 0x40549b ADD	%EBX,%EDI

  (39) 0x40549d DEC	%R10

  (39) 0x4054a0 JNE	4053c0

0x4054a6 MOV	0x1a0(%RSP),%RCX

0x4054ae CMP	$0x6,%RCX

0x4054b2 JA	40532c

/home/eoseret/llm-attention/attention_v2.cpp: 27 - 33

--------------------------------------------------------------------------------

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.29
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	9.54
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.19
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.17
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	5.17
CQA cycles if fully vectorized	0.54
Front-end cycles	5.17
P0 cycles	2.00
P1 cycles	1.70
P2 cycles	4.33
P3 cycles	4.33
P4 cycles	0.50
P5 cycles	4.00
P6 cycles	1.70
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	1.60
P11 cycles	4.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	31.00
Nb loads	13.00
Nb stores	1.00
Nb stack references	8.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.23
Bytes prefetched	0.00
Bytes loaded	116.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	35.71
Vectorization ratio load	40.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	14.29
Vector-efficiency ratio all	13.84
Vector-efficiency ratio load	14.38
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.61

Metric	Value
CQA speedup if no scalar integer	1.29
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	9.54
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.19
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.17
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	5.17
CQA cycles if fully vectorized	0.54
Front-end cycles	5.17
P0 cycles	2.00
P1 cycles	1.70
P2 cycles	4.33
P3 cycles	4.33
P4 cycles	0.50
P5 cycles	4.00
P6 cycles	1.70
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	1.60
P11 cycles	4.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	31.00
Nb loads	13.00
Nb stores	1.00
Nb stack references	8.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.23
Bytes prefetched	0.00
Bytes loaded	116.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	35.71
Vectorization ratio load	40.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	14.29
Vector-efficiency ratio all	13.84
Vector-efficiency ratio load	14.38
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.61

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-gnr-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:27-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:27,30-33.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.17 to 4.00 cycles (1.29x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33
VPMOVSXBD: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:27
- /home/eoseret/llm-attention/attention_v2.cpp:27
VPMOVSXBQ: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:27

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33
VPMOVSXBD: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:27
- /home/eoseret/llm-attention/attention_v2.cpp:27
VPMOVSXBQ: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:27

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 116 bytes. The binary loop is storing 4 bytes.

General properties

nb instructions	28
nb uops	31
loop length	166
used x86 registers	10
used mmx registers	0
used xmm registers	1
used ymm registers	6
used zmm registers	0
nb stack references	8

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.17 cycles
front end	5.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.00	1.70	4.33	4.33	0.50	4.00	1.70	0.50	0.50	0.50	1.60	4.33
cycles	2.00	1.70	4.33	4.33	0.50	4.00	1.70	0.50	0.50	0.50	1.60	4.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.17
Dispatch	4.33
Overall L1	5.17

Vectorization ratios

INT

all	36%
load	40%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	35%
load	40%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

INT

all	13%
load	14%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	13%
load	14%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.17 cycles. At this rate:

11% of peak load performance is reached (22.45 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.77 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.17 to 4.33 cycles (1.19x speedup).

ASM code

In the binary file, the address of the loop is: 405358

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV %R8D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
ADD %EDX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0xd0(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RCX,%RDI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x1(%R8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP 0x198(%RSP),%R8	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 4052b0 <main+0x1e90>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CMPL $0x8,0xc8(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
MOV 0x20(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x70(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVDQU 0x300(%RSP),%YMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VPMOVSXBD 0x9de8(%RIP),%YMM6	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VPMOVSXBD 0x9de7(%RIP),%YMM7	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VPBROADCASTQ 0x9de6(%RIP),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPMOVSXBQ 0x9da9(%RIP),%YMM9	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (6.3%)
VPBROADCASTD 0x9d9c(%RIP),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
JB 4054a6 <main+0x2086>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x188(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x1a0(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP $0x6,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JA 40532c <main+0x1f0c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-gnr-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:27-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:27,30-33.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.17 to 4.00 cycles (1.29x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33
VPMOVSXBD: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:27
- /home/eoseret/llm-attention/attention_v2.cpp:27
VPMOVSXBQ: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:27

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33
VPMOVSXBD: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:27
- /home/eoseret/llm-attention/attention_v2.cpp:27
VPMOVSXBQ: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:27

Workaround

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 116 bytes. The binary loop is storing 4 bytes.

General properties

nb instructions	28
nb uops	31
loop length	166
used x86 registers	10
used mmx registers	0
used xmm registers	1
used ymm registers	6
used zmm registers	0
nb stack references	8

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.17 cycles
front end	5.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.00	1.70	4.33	4.33	0.50	4.00	1.70	0.50	0.50	0.50	1.60	4.33
cycles	2.00	1.70	4.33	4.33	0.50	4.00	1.70	0.50	0.50	0.50	1.60	4.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.17
Dispatch	4.33
Overall L1	5.17

Vectorization ratios

INT

all	36%
load	40%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	35%
load	40%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

INT

all	13%
load	14%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	13%
load	14%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.17 cycles. At this rate:

11% of peak load performance is reached (22.45 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.77 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 405358

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV %R8D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
ADD %EDX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0xd0(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RCX,%RDI,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x1(%R8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP 0x198(%RSP),%R8	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 4052b0 <main+0x1e90>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPS %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CMPL $0x8,0xc8(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
MOV 0x20(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x70(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVDQU 0x300(%RSP),%YMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VPMOVSXBD 0x9de8(%RIP),%YMM6	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VPMOVSXBD 0x9de7(%RIP),%YMM7	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VPBROADCASTQ 0x9de6(%RIP),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPMOVSXBQ 0x9da9(%RIP),%YMM9	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (6.3%)
VPBROADCASTD 0x9d9c(%RIP),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
JB 4054a6 <main+0x2086>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R8D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x188(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x1a0(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP $0x6,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JA 40532c <main+0x1f0c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code