OV - attention-gnr-256 - Loop 37

0x4052b0 MOV	0xa8(%RSP),%RSI

0x4052b8 LEA	0x1(%RSI),%EDX

0x4052bb MOV	0x90(%RSP),%RCX

0x4052c3 ADD	%ECX,%EAX

0x4052c5 CMP	0xbc(%RSP),%ESI

0x4052cc JE	405680

0x4052d2 MOV	%RDX,0xa8(%RSP)

0x4052da IMUL	%ECX,%EDX

0x4052dd MOV	0x168(%RSP),%RCX

0x4052e5 LEA	(%RCX,%RDX,1),%ESI

0x4052e8 MOV	%ESI,0x18(%RSP)

0x4052ec LEA	(%RCX,%RDX,1),%ESI

0x4052ef MOV	%ESI,0x30(%RSP)

0x4052f3 LEA	(%RCX,%RDX,1),%ESI

0x4052f6 MOV	%ESI,0x60(%RSP)

0x4052fa LEA	(%RCX,%RDX,1),%ESI

0x4052fd MOV	%ESI,0x88(%RSP)

0x405304 LEA	(%RCX,%RDX,1),%ESI

0x405307 MOV	%ESI,0x98(%RSP)

0x40530e ADD	%EDX,%ECX

0x405310 MOV	%RCX,0x28(%RSP)

0x405315 MOV	0x160(%RSP),%RCX

0x40531d ADD	%EDX,%ECX

0x40531f MOV	%RCX,0xb0(%RSP)

0x405327 XOR	%R8D,%R8D

0x40532a JMP	405358

  (38) 0x40532c MOV	%R8D,%EDI

  (38) 0x40532f NOP

  (38) 0x405330 VCVTSD2SS	%XMM0,%XMM0,%XMM0

  (38) 0x405334 ADD	%EDX,%EDI

  (38) 0x405336 MOV	0xd0(%RSP),%RCX

  (38) 0x40533e VMOVSS	%XMM0,(%RCX,%RDI,4)

  (38) 0x405343 LEA	0x1(%R8),%RSI

  (38) 0x405347 CMP	0x198(%RSP),%R8

  (38) 0x40534f MOV	%RSI,%R8

  (38) 0x405352 JE	4052b0

  (38) 0x405358 VXORPS	%XMM0,%XMM0,%XMM0

  (38) 0x40535c CMPL	$0x8,0xc8(%RSP)

  (38) 0x405364 MOV	0x20(%RSP),%RCX

  (38) 0x405369 MOV	0x70(%RSP),%R9

  (38) 0x40536e VMOVDQU	0x300(%RSP),%YMM5

  (38) 0x405377 VPMOVSXBD	0x9de8(%RIP),%YMM6

  (38) 0x405380 VPMOVSXBD	0x9de7(%RIP),%YMM7

  (38) 0x405389 VPBROADCASTQ	0x9de6(%RIP),%YMM8

  (38) 0x405392 VPMOVSXBQ	0x9da9(%RIP),%YMM9

  (38) 0x40539b VPBROADCASTD	0x9d9c(%RIP),%YMM10

  (38) 0x4053a4 JB	4054a6

  (38) 0x4053aa MOV	%R8D,%EDI

  (38) 0x4053ad MOV	%EAX,%R11D

  (38) 0x4053b0 MOV	0x188(%RSP),%R10

  (38) 0x4053b8 NOPL	(%RAX,%RAX,1)

    (39) 0x4053c0 LEA	0x5(%R11),%ESI

    (39) 0x4053c4 VPBROADCASTD	%R11D,%XMM1

    (39) 0x4053ca VPADDD	%YMM6,%YMM1,%YMM2

    (39) 0x4053ce VPERMT2D	%YMM1,%YMM7,%YMM2

    (39) 0x4053d4 VPBROADCASTD	%ESI,%YMM3

    (39) 0x4053da VPBLENDD	$0x20,%YMM3,%YMM2,%YMM2

    (39) 0x4053e0 VPADDD	%YMM1,%YMM8,%YMM1

    (39) 0x4053e4 VPERMT2Q	%YMM1,%YMM9,%YMM2

    (39) 0x4053ea VPSUBD	%YMM10,%YMM2,%YMM1

    (39) 0x4053ef LEA	(%RCX,%R14,1),%RSI

    (39) 0x4053f3 VPXOR	%XMM2,%XMM2,%XMM2

    (39) 0x4053f7 KXNORW	%K0,%K0,%K1

    (39) 0x4053fb VGATHERDPS	(%RSI,%YMM1,4),%YMM2{%K1}

    (39) 0x405402 LEA	(%R12,%RDI,1),%ESI

    (39) 0x405406 VPBROADCASTD	%ESI,%YMM1

    (39) 0x40540c LEA	(%R13,%RDI,1),%ESI

    (39) 0x405411 VPBROADCASTD	%EDI,%XMM3

    (39) 0x405417 VPADDD	%YMM5,%YMM3,%YMM4

    (39) 0x40541b VPERMT2D	%YMM3,%YMM7,%YMM4

    (39) 0x405421 VPBLENDD	$0x20,%YMM1,%YMM4,%YMM1

    (39) 0x405427 VPBROADCASTD	%ESI,%YMM3

    (39) 0x40542d LEA	(%R15,%RDI,1),%ESI

    (39) 0x405431 VPBLENDD	$0x40,%YMM3,%YMM1,%YMM1

    (39) 0x405437 VPBROADCASTD	%ESI,%YMM3

    (39) 0x40543d VPBLENDD	$-0x80,%YMM3,%YMM1,%YMM1

    (39) 0x405443 VPSUBD	%YMM10,%YMM1,%YMM1

    (39) 0x405448 LEA	(%R9,%R14,1),%RSI

    (39) 0x40544c VPXOR	%XMM3,%XMM3,%XMM3

    (39) 0x405450 KXNORW	%K0,%K0,%K1

    (39) 0x405454 VGATHERDPS	(%RSI,%YMM1,4),%YMM3{%K1}

    (39) 0x40545b VCVTPS2PD	%XMM2,%YMM1

    (39) 0x40545f VEXTRACTF128	$0x1,%YMM2,%XMM2

    (39) 0x405465 VCVTPS2PD	%XMM2,%YMM2

    (39) 0x405469 VCVTPS2PD	%XMM3,%YMM4

    (39) 0x40546d VEXTRACTF128	$0x1,%YMM3,%XMM3

    (39) 0x405473 VCVTPS2PD	%XMM3,%YMM3

    (39) 0x405477 VMULPD	%YMM2,%YMM3,%YMM2

    (39) 0x40547b VFMADD231PD	%YMM4,%YMM1,%YMM2

    (39) 0x405480 VEXTRACTF128	$0x1,%YMM2,%XMM1

    (39) 0x405486 VADDPD	%XMM1,%XMM2,%XMM1

    (39) 0x40548a VSHUFPD	$0x1,%XMM1,%XMM1,%XMM2

    (39) 0x40548f VADDSD	%XMM2,%XMM1,%XMM1

    (39) 0x405493 VADDSD	%XMM1,%XMM0,%XMM0

    (39) 0x405497 ADD	$0x8,%R11D

    (39) 0x40549b ADD	%EBX,%EDI

    (39) 0x40549d DEC	%R10

    (39) 0x4054a0 JNE	4053c0

  (38) 0x4054a6 MOV	0x1a0(%RSP),%RCX

  (38) 0x4054ae CMP	$0x6,%RCX

  (38) 0x4054b2 JA	40532c

/home/eoseret/llm-attention/attention_v2.cpp: 26 - 194

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

[...]

194:       start = std::chrono::steady_clock::now();

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.61
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-26,attention_v2.cpp:31-31,attention_v2.cpp:194-194
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.33
CQA cycles if no scalar integer	4.33
CQA cycles if FP arith vectorized	4.33
CQA cycles if fully vectorized	0.34
Front-end cycles	4.33
P0 cycles	2.50
P1 cycles	3.00
P2 cycles	1.67
P3 cycles	1.67
P4 cycles	4.00
P5 cycles	2.40
P6 cycles	2.30
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	2.40
P11 cycles	1.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.00
Nb uops	26.00
Nb loads	5.00
Nb stores	8.00
Nb stack references	12.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.46
Bytes prefetched	0.00
Bytes loaded	36.00
Bytes stored	44.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	7.95
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	8.59
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.61
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-26,attention_v2.cpp:31-31,attention_v2.cpp:194-194
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.33
CQA cycles if no scalar integer	4.33
CQA cycles if FP arith vectorized	4.33
CQA cycles if fully vectorized	0.34
Front-end cycles	4.33
P0 cycles	2.50
P1 cycles	3.00
P2 cycles	1.67
P3 cycles	1.67
P4 cycles	4.00
P5 cycles	2.40
P6 cycles	2.30
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	2.40
P11 cycles	1.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.00
Nb uops	26.00
Nb loads	5.00
Nb stores	8.00
Nb stack references	12.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.46
Bytes prefetched	0.00
Bytes loaded	36.00
Bytes stored	44.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	7.95
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	8.59
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:26-194
Module	attention-gnr-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-33,194.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:26,31,194.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.33 to 0.34 cycles (12.61x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 36 bytes. The binary loop is storing 44 bytes.

General properties

nb instructions	26
nb uops	26
loop length	124
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.33 cycles
front end	4.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.50	2.40	1.67	1.67	4.00	2.40	2.30	4.00	4.00	4.00	2.40	1.67
cycles	2.50	3.00	1.67	1.67	4.00	2.40	2.30	4.00	4.00	4.00	2.40	1.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.33
Dispatch	4.00
Overall L1	4.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	6%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.33 cycles. At this rate:

4% of peak load performance is reached (8.31 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (10.15 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.33 to 4.00 cycles (1.08x speedup).

ASM code

In the binary file, the address of the loop is: 4052d2

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV 0xa8(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%RSI),%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV 0x90(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %ECX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP 0xbc(%RSP),%ESI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JE 405680 <main+0x2260>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDX,0xa8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL %ECX,%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x168(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RCX,%RDX,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %ESI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA (%RCX,%RDX,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %ESI,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA (%RCX,%RDX,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %ESI,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA (%RCX,%RDX,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %ESI,0x88(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA (%RCX,%RDX,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %ESI,0x98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x160(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,0xb0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 405358 <main+0x1f38>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

Function	main
Source file and lines	attention_v2.cpp:26-194
Module	attention-gnr-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-33,194.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:26,31,194.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.33 to 0.34 cycles (12.61x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 36 bytes. The binary loop is storing 44 bytes.

General properties

nb instructions	26
nb uops	26
loop length	124
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.33 cycles
front end	4.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.50	2.40	1.67	1.67	4.00	2.40	2.30	4.00	4.00	4.00	2.40	1.67
cycles	2.50	3.00	1.67	1.67	4.00	2.40	2.30	4.00	4.00	4.00	2.40	1.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.33
Dispatch	4.00
Overall L1	4.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	6%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.33 cycles. At this rate:

4% of peak load performance is reached (8.31 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (10.15 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.33 to 4.00 cycles (1.08x speedup).

ASM code

In the binary file, the address of the loop is: 4052d2

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV 0xa8(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%RSI),%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV 0x90(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %ECX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
CMP 0xbc(%RSP),%ESI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JE 405680 <main+0x2260>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDX,0xa8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL %ECX,%EDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x168(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RCX,%RDX,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %ESI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA (%RCX,%RDX,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %ESI,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA (%RCX,%RDX,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %ESI,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA (%RCX,%RDX,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %ESI,0x88(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA (%RCX,%RDX,1),%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %ESI,0x98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x160(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,0xb0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 405358 <main+0x1f38>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code