| Loop Id: 35 | Module: attention-gnr-256 | Source: attention_v2.cpp:27-33 | Coverage: 1.39% |
|---|
| Loop Id: 35 | Module: attention-gnr-256 | Source: attention_v2.cpp:27-33 | Coverage: 1.39% |
|---|
0x40574c MOV %R8D,%EDI |
0x40574f NOP |
0x405750 VCVTSD2SS %XMM0,%XMM0,%XMM0 |
0x405754 ADD %EDX,%EDI |
0x405756 MOV 0x80(%RSP),%RCX |
0x40575e VMOVSS %XMM0,(%RCX,%RDI,4) |
0x405763 LEA 0x1(%R8),%RSI |
0x405767 CMP 0x198(%RSP),%R8 |
0x40576f MOV %RSI,%R8 |
0x405772 JE 4056d0 |
0x405778 VXORPS %XMM0,%XMM0,%XMM0 |
0x40577c CMPL $0x8,0xc8(%RSP) |
0x405784 MOV 0x20(%RSP),%RCX |
0x405789 MOV 0x68(%RSP),%R9 |
0x40578e VMOVDQU 0x300(%RSP),%YMM5 |
0x405797 VPMOVSXBD 0x99c8(%RIP),%YMM6 |
0x4057a0 VPMOVSXBD 0x99c7(%RIP),%YMM7 |
0x4057a9 VPBROADCASTQ 0x99c6(%RIP),%YMM8 |
0x4057b2 VPMOVSXBQ 0x9989(%RIP),%YMM9 |
0x4057bb VPBROADCASTD 0x997c(%RIP),%YMM10 |
0x4057c4 JB 4058c6 |
0x4057ca MOV %R8D,%EDI |
0x4057cd MOV %EAX,%R11D |
0x4057d0 MOV 0x188(%RSP),%R10 |
0x4057d8 NOPL (%RAX,%RAX,1) |
(36) 0x4057e0 LEA 0x5(%R11),%ESI |
(36) 0x4057e4 VPBROADCASTD %R11D,%XMM1 |
(36) 0x4057ea VPADDD %YMM6,%YMM1,%YMM2 |
(36) 0x4057ee VPERMT2D %YMM1,%YMM7,%YMM2 |
(36) 0x4057f4 VPBROADCASTD %ESI,%YMM3 |
(36) 0x4057fa VPBLENDD $0x20,%YMM3,%YMM2,%YMM2 |
(36) 0x405800 VPADDD %YMM1,%YMM8,%YMM1 |
(36) 0x405804 VPERMT2Q %YMM1,%YMM9,%YMM2 |
(36) 0x40580a VPSUBD %YMM10,%YMM2,%YMM1 |
(36) 0x40580f LEA (%RCX,%R14,1),%RSI |
(36) 0x405813 KXNORW %K0,%K0,%K1 |
(36) 0x405817 VPXOR %XMM2,%XMM2,%XMM2 |
(36) 0x40581b VGATHERDPS (%RSI,%YMM1,4),%YMM2{%K1} |
(36) 0x405822 LEA (%R12,%RDI,1),%ESI |
(36) 0x405826 VPBROADCASTD %ESI,%YMM1 |
(36) 0x40582c LEA (%R13,%RDI,1),%ESI |
(36) 0x405831 VPBROADCASTD %EDI,%XMM3 |
(36) 0x405837 VPADDD %YMM5,%YMM3,%YMM4 |
(36) 0x40583b VPERMT2D %YMM3,%YMM7,%YMM4 |
(36) 0x405841 VPBLENDD $0x20,%YMM1,%YMM4,%YMM1 |
(36) 0x405847 VPBROADCASTD %ESI,%YMM3 |
(36) 0x40584d LEA (%R15,%RDI,1),%ESI |
(36) 0x405851 VPBLENDD $0x40,%YMM3,%YMM1,%YMM1 |
(36) 0x405857 VPBROADCASTD %ESI,%YMM3 |
(36) 0x40585d VPBLENDD $-0x80,%YMM3,%YMM1,%YMM1 |
(36) 0x405863 VPSUBD %YMM10,%YMM1,%YMM1 |
(36) 0x405868 LEA (%R9,%R14,1),%RSI |
(36) 0x40586c KXNORW %K0,%K0,%K1 |
(36) 0x405870 VPXOR %XMM3,%XMM3,%XMM3 |
(36) 0x405874 VGATHERDPS (%RSI,%YMM1,4),%YMM3{%K1} |
(36) 0x40587b VCVTPS2PD %XMM2,%YMM1 |
(36) 0x40587f VEXTRACTF128 $0x1,%YMM2,%XMM2 |
(36) 0x405885 VCVTPS2PD %XMM2,%YMM2 |
(36) 0x405889 VCVTPS2PD %XMM3,%YMM4 |
(36) 0x40588d VEXTRACTF128 $0x1,%YMM3,%XMM3 |
(36) 0x405893 VCVTPS2PD %XMM3,%YMM3 |
(36) 0x405897 VMULPD %YMM2,%YMM3,%YMM2 |
(36) 0x40589b VFMADD231PD %YMM4,%YMM1,%YMM2 |
(36) 0x4058a0 VEXTRACTF128 $0x1,%YMM2,%XMM1 |
(36) 0x4058a6 VADDPD %XMM1,%XMM2,%XMM1 |
(36) 0x4058aa VSHUFPD $0x1,%XMM1,%XMM1,%XMM2 |
(36) 0x4058af VADDSD %XMM2,%XMM1,%XMM1 |
(36) 0x4058b3 VADDSD %XMM1,%XMM0,%XMM0 |
(36) 0x4058b7 ADD $0x8,%R11D |
(36) 0x4058bb ADD %EBX,%EDI |
(36) 0x4058bd DEC %R10 |
(36) 0x4058c0 JNE 4057e0 |
0x4058c6 MOV 0x1a0(%RSP),%RCX |
0x4058ce CMP $0x6,%RCX |
0x4058d2 JA 40574c |
/home/eoseret/llm-attention/attention_v2.cpp: 27 - 33 |
-------------------------------------------------------------------------------- |
27: for (unsigned int j = 0; j < N; ++j) { //vectorized |
28: double sum = 0.0; |
29: #pragma clang loop vectorize(enable) |
30: for (unsigned int k = 0; k < K; ++k) { //vectorized |
31: sum += (double)A[i * K + k] * (double)B[k * N + j]; |
32: } |
33: C[i * N + j] = alpha * static_cast<float>(sum); |
| Coverage (%) | Name | Source Location | Module |
|---|
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.29 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 9.54 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.19 |
| Bottlenecks | micro-operation queue, |
| Function | main |
| Source | attention_v2.cpp:27-27,attention_v2.cpp:30-33 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 5.17 |
| CQA cycles if no scalar integer | 4.00 |
| CQA cycles if FP arith vectorized | 5.17 |
| CQA cycles if fully vectorized | 0.54 |
| Front-end cycles | 5.17 |
| P0 cycles | 2.00 |
| P1 cycles | 1.70 |
| P2 cycles | 4.33 |
| P3 cycles | 4.33 |
| P4 cycles | 0.50 |
| P5 cycles | 4.00 |
| P6 cycles | 1.70 |
| P7 cycles | 0.50 |
| P8 cycles | 0.50 |
| P9 cycles | 0.50 |
| P10 cycles | 1.60 |
| P11 cycles | 4.33 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 28.00 |
| Nb uops | 31.00 |
| Nb loads | 13.00 |
| Nb stores | 1.00 |
| Nb stack references | 8.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 23.23 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 116.00 |
| Bytes stored | 4.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 35.71 |
| Vectorization ratio load | 40.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 14.29 |
| Vector-efficiency ratio all | 13.84 |
| Vector-efficiency ratio load | 14.38 |
| Vector-efficiency ratio store | 6.25 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 11.61 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.29 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 9.54 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.19 |
| Bottlenecks | micro-operation queue, |
| Function | main |
| Source | attention_v2.cpp:27-27,attention_v2.cpp:30-33 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 5.17 |
| CQA cycles if no scalar integer | 4.00 |
| CQA cycles if FP arith vectorized | 5.17 |
| CQA cycles if fully vectorized | 0.54 |
| Front-end cycles | 5.17 |
| P0 cycles | 2.00 |
| P1 cycles | 1.70 |
| P2 cycles | 4.33 |
| P3 cycles | 4.33 |
| P4 cycles | 0.50 |
| P5 cycles | 4.00 |
| P6 cycles | 1.70 |
| P7 cycles | 0.50 |
| P8 cycles | 0.50 |
| P9 cycles | 0.50 |
| P10 cycles | 1.60 |
| P11 cycles | 4.33 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 28.00 |
| Nb uops | 31.00 |
| Nb loads | 13.00 |
| Nb stores | 1.00 |
| Nb stack references | 8.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 23.23 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 116.00 |
| Bytes stored | 4.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 35.71 |
| Vectorization ratio load | 40.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 14.29 |
| Vector-efficiency ratio all | 13.84 |
| Vector-efficiency ratio load | 14.38 |
| Vector-efficiency ratio store | 6.25 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 11.61 |
| Path / |
| Function | main |
| Source file and lines | attention_v2.cpp:27-33 |
| Module | attention-gnr-256 |
| nb instructions | 28 |
| nb uops | 31 |
| loop length | 166 |
| used x86 registers | 10 |
| used mmx registers | 0 |
| used xmm registers | 1 |
| used ymm registers | 6 |
| used zmm registers | 0 |
| nb stack references | 8 |
| micro-operation queue | 5.17 cycles |
| front end | 5.17 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 2.00 | 1.70 | 4.33 | 4.33 | 0.50 | 4.00 | 1.70 | 0.50 | 0.50 | 0.50 | 1.60 | 4.33 |
| cycles | 2.00 | 1.70 | 4.33 | 4.33 | 0.50 | 4.00 | 1.70 | 0.50 | 0.50 | 0.50 | 1.60 | 4.33 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 5.17 |
| Dispatch | 4.33 |
| Overall L1 | 5.17 |
| all | 36% |
| load | 40% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 33% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 50% |
| all | 35% |
| load | 40% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 14% |
| all | 13% |
| load | 14% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 8% |
| all | 14% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 6% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 18% |
| all | 13% |
| load | 14% |
| store | 6% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 11% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV %R8D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| VCVTSD2SS %XMM0,%XMM0,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | scal (12.5%) |
| ADD %EDX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV 0x80(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| VMOVSS %XMM0,(%RCX,%RDI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| LEA 0x1(%R8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| CMP 0x198(%RSP),%R8 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | scal (12.5%) |
| MOV %RSI,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| JE 4056d0 <main+0x22b0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| VXORPS %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| CMPL $0x8,0xc8(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | scal (6.3%) |
| MOV 0x20(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV 0x68(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| VMOVDQU 0x300(%RSP),%YMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VPMOVSXBD 0x99c8(%RIP),%YMM6 | 2 | 0 | 0 | 0.33 | 0.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 | vect (12.5%) |
| VPMOVSXBD 0x99c7(%RIP),%YMM7 | 2 | 0 | 0 | 0.33 | 0.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 | vect (12.5%) |
| VPBROADCASTQ 0x99c6(%RIP),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 | scal (12.5%) |
| VPMOVSXBQ 0x9989(%RIP),%YMM9 | 2 | 0 | 0 | 0.33 | 0.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 | vect (6.3%) |
| VPBROADCASTD 0x997c(%RIP),%YMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 | scal (6.3%) |
| JB 4058c6 <main+0x24a6> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| MOV %R8D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| MOV %EAX,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| MOV 0x188(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV 0x1a0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| CMP $0x6,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| JA 40574c <main+0x232c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| Function | main |
| Source file and lines | attention_v2.cpp:27-33 |
| Module | attention-gnr-256 |
| nb instructions | 28 |
| nb uops | 31 |
| loop length | 166 |
| used x86 registers | 10 |
| used mmx registers | 0 |
| used xmm registers | 1 |
| used ymm registers | 6 |
| used zmm registers | 0 |
| nb stack references | 8 |
| micro-operation queue | 5.17 cycles |
| front end | 5.17 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 2.00 | 1.70 | 4.33 | 4.33 | 0.50 | 4.00 | 1.70 | 0.50 | 0.50 | 0.50 | 1.60 | 4.33 |
| cycles | 2.00 | 1.70 | 4.33 | 4.33 | 0.50 | 4.00 | 1.70 | 0.50 | 0.50 | 0.50 | 1.60 | 4.33 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 5.17 |
| Dispatch | 4.33 |
| Overall L1 | 5.17 |
| all | 36% |
| load | 40% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 33% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 50% |
| all | 35% |
| load | 40% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 14% |
| all | 13% |
| load | 14% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 8% |
| all | 14% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 6% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 18% |
| all | 13% |
| load | 14% |
| store | 6% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 11% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV %R8D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| VCVTSD2SS %XMM0,%XMM0,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | scal (12.5%) |
| ADD %EDX,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV 0x80(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| VMOVSS %XMM0,(%RCX,%RDI,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| LEA 0x1(%R8),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| CMP 0x198(%RSP),%R8 | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | scal (12.5%) |
| MOV %RSI,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| JE 4056d0 <main+0x22b0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| VXORPS %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| CMPL $0x8,0xc8(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | scal (6.3%) |
| MOV 0x20(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV 0x68(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| VMOVDQU 0x300(%RSP),%YMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VPMOVSXBD 0x99c8(%RIP),%YMM6 | 2 | 0 | 0 | 0.33 | 0.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 | vect (12.5%) |
| VPMOVSXBD 0x99c7(%RIP),%YMM7 | 2 | 0 | 0 | 0.33 | 0.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 | vect (12.5%) |
| VPBROADCASTQ 0x99c6(%RIP),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 | scal (12.5%) |
| VPMOVSXBQ 0x9989(%RIP),%YMM9 | 2 | 0 | 0 | 0.33 | 0.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 | vect (6.3%) |
| VPBROADCASTD 0x997c(%RIP),%YMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 | scal (6.3%) |
| JB 4058c6 <main+0x24a6> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| MOV %R8D,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| MOV %EAX,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| MOV 0x188(%RSP),%R10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV 0x1a0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| CMP $0x6,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| JA 40574c <main+0x232c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
