| Loop Id: 31 | Module: attention-gnr-256 | Source: attention_v2.cpp:237-238 | Coverage: 0.27% |
|---|
| Loop Id: 31 | Module: attention-gnr-256 | Source: attention_v2.cpp:237-238 | Coverage: 0.27% |
|---|
0x406bf0 VPBROADCASTQ %RDX,%YMM1 |
0x406bf6 VPADDQ %YMM1,%YMM12,%YMM2 |
0x406bfa VPADDQ %YMM1,%YMM13,%YMM3 |
0x406bfe VPADDQ %YMM1,%YMM10,%YMM4 |
0x406c02 VPMULLQ %YMM4,%YMM9,%YMM4 |
0x406c08 VPMULLQ %YMM3,%YMM9,%YMM3 |
0x406c0e VPMULLQ %YMM2,%YMM9,%YMM2 |
0x406c14 VPADDQ %YMM1,%YMM11,%YMM1 |
0x406c18 VPMULLQ %YMM1,%YMM9,%YMM1 |
0x406c1e VPADDQ %YMM0,%YMM1,%YMM1 |
0x406c22 VPADDQ %YMM0,%YMM2,%YMM2 |
0x406c26 VPADDQ %YMM0,%YMM3,%YMM3 |
0x406c2a VPADDQ %YMM0,%YMM4,%YMM4 |
0x406c2e VMOVUPS (%RAX,%RDX,4),%XMM5 [2] |
0x406c33 VMOVUPS 0x10(%RAX,%RDX,4),%XMM6 [2] |
0x406c39 VMOVUPS 0x20(%RAX,%RDX,4),%XMM7 [2] |
0x406c3f VMOVUPS 0x30(%RAX,%RDX,4),%XMM8 [2] |
0x406c45 KXNORW %K0,%K0,%K1 |
0x406c49 VSCATTERQPS %XMM5,(%RSI,%YMM4,4){%K1} [1] |
0x406c50 KXNORW %K0,%K0,%K1 |
0x406c54 VSCATTERQPS %XMM6,(%RSI,%YMM3,4){%K1} [1] |
0x406c5b KXNORW %K0,%K0,%K1 |
0x406c5f VSCATTERQPS %XMM7,(%RSI,%YMM2,4){%K1} [1] |
0x406c66 KXNORW %K0,%K0,%K1 |
0x406c6a VSCATTERQPS %XMM8,(%RSI,%YMM1,4){%K1} [1] |
0x406c71 ADD $0x10,%RDX |
0x406c75 CMP %R9,%RDX |
0x406c78 JB 406bf0 |
/home/eoseret/llm-attention/attention_v2.cpp: 237 - 238 |
-------------------------------------------------------------------------------- |
237: for (int j = 0; j < dim; ++j)// vectorized |
238: h_KT[j * context_size + i] = h_K[i * dim + j]; |
| Coverage (%) | Name | Source Location | Module |
|---|
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.05 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 3.11 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.21 |
| Bottlenecks | micro-operation queue, |
| Function | main |
| Source | attention_v2.cpp:237-238 |
| Source loop unroll info | unrolled by 32 |
| Source loop unroll confidence level | high |
| Unroll/vectorization loop type | main |
| Unroll factor | 32 |
| CQA cycles | 14.50 |
| CQA cycles if no scalar integer | 13.83 |
| CQA cycles if FP arith vectorized | 14.50 |
| CQA cycles if fully vectorized | 4.66 |
| Front-end cycles | 14.50 |
| P0 cycles | 12.00 |
| P1 cycles | 12.00 |
| P2 cycles | 1.33 |
| P3 cycles | 1.33 |
| P4 cycles | 8.00 |
| P5 cycles | 9.00 |
| P6 cycles | 2.60 |
| P7 cycles | 8.00 |
| P8 cycles | 8.00 |
| P9 cycles | 8.00 |
| P10 cycles | 2.40 |
| P11 cycles | 1.33 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 28.00 |
| Nb uops | 87.00 |
| Nb loads | 4.00 |
| Nb stores | 4.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 13.24 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 64.00 |
| Bytes stored | 128.00 |
| Stride 0 | 0.00 |
| Stride 1 | 1.00 |
| Stride n | 0.00 |
| Stride unknown | 1.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 95.24 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 38.69 |
| Vector-efficiency ratio load | 25.00 |
| Vector-efficiency ratio store | 25.00 |
| Vector-efficiency ratio mul | 50.00 |
| Vector-efficiency ratio add_sub | 50.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 12.50 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.05 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 3.11 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.21 |
| Bottlenecks | micro-operation queue, |
| Function | main |
| Source | attention_v2.cpp:237-238 |
| Source loop unroll info | unrolled by 32 |
| Source loop unroll confidence level | high |
| Unroll/vectorization loop type | main |
| Unroll factor | 32 |
| CQA cycles | 14.50 |
| CQA cycles if no scalar integer | 13.83 |
| CQA cycles if FP arith vectorized | 14.50 |
| CQA cycles if fully vectorized | 4.66 |
| Front-end cycles | 14.50 |
| P0 cycles | 12.00 |
| P1 cycles | 12.00 |
| P2 cycles | 1.33 |
| P3 cycles | 1.33 |
| P4 cycles | 8.00 |
| P5 cycles | 9.00 |
| P6 cycles | 2.60 |
| P7 cycles | 8.00 |
| P8 cycles | 8.00 |
| P9 cycles | 8.00 |
| P10 cycles | 2.40 |
| P11 cycles | 1.33 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 28.00 |
| Nb uops | 87.00 |
| Nb loads | 4.00 |
| Nb stores | 4.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 13.24 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 64.00 |
| Bytes stored | 128.00 |
| Stride 0 | 0.00 |
| Stride 1 | 1.00 |
| Stride n | 0.00 |
| Stride unknown | 1.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 95.24 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 38.69 |
| Vector-efficiency ratio load | 25.00 |
| Vector-efficiency ratio store | 25.00 |
| Vector-efficiency ratio mul | 50.00 |
| Vector-efficiency ratio add_sub | 50.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 12.50 |
| Path / |
| Function | main |
| Source file and lines | attention_v2.cpp:237-238 |
| Module | attention-gnr-256 |
| nb instructions | 28 |
| nb uops | 87 |
| loop length | 142 |
| used x86 registers | 4 |
| used mmx registers | 0 |
| used xmm registers | 4 |
| used ymm registers | 10 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 14.50 cycles |
| front end | 14.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 12.00 | 12.00 | 1.33 | 1.33 | 8.00 | 9.00 | 2.60 | 8.00 | 8.00 | 8.00 | 2.40 | 1.33 |
| cycles | 12.00 | 12.00 | 1.33 | 1.33 | 8.00 | 9.00 | 2.60 | 8.00 | 8.00 | 8.00 | 2.40 | 1.33 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 14.50 |
| Dispatch | 12.00 |
| Data deps. | 1.00 |
| Overall L1 | 14.50 |
| all | 92% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 95% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 47% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 50% |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 25% |
| load | 25% |
| store | 25% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 38% |
| load | 25% |
| store | 25% |
| mul | 50% |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 12% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VPBROADCASTQ %RDX,%YMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | scal (12.5%) |
| VPADDQ %YMM1,%YMM12,%YMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPADDQ %YMM1,%YMM13,%YMM3 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPADDQ %YMM1,%YMM10,%YMM4 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPMULLQ %YMM4,%YMM9,%YMM4 | 5 | 1.50 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 | vect (50.0%) |
| VPMULLQ %YMM3,%YMM9,%YMM3 | 5 | 1.50 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 | vect (50.0%) |
| VPMULLQ %YMM2,%YMM9,%YMM2 | 5 | 1.50 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 | vect (50.0%) |
| VPADDQ %YMM1,%YMM11,%YMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPMULLQ %YMM1,%YMM9,%YMM1 | 5 | 1.50 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 | vect (50.0%) |
| VPADDQ %YMM0,%YMM1,%YMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPADDQ %YMM0,%YMM2,%YMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPADDQ %YMM0,%YMM3,%YMM3 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPADDQ %YMM0,%YMM4,%YMM4 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VMOVUPS (%RAX,%RDX,4),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (25.0%) |
| VMOVUPS 0x10(%RAX,%RDX,4),%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (25.0%) |
| VMOVUPS 0x20(%RAX,%RDX,4),%XMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (25.0%) |
| VMOVUPS 0x30(%RAX,%RDX,4),%XMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (25.0%) |
| KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | N/A |
| VSCATTERQPS %XMM5,(%RSI,%YMM4,4){%K1} | 12 | 1.70 | 0.70 | 0 | 0 | 2 | 0.20 | 0.20 | 2 | 2 | 2 | 0.20 | 0 | 2-12 | 5 | vect (25.0%) |
| KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | N/A |
| VSCATTERQPS %XMM6,(%RSI,%YMM3,4){%K1} | 12 | 1.70 | 0.70 | 0 | 0 | 2 | 0.20 | 0.20 | 2 | 2 | 2 | 0.20 | 0 | 2-12 | 5 | vect (25.0%) |
| KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | N/A |
| VSCATTERQPS %XMM7,(%RSI,%YMM2,4){%K1} | 12 | 1.70 | 0.70 | 0 | 0 | 2 | 0.20 | 0.20 | 2 | 2 | 2 | 0.20 | 0 | 2-12 | 5 | vect (25.0%) |
| KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | N/A |
| VSCATTERQPS %XMM8,(%RSI,%YMM1,4){%K1} | 12 | 1.70 | 0.70 | 0 | 0 | 2 | 0.20 | 0.20 | 2 | 2 | 2 | 0.20 | 0 | 2-12 | 5 | vect (25.0%) |
| ADD $0x10,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| CMP %R9,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| JB 406bf0 <main+0x37d0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| Function | main |
| Source file and lines | attention_v2.cpp:237-238 |
| Module | attention-gnr-256 |
| nb instructions | 28 |
| nb uops | 87 |
| loop length | 142 |
| used x86 registers | 4 |
| used mmx registers | 0 |
| used xmm registers | 4 |
| used ymm registers | 10 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 14.50 cycles |
| front end | 14.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 12.00 | 12.00 | 1.33 | 1.33 | 8.00 | 9.00 | 2.60 | 8.00 | 8.00 | 8.00 | 2.40 | 1.33 |
| cycles | 12.00 | 12.00 | 1.33 | 1.33 | 8.00 | 9.00 | 2.60 | 8.00 | 8.00 | 8.00 | 2.40 | 1.33 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 14.50 |
| Dispatch | 12.00 |
| Data deps. | 1.00 |
| Overall L1 | 14.50 |
| all | 92% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 95% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 47% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 50% |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 25% |
| load | 25% |
| store | 25% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 38% |
| load | 25% |
| store | 25% |
| mul | 50% |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 12% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VPBROADCASTQ %RDX,%YMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | scal (12.5%) |
| VPADDQ %YMM1,%YMM12,%YMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPADDQ %YMM1,%YMM13,%YMM3 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPADDQ %YMM1,%YMM10,%YMM4 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPMULLQ %YMM4,%YMM9,%YMM4 | 5 | 1.50 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 | vect (50.0%) |
| VPMULLQ %YMM3,%YMM9,%YMM3 | 5 | 1.50 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 | vect (50.0%) |
| VPMULLQ %YMM2,%YMM9,%YMM2 | 5 | 1.50 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 | vect (50.0%) |
| VPADDQ %YMM1,%YMM11,%YMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPMULLQ %YMM1,%YMM9,%YMM1 | 5 | 1.50 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 | vect (50.0%) |
| VPADDQ %YMM0,%YMM1,%YMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPADDQ %YMM0,%YMM2,%YMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPADDQ %YMM0,%YMM3,%YMM3 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPADDQ %YMM0,%YMM4,%YMM4 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VMOVUPS (%RAX,%RDX,4),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (25.0%) |
| VMOVUPS 0x10(%RAX,%RDX,4),%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (25.0%) |
| VMOVUPS 0x20(%RAX,%RDX,4),%XMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (25.0%) |
| VMOVUPS 0x30(%RAX,%RDX,4),%XMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (25.0%) |
| KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | N/A |
| VSCATTERQPS %XMM5,(%RSI,%YMM4,4){%K1} | 12 | 1.70 | 0.70 | 0 | 0 | 2 | 0.20 | 0.20 | 2 | 2 | 2 | 0.20 | 0 | 2-12 | 5 | vect (25.0%) |
| KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | N/A |
| VSCATTERQPS %XMM6,(%RSI,%YMM3,4){%K1} | 12 | 1.70 | 0.70 | 0 | 0 | 2 | 0.20 | 0.20 | 2 | 2 | 2 | 0.20 | 0 | 2-12 | 5 | vect (25.0%) |
| KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | N/A |
| VSCATTERQPS %XMM7,(%RSI,%YMM2,4){%K1} | 12 | 1.70 | 0.70 | 0 | 0 | 2 | 0.20 | 0.20 | 2 | 2 | 2 | 0.20 | 0 | 2-12 | 5 | vect (25.0%) |
| KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | N/A |
| VSCATTERQPS %XMM8,(%RSI,%YMM1,4){%K1} | 12 | 1.70 | 0.70 | 0 | 0 | 2 | 0.20 | 0.20 | 2 | 2 | 2 | 0.20 | 0 | 2-12 | 5 | vect (25.0%) |
| ADD $0x10,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| CMP %R9,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| JB 406bf0 <main+0x37d0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
