OV - attention-gnr-256 - Loop 31

	Loop Id: 31	Module: attention-gnr-256	Source: attention_v2.cpp:237-238	Coverage: 0.27%

0x406bf0 VPBROADCASTQ	%RDX,%YMM1

0x406bf6 VPADDQ	%YMM1,%YMM12,%YMM2

0x406bfa VPADDQ	%YMM1,%YMM13,%YMM3

0x406bfe VPADDQ	%YMM1,%YMM10,%YMM4

0x406c02 VPMULLQ	%YMM4,%YMM9,%YMM4

0x406c08 VPMULLQ	%YMM3,%YMM9,%YMM3

0x406c0e VPMULLQ	%YMM2,%YMM9,%YMM2

0x406c14 VPADDQ	%YMM1,%YMM11,%YMM1

0x406c18 VPMULLQ	%YMM1,%YMM9,%YMM1

0x406c1e VPADDQ	%YMM0,%YMM1,%YMM1

0x406c22 VPADDQ	%YMM0,%YMM2,%YMM2

0x406c26 VPADDQ	%YMM0,%YMM3,%YMM3

0x406c2a VPADDQ	%YMM0,%YMM4,%YMM4

0x406c2e VMOVUPS	(%RAX,%RDX,4),%XMM5    [2]

0x406c33 VMOVUPS	0x10(%RAX,%RDX,4),%XMM6    [2]

0x406c39 VMOVUPS	0x20(%RAX,%RDX,4),%XMM7    [2]

0x406c3f VMOVUPS	0x30(%RAX,%RDX,4),%XMM8    [2]

0x406c45 KXNORW	%K0,%K0,%K1

0x406c49 VSCATTERQPS	%XMM5,(%RSI,%YMM4,4){%K1}    [1]

0x406c50 KXNORW	%K0,%K0,%K1

0x406c54 VSCATTERQPS	%XMM6,(%RSI,%YMM3,4){%K1}    [1]

0x406c5b KXNORW	%K0,%K0,%K1

0x406c5f VSCATTERQPS	%XMM7,(%RSI,%YMM2,4){%K1}    [1]

0x406c66 KXNORW	%K0,%K0,%K1

0x406c6a VSCATTERQPS	%XMM8,(%RSI,%YMM1,4){%K1}    [1]

0x406c71 ADD	$0x10,%RDX

0x406c75 CMP	%R9,%RDX

0x406c78 JB	406bf0

/home/eoseret/llm-attention/attention_v2.cpp: 237 - 238

--------------------------------------------------------------------------------

237:          for (int j = 0; j < dim; ++j)// vectorized

238:             h_KT[j * context_size + i] = h_K[i * dim + j];

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.05
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.11
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:237-238
Source loop unroll info	unrolled by 32
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	32
CQA cycles	14.50
CQA cycles if no scalar integer	13.83
CQA cycles if FP arith vectorized	14.50
CQA cycles if fully vectorized	4.66
Front-end cycles	14.50
P0 cycles	12.00
P1 cycles	12.00
P2 cycles	1.33
P3 cycles	1.33
P4 cycles	8.00
P5 cycles	9.00
P6 cycles	2.60
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	2.40
P11 cycles	1.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	87.00
Nb loads	4.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.24
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	128.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	95.24
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	38.69
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.05
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.11
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:237-238
Source loop unroll info	unrolled by 32
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	32
CQA cycles	14.50
CQA cycles if no scalar integer	13.83
CQA cycles if FP arith vectorized	14.50
CQA cycles if fully vectorized	4.66
Front-end cycles	14.50
P0 cycles	12.00
P1 cycles	12.00
P2 cycles	1.33
P3 cycles	1.33
P4 cycles	8.00
P5 cycles	9.00
P6 cycles	2.60
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	2.40
P11 cycles	1.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	87.00
Nb loads	4.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	13.24
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	128.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	95.24
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	38.69
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:237-238
Module	attention-gnr-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:237-238.

It is main loop of related source loop which is unrolled by 32 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 38% of vector register length is used (average across all SSE/AVX instructions).

Details

95% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPMULLQ: 4 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:238
- /home/eoseret/llm-attention/attention_v2.cpp:238
- /home/eoseret/llm-attention/attention_v2.cpp:238
- /home/eoseret/llm-attention/attention_v2.cpp:238
VSCATTERQPS: 4 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:238
- /home/eoseret/llm-attention/attention_v2.cpp:238
- /home/eoseret/llm-attention/attention_v2.cpp:238
- /home/eoseret/llm-attention/attention_v2.cpp:238

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VSCATTERQPS: 4 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:238
- /home/eoseret/llm-attention/attention_v2.cpp:238
- /home/eoseret/llm-attention/attention_v2.cpp:238
- /home/eoseret/llm-attention/attention_v2.cpp:238

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 128 bytes.

General properties

nb instructions	28
nb uops	87
loop length	142
used x86 registers	4
used mmx registers	0
used xmm registers	4
used ymm registers	10
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	14.50 cycles
front end	14.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	12.00	12.00	1.33	1.33	8.00	9.00	2.60	8.00	8.00	8.00	2.40	1.33
cycles	12.00	12.00	1.33	1.33	8.00	9.00	2.60	8.00	8.00	8.00	2.40	1.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	14.50
Dispatch	12.00
Data deps.	1.00
Overall L1	14.50

Vectorization ratios

INT

all	92%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	95%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	47%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	38%
load	25%
store	25%
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.50 cycles. At this rate:

2% of peak load performance is reached (4.41 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.83 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 14.50 to 12.00 cycles (1.21x speedup).

ASM code

In the binary file, the address of the loop is: 406bf0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VPBROADCASTQ %RDX,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPADDQ %YMM1,%YMM12,%YMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPADDQ %YMM1,%YMM13,%YMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPADDQ %YMM1,%YMM10,%YMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPMULLQ %YMM4,%YMM9,%YMM4	5	1.50	1.50	0	0	0	0	0	0	0	0	0	0	15	1.50	vect (50.0%)
VPMULLQ %YMM3,%YMM9,%YMM3	5	1.50	1.50	0	0	0	0	0	0	0	0	0	0	15	1.50	vect (50.0%)
VPMULLQ %YMM2,%YMM9,%YMM2	5	1.50	1.50	0	0	0	0	0	0	0	0	0	0	15	1.50	vect (50.0%)
VPADDQ %YMM1,%YMM11,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPMULLQ %YMM1,%YMM9,%YMM1	5	1.50	1.50	0	0	0	0	0	0	0	0	0	0	15	1.50	vect (50.0%)
VPADDQ %YMM0,%YMM1,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPADDQ %YMM0,%YMM2,%YMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPADDQ %YMM0,%YMM3,%YMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPADDQ %YMM0,%YMM4,%YMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VMOVUPS (%RAX,%RDX,4),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPS 0x10(%RAX,%RDX,4),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPS 0x20(%RAX,%RDX,4),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPS 0x30(%RAX,%RDX,4),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VSCATTERQPS %XMM5,(%RSI,%YMM4,4){%K1}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VSCATTERQPS %XMM6,(%RSI,%YMM3,4){%K1}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VSCATTERQPS %XMM7,(%RSI,%YMM2,4){%K1}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VSCATTERQPS %XMM8,(%RSI,%YMM1,4){%K1}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (25.0%)
ADD $0x10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R9,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JB 406bf0 <main+0x37d0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:237-238
Module	attention-gnr-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:237-238.

It is main loop of related source loop which is unrolled by 32 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. Only 38% of vector register length is used (average across all SSE/AVX instructions).

Details

95% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPMULLQ: 4 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:238
- /home/eoseret/llm-attention/attention_v2.cpp:238
- /home/eoseret/llm-attention/attention_v2.cpp:238
- /home/eoseret/llm-attention/attention_v2.cpp:238
VSCATTERQPS: 4 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:238
- /home/eoseret/llm-attention/attention_v2.cpp:238
- /home/eoseret/llm-attention/attention_v2.cpp:238
- /home/eoseret/llm-attention/attention_v2.cpp:238

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VSCATTERQPS: 4 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:238
- /home/eoseret/llm-attention/attention_v2.cpp:238
- /home/eoseret/llm-attention/attention_v2.cpp:238
- /home/eoseret/llm-attention/attention_v2.cpp:238

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 128 bytes.

General properties

nb instructions	28
nb uops	87
loop length	142
used x86 registers	4
used mmx registers	0
used xmm registers	4
used ymm registers	10
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	14.50 cycles
front end	14.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	12.00	12.00	1.33	1.33	8.00	9.00	2.60	8.00	8.00	8.00	2.40	1.33
cycles	12.00	12.00	1.33	1.33	8.00	9.00	2.60	8.00	8.00	8.00	2.40	1.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	14.50
Dispatch	12.00
Data deps.	1.00
Overall L1	14.50

Vectorization ratios

INT

all	92%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	95%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	47%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	38%
load	25%
store	25%
mul	50%
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.50 cycles. At this rate:

2% of peak load performance is reached (4.41 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.83 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 406bf0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VPBROADCASTQ %RDX,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPADDQ %YMM1,%YMM12,%YMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPADDQ %YMM1,%YMM13,%YMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPADDQ %YMM1,%YMM10,%YMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPMULLQ %YMM4,%YMM9,%YMM4	5	1.50	1.50	0	0	0	0	0	0	0	0	0	0	15	1.50	vect (50.0%)
VPMULLQ %YMM3,%YMM9,%YMM3	5	1.50	1.50	0	0	0	0	0	0	0	0	0	0	15	1.50	vect (50.0%)
VPMULLQ %YMM2,%YMM9,%YMM2	5	1.50	1.50	0	0	0	0	0	0	0	0	0	0	15	1.50	vect (50.0%)
VPADDQ %YMM1,%YMM11,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPMULLQ %YMM1,%YMM9,%YMM1	5	1.50	1.50	0	0	0	0	0	0	0	0	0	0	15	1.50	vect (50.0%)
VPADDQ %YMM0,%YMM1,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPADDQ %YMM0,%YMM2,%YMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPADDQ %YMM0,%YMM3,%YMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPADDQ %YMM0,%YMM4,%YMM4	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VMOVUPS (%RAX,%RDX,4),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPS 0x10(%RAX,%RDX,4),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPS 0x20(%RAX,%RDX,4),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVUPS 0x30(%RAX,%RDX,4),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VSCATTERQPS %XMM5,(%RSI,%YMM4,4){%K1}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VSCATTERQPS %XMM6,(%RSI,%YMM3,4){%K1}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VSCATTERQPS %XMM7,(%RSI,%YMM2,4){%K1}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (25.0%)
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
VSCATTERQPS %XMM8,(%RSI,%YMM1,4){%K1}	12	1.70	0.70	0	0	2	0.20	0.20	2	2	2	0.20	0	2-12	5	vect (25.0%)
ADD $0x10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R9,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JB 406bf0 <main+0x37d0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code