OV - attention-gnr-256 - Loop 28

	Loop Id: 28	Module: attention-gnr-256	Source: attention_v2.cpp:30-31	Coverage: 28.44%

0x405d10 LEA	0x5(%R8),%ECX

0x405d14 LEA	(%RSI,%RDI,1),%EDX

0x405d17 VPBROADCASTD	%R8D,%XMM1

0x405d1d VPADDD	%YMM1,%YMM8,%YMM2

0x405d21 VPERMT2D	%YMM1,%YMM9,%YMM2

0x405d27 VPBROADCASTD	%ECX,%YMM3

0x405d2d VPBLENDD	$0x20,%YMM3,%YMM2,%YMM2

0x405d33 VPADDD	%YMM1,%YMM10,%YMM1

0x405d37 VPERMT2Q	%YMM1,%YMM11,%YMM2

0x405d3d VPSUBD	%YMM12,%YMM2,%YMM1

0x405d42 LEA	(%R10,%R14,1),%RCX

0x405d46 KXNORW	%K0,%K0,%K1

0x405d4a VPXOR	%XMM2,%XMM2,%XMM2

0x405d4e VGATHERDPS	(%RCX,%YMM1,4),%YMM2{%K1}    [2]

0x405d55 VCVTPS2PD	%XMM2,%YMM1

0x405d59 VPBROADCASTD	%EDI,%XMM3

0x405d5f VPADDD	%YMM7,%YMM3,%YMM4

0x405d63 VPERMT2D	%YMM3,%YMM9,%YMM4

0x405d69 VPBROADCASTD	%EDX,%YMM5

0x405d6f VPBLENDD	$0x20,%YMM5,%YMM4,%YMM4

0x405d75 VPADDD	%YMM3,%YMM6,%YMM3

0x405d79 VPERMT2Q	%YMM3,%YMM11,%YMM4

0x405d7f VPSUBD	%YMM12,%YMM4,%YMM3

0x405d84 LEA	(%RBX,%R14,1),%RCX

0x405d88 KXNORW	%K0,%K0,%K1

0x405d8c VPXOR	%XMM4,%XMM4,%XMM4

0x405d90 VGATHERDPS	(%RCX,%YMM3,4),%YMM4{%K1}    [1]

0x405d97 VEXTRACTF128	$0x1,%YMM2,%XMM2

0x405d9d VCVTPS2PD	%XMM2,%YMM2

0x405da1 VCVTPS2PD	%XMM4,%YMM3

0x405da5 VEXTRACTF128	$0x1,%YMM4,%XMM4

0x405dab VCVTPS2PD	%XMM4,%YMM4

0x405daf VMULPD	%YMM2,%YMM4,%YMM2

0x405db3 VFMADD231PD	%YMM3,%YMM1,%YMM2

0x405db8 VEXTRACTF128	$0x1,%YMM2,%XMM1

0x405dbe VADDPD	%XMM1,%XMM2,%XMM1

0x405dc2 VSHUFPD	$0x1,%XMM1,%XMM1,%XMM2

0x405dc7 VADDSD	%XMM2,%XMM1,%XMM1

0x405dcb VADDSD	%XMM1,%XMM0,%XMM0

0x405dcf ADD	$0x8,%R8D

0x405dd3 ADD	%EAX,%EDI

0x405dd5 DEC	%R11

0x405dd8 JNE	405d10

/home/eoseret/llm-attention/attention_v2.cpp: 30 - 31

--------------------------------------------------------------------------------

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.21
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.15
Bottlenecks	P5,
Function	main
Source	attention_v2.cpp:30-31
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.00
CQA cycles if no scalar integer	15.00
CQA cycles if FP arith vectorized	15.00
CQA cycles if fully vectorized	4.67
Front-end cycles	9.00
P0 cycles	13.00
P1 cycles	13.00
P2 cycles	5.33
P3 cycles	5.33
P4 cycles	0.00
P5 cycles	15.00
P6 cycles	2.60
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	2.40
P11 cycles	5.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	43.00
Nb uops	54.00
Nb loads	2.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	1.07
Nb FLOP add-sub	4.00
Nb FLOP mul	4.00
Nb FLOP fma	4.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.27
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	81.82
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	77.78
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	81.82
Vector-efficiency ratio all	34.09
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	38.89
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	30.68

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.21
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.15
Bottlenecks	P5,
Function	main
Source	attention_v2.cpp:30-31
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	15.00
CQA cycles if no scalar integer	15.00
CQA cycles if FP arith vectorized	15.00
CQA cycles if fully vectorized	4.67
Front-end cycles	9.00
P0 cycles	13.00
P1 cycles	13.00
P2 cycles	5.33
P3 cycles	5.33
P4 cycles	0.00
P5 cycles	15.00
P6 cycles	2.60
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	2.40
P11 cycles	5.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	43.00
Nb uops	54.00
Nb loads	2.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	1.07
Nb FLOP add-sub	4.00
Nb FLOP mul	4.00
Nb FLOP fma	4.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.27
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	2.00
Vectorization ratio all	81.82
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	77.78
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	81.82
Vector-efficiency ratio all	34.09
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	38.89
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	30.68

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:30-31
Module	attention-gnr-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:30-31.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 34% of vector register length is used (average across all SSE/AVX instructions).

Details

81% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

77% of SSE/AVX addition or subtraction instructions are used in vector version.
81% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 15.00 to 13.00 cycles (1.15x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 4 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
VGATHERDPS: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 3 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 3 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 4 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 2 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction (4 inside FMA instructions)
8: multiply (4 inside FMA instructions)

The binary loop is loading 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	43
nb uops	54
loop length	206
used x86 registers	10
used mmx registers	0
used xmm registers	5
used ymm registers	12
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	3.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.00 cycles
front end	9.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	13.00	13.00	5.33	5.33	0.00	15.00	2.60	0.00	0.00	0.00	2.40	5.33
cycles	13.00	13.00	5.33	5.33	0.00	15.00	2.60	0.00	0.00	0.00	2.40	5.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	9.00
Dispatch	15.00
Data deps.	3.00
Overall L1	15.00

Vectorization ratios

INT

all	77%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	66%

all	86%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	33%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	81%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	77%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	81%

Vector efficiency ratios

INT

all	37%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	31%

all	30%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	16%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

INT+FP

all	34%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	38%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.00 cycles. At this rate:

2% of peak load performance is reached (4.27 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 405d10

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
LEA 0x5(%R8),%ECX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
LEA (%RSI,%RDI,1),%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VPBROADCASTD %R8D,%XMM1	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
VPADDD %YMM1,%YMM8,%YMM2	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPERMT2D %YMM1,%YMM9,%YMM2	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VPBROADCASTD %ECX,%YMM3	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
VPBLENDD $0x20,%YMM3,%YMM2,%YMM2	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPADDD %YMM1,%YMM10,%YMM1	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPERMT2Q %YMM1,%YMM11,%YMM2	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VPSUBD %YMM12,%YMM2,%YMM1	1	0.33	0.33	0	0	0.33	0	0	0	0-1	0.33	vect (50.0%)
LEA (%R10,%R14,1),%RCX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VPXOR %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VGATHERDPS (%RCX,%YMM1,4),%YMM2{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VCVTPS2PD %XMM2,%YMM1	2	0.50	0.50	0	0	1	0	0	0	7	1	vect (25.0%)
VPBROADCASTD %EDI,%XMM3	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
VPADDD %YMM7,%YMM3,%YMM4	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPERMT2D %YMM3,%YMM9,%YMM4	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VPBROADCASTD %EDX,%YMM5	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
VPBLENDD $0x20,%YMM5,%YMM4,%YMM4	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPADDD %YMM3,%YMM6,%YMM3	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPERMT2Q %YMM3,%YMM11,%YMM4	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VPSUBD %YMM12,%YMM4,%YMM3	1	0.33	0.33	0	0	0.33	0	0	0	0-1	0.33	vect (50.0%)
LEA (%RBX,%R14,1),%RCX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VPXOR %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VGATHERDPS (%RCX,%YMM3,4),%YMM4{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VEXTRACTF128 $0x1,%YMM2,%XMM2	1	0	0	0	0	1	0	0	0	3	1	vect (25.0%)
VCVTPS2PD %XMM2,%YMM2	2	0.50	0.50	0	0	1	0	0	0	7	1	vect (25.0%)
VCVTPS2PD %XMM4,%YMM3	2	0.50	0.50	0	0	1	0	0	0	7	1	vect (25.0%)
VEXTRACTF128 $0x1,%YMM4,%XMM4	1	0	0	0	0	1	0	0	0	3	1	vect (25.0%)
VCVTPS2PD %XMM4,%YMM4	2	0.50	0.50	0	0	1	0	0	0	7	1	vect (25.0%)
VMULPD %YMM2,%YMM4,%YMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM3,%YMM1,%YMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM2,%XMM1	1	0	0	0	0	1	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM2,%XMM1	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2	1	0	0.50	0	0	0.50	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM2,%XMM1,%XMM1	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
ADD $0x8,%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
ADD %EAX,%EDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
DEC %R11	1	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 405d10 <main+0x28f0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:30-31
Module	attention-gnr-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:30-31.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 34% of vector register length is used (average across all SSE/AVX instructions).

Details

81% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

77% of SSE/AVX addition or subtraction instructions are used in vector version.
81% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTPS2PD: 4 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
VGATHERDPS: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 3 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 3 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPS: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTPS2PD (FP32 to FP64, SIMD): 4 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31
- /home/eoseret/llm-attention/attention_v2.cpp:31

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 16 FP arithmetical operations:

8: addition or subtraction (4 inside FMA instructions)
8: multiply (4 inside FMA instructions)

The binary loop is loading 64 bytes (8 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	43
nb uops	54
loop length	206
used x86 registers	10
used mmx registers	0
used xmm registers	5
used ymm registers	12
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	3.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.00 cycles
front end	9.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	13.00	13.00	5.33	5.33	0.00	15.00	2.60	0.00	0.00	0.00	2.40	5.33
cycles	13.00	13.00	5.33	5.33	0.00	15.00	2.60	0.00	0.00	0.00	2.40	5.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	9.00
Dispatch	15.00
Data deps.	3.00
Overall L1	15.00

Vectorization ratios

INT

all	77%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	66%

all	86%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	33%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	81%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	77%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	81%

Vector efficiency ratios

INT

all	37%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	31%

all	30%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	16%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

INT+FP

all	34%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	38%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	30%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 15.00 cycles. At this rate:

2% of peak load performance is reached (4.27 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 405d10

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
LEA 0x5(%R8),%ECX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
LEA (%RSI,%RDI,1),%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VPBROADCASTD %R8D,%XMM1	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
VPADDD %YMM1,%YMM8,%YMM2	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPERMT2D %YMM1,%YMM9,%YMM2	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VPBROADCASTD %ECX,%YMM3	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
VPBLENDD $0x20,%YMM3,%YMM2,%YMM2	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPADDD %YMM1,%YMM10,%YMM1	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPERMT2Q %YMM1,%YMM11,%YMM2	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VPSUBD %YMM12,%YMM2,%YMM1	1	0.33	0.33	0	0	0.33	0	0	0	0-1	0.33	vect (50.0%)
LEA (%R10,%R14,1),%RCX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VPXOR %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VGATHERDPS (%RCX,%YMM1,4),%YMM2{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VCVTPS2PD %XMM2,%YMM1	2	0.50	0.50	0	0	1	0	0	0	7	1	vect (25.0%)
VPBROADCASTD %EDI,%XMM3	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
VPADDD %YMM7,%YMM3,%YMM4	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPERMT2D %YMM3,%YMM9,%YMM4	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VPBROADCASTD %EDX,%YMM5	1	0	0	0	0	1	0	0	0	3	1	scal (6.3%)
VPBLENDD $0x20,%YMM5,%YMM4,%YMM4	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPADDD %YMM3,%YMM6,%YMM3	1	0.33	0.33	0	0	0.33	0	0	0	1	0.33	vect (50.0%)
VPERMT2Q %YMM3,%YMM11,%YMM4	1	0	0	0	0	1	0	0	0	3	1	vect (50.0%)
VPSUBD %YMM12,%YMM4,%YMM3	1	0.33	0.33	0	0	0.33	0	0	0	0-1	0.33	vect (50.0%)
LEA (%RBX,%R14,1),%RCX	1	0	0	0	0	0	0	0	0	0	0.17	N/A
KXNORW %K0,%K0,%K1	1	1	0	0	0	0	0	0	0	1	1	N/A
VPXOR %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VGATHERDPS (%RCX,%YMM3,4),%YMM4{%K1}	5	1	1	2.67	2.67	1	0	0	2.67	29	3	vect (50.0%)
VEXTRACTF128 $0x1,%YMM2,%XMM2	1	0	0	0	0	1	0	0	0	3	1	vect (25.0%)
VCVTPS2PD %XMM2,%YMM2	2	0.50	0.50	0	0	1	0	0	0	7	1	vect (25.0%)
VCVTPS2PD %XMM4,%YMM3	2	0.50	0.50	0	0	1	0	0	0	7	1	vect (25.0%)
VEXTRACTF128 $0x1,%YMM4,%XMM4	1	0	0	0	0	1	0	0	0	3	1	vect (25.0%)
VCVTPS2PD %XMM4,%YMM4	2	0.50	0.50	0	0	1	0	0	0	7	1	vect (25.0%)
VMULPD %YMM2,%YMM4,%YMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM3,%YMM1,%YMM2	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM2,%XMM1	1	0	0	0	0	1	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM2,%XMM1	1	0	0.50	0	0	0.50	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM1,%XMM1,%XMM2	1	0	0.50	0	0	0.50	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM2,%XMM1,%XMM1	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0.50	0	0	0	3	0.50	scal (12.5%)
ADD $0x8,%R8D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
ADD %EAX,%EDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
DEC %R11	1	0	0	0	0	0	0	0	0	1	0.17	N/A
JNE 405d10 <main+0x28f0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code