OV - attention-gnr-256 - Loop 27

	Loop Id: 27	Module: attention-gnr-256	Source: attention_v2.cpp:27-33	Coverage: 5.87%

0x405c52 MOV	%R9D,%R8D

0x405c55 MOV	0x50(%RSP),%RBX

0x405c5a NOPW	(%RAX,%RAX,1)

0x405c60 VCVTSD2SS	%XMM0,%XMM0,%XMM0

0x405c64 ADD	0x28(%RSP),%R8D

0x405c69 VMULSS	0x24c(%RSP),%XMM0,%XMM0

0x405c72 VMOVSS	%XMM0,(%RBX,%R8,4)

0x405c78 LEA	0x1(%R9),%RCX

0x405c7c CMP	0x170(%RSP),%R9

0x405c84 MOV	%RCX,%R9

0x405c87 JE	405bc0

0x405c8d VPXOR	%XMM0,%XMM0,%XMM0

0x405c91 CMPL	$0x8,0xc8(%RSP)

0x405c99 MOV	0x58(%RSP),%R10

0x405c9e VMOVDQU	0x360(%RSP),%YMM6

0x405ca7 VMOVDQU	0x340(%RSP),%YMM7

0x405cb0 VPMOVSXBD	0x94af(%RIP),%YMM8

0x405cb9 VPMOVSXBD	0x94ae(%RIP),%YMM9

0x405cc2 VPBROADCASTQ	0x94ad(%RIP),%YMM10

0x405ccb VPMOVSXBQ	0x9470(%RIP),%YMM11

0x405cd4 VPBROADCASTD	0x9463(%RIP),%YMM12

0x405cdd MOV	0x248(%RSP),%EAX

0x405ce4 MOV	0x270(%RSP),%RSI

0x405cec MOV	0x38(%RSP),%RBX

0x405cf1 JB	405dde

0x405cf7 MOV	%R9D,%EDI

0x405cfa MOV	0x18(%RSP),%R8D

0x405cff MOV	0x188(%RSP),%R11

0x405d07 NOPW	(%RAX,%RAX,1)

  (28) 0x405d10 LEA	0x5(%R8),%ECX

  (28) 0x405d14 LEA	(%RSI,%RDI,1),%EDX

  (28) 0x405d17 VPBROADCASTD	%R8D,%XMM1

  (28) 0x405d1d VPADDD	%YMM1,%YMM8,%YMM2

  (28) 0x405d21 VPERMT2D	%YMM1,%YMM9,%YMM2

  (28) 0x405d27 VPBROADCASTD	%ECX,%YMM3

  (28) 0x405d2d VPBLENDD	$0x20,%YMM3,%YMM2,%YMM2

  (28) 0x405d33 VPADDD	%YMM1,%YMM10,%YMM1

  (28) 0x405d37 VPERMT2Q	%YMM1,%YMM11,%YMM2

  (28) 0x405d3d VPSUBD	%YMM12,%YMM2,%YMM1

  (28) 0x405d42 LEA	(%R10,%R14,1),%RCX

  (28) 0x405d46 KXNORW	%K0,%K0,%K1

  (28) 0x405d4a VPXOR	%XMM2,%XMM2,%XMM2

  (28) 0x405d4e VGATHERDPS	(%RCX,%YMM1,4),%YMM2{%K1}

  (28) 0x405d55 VCVTPS2PD	%XMM2,%YMM1

  (28) 0x405d59 VPBROADCASTD	%EDI,%XMM3

  (28) 0x405d5f VPADDD	%YMM7,%YMM3,%YMM4

  (28) 0x405d63 VPERMT2D	%YMM3,%YMM9,%YMM4

  (28) 0x405d69 VPBROADCASTD	%EDX,%YMM5

  (28) 0x405d6f VPBLENDD	$0x20,%YMM5,%YMM4,%YMM4

  (28) 0x405d75 VPADDD	%YMM3,%YMM6,%YMM3

  (28) 0x405d79 VPERMT2Q	%YMM3,%YMM11,%YMM4

  (28) 0x405d7f VPSUBD	%YMM12,%YMM4,%YMM3

  (28) 0x405d84 LEA	(%RBX,%R14,1),%RCX

  (28) 0x405d88 KXNORW	%K0,%K0,%K1

  (28) 0x405d8c VPXOR	%XMM4,%XMM4,%XMM4

  (28) 0x405d90 VGATHERDPS	(%RCX,%YMM3,4),%YMM4{%K1}

  (28) 0x405d97 VEXTRACTF128	$0x1,%YMM2,%XMM2

  (28) 0x405d9d VCVTPS2PD	%XMM2,%YMM2

  (28) 0x405da1 VCVTPS2PD	%XMM4,%YMM3

  (28) 0x405da5 VEXTRACTF128	$0x1,%YMM4,%XMM4

  (28) 0x405dab VCVTPS2PD	%XMM4,%YMM4

  (28) 0x405daf VMULPD	%YMM2,%YMM4,%YMM2

  (28) 0x405db3 VFMADD231PD	%YMM3,%YMM1,%YMM2

  (28) 0x405db8 VEXTRACTF128	$0x1,%YMM2,%XMM1

  (28) 0x405dbe VADDPD	%XMM1,%XMM2,%XMM1

  (28) 0x405dc2 VSHUFPD	$0x1,%XMM1,%XMM1,%XMM2

  (28) 0x405dc7 VADDSD	%XMM2,%XMM1,%XMM1

  (28) 0x405dcb VADDSD	%XMM1,%XMM0,%XMM0

  (28) 0x405dcf ADD	$0x8,%R8D

  (28) 0x405dd3 ADD	%EAX,%EDI

  (28) 0x405dd5 DEC	%R11

  (28) 0x405dd8 JNE	405d10

0x405dde MOV	0x1a0(%RSP),%RCX

0x405de6 CMP	$0x6,%RCX

0x405dea JA	405c52

/home/eoseret/llm-attention/attention_v2.cpp: 27 - 33

--------------------------------------------------------------------------------

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.58
CQA speedup if FP arith vectorized	1.42
CQA speedup if fully vectorized	7.60
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P2, P3, P11,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.33
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.46
CQA cycles if fully vectorized	0.83
Front-end cycles	5.83
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	6.33
P3 cycles	6.33
P4 cycles	0.50
P5 cycles	4.00
P6 cycles	2.00
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	2.00
P11 cycles	6.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	32.00
Nb uops	35.00
Nb loads	19.00
Nb stores	1.00
Nb stack references	14.00
FLOP/cycle	0.16
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.79
Bytes prefetched	0.00
Bytes loaded	172.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	35.29
Vectorization ratio load	38.46
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	14.29
Vector-efficiency ratio all	15.44
Vector-efficiency ratio load	16.35
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.61

Metric	Value
CQA speedup if no scalar integer	1.58
CQA speedup if FP arith vectorized	1.42
CQA speedup if fully vectorized	7.60
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P2, P3, P11,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.33
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.46
CQA cycles if fully vectorized	0.83
Front-end cycles	5.83
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	6.33
P3 cycles	6.33
P4 cycles	0.50
P5 cycles	4.00
P6 cycles	2.00
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	2.00
P11 cycles	6.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	32.00
Nb uops	35.00
Nb loads	19.00
Nb stores	1.00
Nb stack references	14.00
FLOP/cycle	0.16
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	27.79
Bytes prefetched	0.00
Bytes loaded	172.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	35.29
Vectorization ratio load	38.46
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	14.29
Vector-efficiency ratio all	15.44
Vector-efficiency ratio load	16.35
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	11.61

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-gnr-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:27-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:27,30-33.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.33 to 4.00 cycles (1.58x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by reading data from caches/RAM (load units are a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.33 to 5.83 cycles (1.09x speedup).

Workaround

Read less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33
VPMOVSXBD: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:27
- /home/eoseret/llm-attention/attention_v2.cpp:27
VPMOVSXBQ: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:27

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33
VPMOVSXBD: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:27
- /home/eoseret/llm-attention/attention_v2.cpp:27
VPMOVSXBQ: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:27

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 172 bytes (43 single precision FP elements). The binary loop is storing 4 bytes (1 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	32
nb uops	35
loop length	208
used x86 registers	10
used mmx registers	0
used xmm registers	1
used ymm registers	7
used zmm registers	0
nb stack references	14

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.83 cycles
front end	5.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.00	2.00	6.33	6.33	0.50	4.00	2.00	0.50	0.50	0.50	2.00	6.33
cycles	2.00	2.00	6.33	6.33	0.50	4.00	2.00	0.50	0.50	0.50	2.00	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.83
Dispatch	6.33
Overall L1	6.33

Vectorization ratios

INT

all	42%
load	41%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	16%

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	35%
load	38%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

INT

all	16%
load	17%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	8%
load	6%
store	6%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	15%
load	16%
store	6%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.33 cycles. At this rate:

14% of peak load performance is reached (27.16 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.63 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 405c8d

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV %R9D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x50(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
ADD 0x28(%RSP),%R8D	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
VMULSS 0x24c(%RSP),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VMOVSS %XMM0,(%RBX,%R8,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x1(%R9),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP 0x170(%RSP),%R9	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 405bc0 <main+0x27a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CMPL $0x8,0xc8(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
MOV 0x58(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVDQU 0x360(%RSP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVDQU 0x340(%RSP),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VPMOVSXBD 0x94af(%RIP),%YMM8	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VPMOVSXBD 0x94ae(%RIP),%YMM9	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VPBROADCASTQ 0x94ad(%RIP),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPMOVSXBQ 0x9470(%RIP),%YMM11	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (6.3%)
VPBROADCASTD 0x9463(%RIP),%YMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
MOV 0x248(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x270(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x38(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JB 405dde <main+0x29be>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x18(%RSP),%R8D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x188(%RSP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x1a0(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP $0x6,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JA 405c52 <main+0x2832>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-gnr-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:27-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:27,30-33.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.33 to 4.00 cycles (1.58x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 15% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Workaround

Read less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33
VPMOVSXBD: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:27
- /home/eoseret/llm-attention/attention_v2.cpp:27
VPMOVSXBQ: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:27

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33
VPMOVSXBD: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:27
- /home/eoseret/llm-attention/attention_v2.cpp:27
VPMOVSXBQ: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:27

Workaround

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: multiply

The binary loop is loading 172 bytes (43 single precision FP elements). The binary loop is storing 4 bytes (1 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	32
nb uops	35
loop length	208
used x86 registers	10
used mmx registers	0
used xmm registers	1
used ymm registers	7
used zmm registers	0
nb stack references	14

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.83 cycles
front end	5.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.00	2.00	6.33	6.33	0.50	4.00	2.00	0.50	0.50	0.50	2.00	6.33
cycles	2.00	2.00	6.33	6.33	0.50	4.00	2.00	0.50	0.50	0.50	2.00	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.83
Dispatch	6.33
Overall L1	6.33

Vectorization ratios

INT

all	42%
load	41%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	16%

all	0%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	35%
load	38%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

INT

all	16%
load	17%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	8%
load	6%
store	6%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	15%
load	16%
store	6%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.33 cycles. At this rate:

14% of peak load performance is reached (27.16 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.63 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 405c8d

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV %R9D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x50(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
ADD 0x28(%RSP),%R8D	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
VMULSS 0x24c(%RSP),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
VMOVSS %XMM0,(%RBX,%R8,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA 0x1(%R9),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP 0x170(%RSP),%R9	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %RCX,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 405bc0 <main+0x27a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CMPL $0x8,0xc8(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
MOV 0x58(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVDQU 0x360(%RSP),%YMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVDQU 0x340(%RSP),%YMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VPMOVSXBD 0x94af(%RIP),%YMM8	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VPMOVSXBD 0x94ae(%RIP),%YMM9	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (12.5%)
VPBROADCASTQ 0x94ad(%RIP),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPMOVSXBQ 0x9470(%RIP),%YMM11	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	vect (6.3%)
VPBROADCASTD 0x9463(%RIP),%YMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
MOV 0x248(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x270(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x38(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JB 405dde <main+0x29be>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R9D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x18(%RSP),%R8D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x188(%RSP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x1a0(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP $0x6,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JA 405c52 <main+0x2832>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code