OV - attention-gnr-256 - Loop 26

	Loop Id: 26	Module: attention-gnr-256	Source: attention_v2.cpp:26-254 [...]	Coverage: 0.05%

0x405bc0 MOV	0x228(%RSP),%RAX

0x405bc8 LEA	0x1(%RAX),%ECX

0x405bcb MOV	0x90(%RSP),%RDX

0x405bd3 ADD	%EDX,0x18(%RSP)

0x405bd7 CMP	0xbc(%RSP),%EAX

0x405bde MOV	%ECX,%EAX

0x405be0 JE	406000

0x405be6 MOV	%EAX,%ESI

0x405be8 IMUL	%EDX,%ESI

0x405beb MOV	%RAX,0x228(%RSP)

0x405bf3 IMUL	0x128(%RSP),%EAX

0x405bfb MOV	%EAX,0x28(%RSP)

0x405bff MOV	0x168(%RSP),%RCX

0x405c07 LEA	(%RCX,%RSI,1),%EAX

0x405c0a MOV	%EAX,0x88(%RSP)

0x405c11 LEA	(%RCX,%RSI,1),%EAX

0x405c14 MOV	%EAX,0x98(%RSP)

0x405c1b LEA	(%RCX,%RSI,1),%EAX

0x405c1e MOV	%EAX,0xb0(%RSP)

0x405c25 LEA	(%RCX,%RSI,1),%EAX

0x405c28 MOV	%EAX,0xa8(%RSP)

0x405c2f LEA	(%RCX,%RSI,1),%EAX

0x405c32 MOV	%EAX,0xa0(%RSP)

0x405c39 LEA	(%RCX,%RSI,1),%EAX

0x405c3c MOV	%RAX,0x30(%RSP)

0x405c41 ADD	0x160(%RSP),%ESI

0x405c48 MOV	%RSI,0x60(%RSP)

0x405c4d XOR	%R9D,%R9D

0x405c50 JMP	405c8d

  (27) 0x405c52 MOV	%R9D,%R8D

  (27) 0x405c55 MOV	0x50(%RSP),%RBX

  (27) 0x405c5a NOPW	(%RAX,%RAX,1)

  (27) 0x405c60 VCVTSD2SS	%XMM0,%XMM0,%XMM0

  (27) 0x405c64 ADD	0x28(%RSP),%R8D

  (27) 0x405c69 VMULSS	0x24c(%RSP),%XMM0,%XMM0

  (27) 0x405c72 VMOVSS	%XMM0,(%RBX,%R8,4)

  (27) 0x405c78 LEA	0x1(%R9),%RCX

  (27) 0x405c7c CMP	0x170(%RSP),%R9

  (27) 0x405c84 MOV	%RCX,%R9

  (27) 0x405c87 JE	405bc0

  (27) 0x405c8d VPXOR	%XMM0,%XMM0,%XMM0

  (27) 0x405c91 CMPL	$0x8,0xc8(%RSP)

  (27) 0x405c99 MOV	0x58(%RSP),%R10

  (27) 0x405c9e VMOVDQU	0x360(%RSP),%YMM6

  (27) 0x405ca7 VMOVDQU	0x340(%RSP),%YMM7

  (27) 0x405cb0 VPMOVSXBD	0x94af(%RIP),%YMM8

  (27) 0x405cb9 VPMOVSXBD	0x94ae(%RIP),%YMM9

  (27) 0x405cc2 VPBROADCASTQ	0x94ad(%RIP),%YMM10

  (27) 0x405ccb VPMOVSXBQ	0x9470(%RIP),%YMM11

  (27) 0x405cd4 VPBROADCASTD	0x9463(%RIP),%YMM12

  (27) 0x405cdd MOV	0x248(%RSP),%EAX

  (27) 0x405ce4 MOV	0x270(%RSP),%RSI

  (27) 0x405cec MOV	0x38(%RSP),%RBX

  (27) 0x405cf1 JB	405dde

  (27) 0x405cf7 MOV	%R9D,%EDI

  (27) 0x405cfa MOV	0x18(%RSP),%R8D

  (27) 0x405cff MOV	0x188(%RSP),%R11

  (27) 0x405d07 NOPW	(%RAX,%RAX,1)

    (28) 0x405d10 LEA	0x5(%R8),%ECX

    (28) 0x405d14 LEA	(%RSI,%RDI,1),%EDX

    (28) 0x405d17 VPBROADCASTD	%R8D,%XMM1

    (28) 0x405d1d VPADDD	%YMM1,%YMM8,%YMM2

    (28) 0x405d21 VPERMT2D	%YMM1,%YMM9,%YMM2

    (28) 0x405d27 VPBROADCASTD	%ECX,%YMM3

    (28) 0x405d2d VPBLENDD	$0x20,%YMM3,%YMM2,%YMM2

    (28) 0x405d33 VPADDD	%YMM1,%YMM10,%YMM1

    (28) 0x405d37 VPERMT2Q	%YMM1,%YMM11,%YMM2

    (28) 0x405d3d VPSUBD	%YMM12,%YMM2,%YMM1

    (28) 0x405d42 LEA	(%R10,%R14,1),%RCX

    (28) 0x405d46 KXNORW	%K0,%K0,%K1

    (28) 0x405d4a VPXOR	%XMM2,%XMM2,%XMM2

    (28) 0x405d4e VGATHERDPS	(%RCX,%YMM1,4),%YMM2{%K1}

    (28) 0x405d55 VCVTPS2PD	%XMM2,%YMM1

    (28) 0x405d59 VPBROADCASTD	%EDI,%XMM3

    (28) 0x405d5f VPADDD	%YMM7,%YMM3,%YMM4

    (28) 0x405d63 VPERMT2D	%YMM3,%YMM9,%YMM4

    (28) 0x405d69 VPBROADCASTD	%EDX,%YMM5

    (28) 0x405d6f VPBLENDD	$0x20,%YMM5,%YMM4,%YMM4

    (28) 0x405d75 VPADDD	%YMM3,%YMM6,%YMM3

    (28) 0x405d79 VPERMT2Q	%YMM3,%YMM11,%YMM4

    (28) 0x405d7f VPSUBD	%YMM12,%YMM4,%YMM3

    (28) 0x405d84 LEA	(%RBX,%R14,1),%RCX

    (28) 0x405d88 KXNORW	%K0,%K0,%K1

    (28) 0x405d8c VPXOR	%XMM4,%XMM4,%XMM4

    (28) 0x405d90 VGATHERDPS	(%RCX,%YMM3,4),%YMM4{%K1}

    (28) 0x405d97 VEXTRACTF128	$0x1,%YMM2,%XMM2

    (28) 0x405d9d VCVTPS2PD	%XMM2,%YMM2

    (28) 0x405da1 VCVTPS2PD	%XMM4,%YMM3

    (28) 0x405da5 VEXTRACTF128	$0x1,%YMM4,%XMM4

    (28) 0x405dab VCVTPS2PD	%XMM4,%YMM4

    (28) 0x405daf VMULPD	%YMM2,%YMM4,%YMM2

    (28) 0x405db3 VFMADD231PD	%YMM3,%YMM1,%YMM2

    (28) 0x405db8 VEXTRACTF128	$0x1,%YMM2,%XMM1

    (28) 0x405dbe VADDPD	%XMM1,%XMM2,%XMM1

    (28) 0x405dc2 VSHUFPD	$0x1,%XMM1,%XMM1,%XMM2

    (28) 0x405dc7 VADDSD	%XMM2,%XMM1,%XMM1

    (28) 0x405dcb VADDSD	%XMM1,%XMM0,%XMM0

    (28) 0x405dcf ADD	$0x8,%R8D

    (28) 0x405dd3 ADD	%EAX,%EDI

    (28) 0x405dd5 DEC	%R11

    (28) 0x405dd8 JNE	405d10

  (27) 0x405dde MOV	0x1a0(%RSP),%RCX

  (27) 0x405de6 CMP	$0x6,%RCX

  (27) 0x405dea JA	405c52

/home/eoseret/llm-attention/attention_v2.cpp: 26 - 254

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

[...]

254:       start = std::chrono::steady_clock::now();

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.31
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	micro-operation queue, P4, P7, P8, P9,
Function	main
Source	attention_v2.cpp:26-26,attention_v2.cpp:31-33,attention_v2.cpp:254-254
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	0.41
Front-end cycles	5.00
P0 cycles	2.70
P1 cycles	4.00
P2 cycles	2.33
P3 cycles	2.33
P4 cycles	5.00
P5 cycles	2.60
P6 cycles	2.50
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	2.60
P11 cycles	2.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	29.00
Nb uops	30.00
Nb loads	7.00
Nb stores	10.00
Nb stack references	15.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.40
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	52.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	8.17
Vector-efficiency ratio load	8.33
Vector-efficiency ratio store	8.13
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.31
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	micro-operation queue, P4, P7, P8, P9,
Function	main
Source	attention_v2.cpp:26-26,attention_v2.cpp:31-33,attention_v2.cpp:254-254
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	0.41
Front-end cycles	5.00
P0 cycles	2.70
P1 cycles	4.00
P2 cycles	2.33
P3 cycles	2.33
P4 cycles	5.00
P5 cycles	2.60
P6 cycles	2.50
P7 cycles	5.00
P8 cycles	5.00
P9 cycles	5.00
P10 cycles	2.60
P11 cycles	2.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	29.00
Nb uops	30.00
Nb loads	7.00
Nb stores	10.00
Nb stack references	15.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.40
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	52.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	8.17
Vector-efficiency ratio load	8.33
Vector-efficiency ratio store	8.13
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:26-254
Module	attention-gnr-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-33,254.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:26,31-33,254.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.00 to 0.41 cycles (12.31x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by writing data to caches/RAM (the store unit is a bottleneck).

Workaround

Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:26

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 40 bytes. The binary loop is storing 52 bytes.

General properties

nb instructions	29
nb uops	30
loop length	146
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.00 cycles
front end	5.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.70	2.60	2.33	2.33	5.00	2.60	2.50	5.00	5.00	5.00	2.60	2.33
cycles	2.70	4.00	2.33	2.33	5.00	2.60	2.50	5.00	5.00	5.00	2.60	2.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.00
Dispatch	5.00
Overall L1	5.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	8%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

4% of peak load performance is reached (8.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (10.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.00 to 4.00 cycles (1.25x speedup).

ASM code

In the binary file, the address of the loop is: 405be6

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV 0x228(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%RAX),%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV 0x90(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %EDX,0x18(%RSP)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (6.3%)
CMP 0xbc(%RSP),%EAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 406000 <main+0x2be0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %EDX,%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,0x228(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL 0x128(%RSP),%EAX	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
MOV %EAX,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x168(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RCX,%RSI,1),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,0x88(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA (%RCX,%RSI,1),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,0x98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA (%RCX,%RSI,1),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,0xb0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA (%RCX,%RSI,1),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,0xa8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA (%RCX,%RSI,1),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA (%RCX,%RSI,1),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RAX,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD 0x160(%RSP),%ESI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV %RSI,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 405c8d <main+0x286d>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

Function	main
Source file and lines	attention_v2.cpp:26-254
Module	attention-gnr-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-33,254.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:26,31-33,254.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by writing data to caches/RAM (the store unit is a bottleneck).

Workaround

Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:26

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 40 bytes. The binary loop is storing 52 bytes.

General properties

nb instructions	29
nb uops	30
loop length	146
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.00 cycles
front end	5.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.70	2.60	2.33	2.33	5.00	2.60	2.50	5.00	5.00	5.00	2.60	2.33
cycles	2.70	4.00	2.33	2.33	5.00	2.60	2.50	5.00	5.00	5.00	2.60	2.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.00
Dispatch	5.00
Overall L1	5.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	8%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

4% of peak load performance is reached (8.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (10.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 405be6

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV 0x228(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%RAX),%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV 0x90(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %EDX,0x18(%RSP)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (6.3%)
CMP 0xbc(%RSP),%EAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 406000 <main+0x2be0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %EDX,%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,0x228(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL 0x128(%RSP),%EAX	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
MOV %EAX,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x168(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RCX,%RSI,1),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,0x88(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA (%RCX,%RSI,1),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,0x98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA (%RCX,%RSI,1),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,0xb0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA (%RCX,%RSI,1),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,0xa8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA (%RCX,%RSI,1),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA (%RCX,%RSI,1),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RAX,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD 0x160(%RSP),%ESI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV %RSI,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
JMP 405c8d <main+0x286d>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code