OV - attention-gnr-256 - Loop 25

0x4060e0 VMAXSS	-0x1c(%RCX),%XMM8,%XMM0    [1]

0x4060e5 VMAXSS	-0x18(%RCX),%XMM0,%XMM0    [1]

0x4060ea VMAXSS	-0x14(%RCX),%XMM0,%XMM0    [1]

0x4060ef VMAXSS	-0x10(%RCX),%XMM0,%XMM0    [1]

0x4060f4 VMAXSS	-0xc(%RCX),%XMM0,%XMM0    [1]

0x4060f9 VMAXSS	-0x8(%RCX),%XMM0,%XMM0    [1]

0x4060fe VMAXSS	-0x4(%RCX),%XMM0,%XMM0    [1]

0x406103 VMAXSS	(%RCX),%XMM0,%XMM8    [1]

0x406107 ADD	$0x20,%RCX

0x40610b DEC	%RAX

0x40610e JNE	4060e0

/home/eoseret/llm-attention/attention_v2.cpp: 47 - 48

--------------------------------------------------------------------------------

47:       for (int idx = 0; idx <= row; ++idx) // vectorised

48:          if (S_row[idx] > max_val) max_val = S_row[idx];

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	16.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	8.00
Bottlenecks
Function	main
Source	attention_v2.cpp:47-48
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	32.00
CQA cycles if no scalar integer	32.00
CQA cycles if FP arith vectorized	32.00
CQA cycles if fully vectorized	2.00
Front-end cycles	1.67
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	2.67
P3 cycles	2.67
P4 cycles	0.00
P5 cycles	0.00
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	2.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	32
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	10.00
Nb loads	8.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.00
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	6.25
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	16.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	8.00
Bottlenecks
Function	main
Source	attention_v2.cpp:47-48
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	32.00
CQA cycles if no scalar integer	32.00
CQA cycles if FP arith vectorized	32.00
CQA cycles if fully vectorized	2.00
Front-end cycles	1.67
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	2.67
P3 cycles	2.67
P4 cycles	0.00
P5 cycles	0.00
P6 cycles	1.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	2.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	32
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	10.00
Nb loads	8.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.00
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	6.25
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:47-48
Module	attention-gnr-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:47-48.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 16 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 32.00 to 2.00 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes (8 single precision FP elements).

General properties

nb instructions	11
nb uops	10
loop length	48
used x86 registers	2
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	1.67 cycles
front end	1.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.00	4.00	2.67	2.67	0.00	0.00	1.00	0.00	0.00	0.00	0.00	2.67
cycles	4.00	4.00	2.67	2.67	0.00	0.00	1.00	0.00	0.00	0.00	0.00	2.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	32.00

Cycles summary

Front-end	1.67
Dispatch	4.00
Data deps.	32.00
Overall L1	32.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	6%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 32.00 cycles. At this rate:

0% of peak load performance is reached (1.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4060e0

Instruction	Nb FU	P0	P1	P2	P3	P6	P11	Latency	Recip. throughput	Vectorization
VMAXSS -0x1c(%RCX),%XMM8,%XMM0	1	0.50	0.50	0.33	0.33	0	0.33	4	0.50	scal (6.3%)
VMAXSS -0x18(%RCX),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0.33	4	0.50	scal (6.3%)
VMAXSS -0x14(%RCX),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0.33	4	0.50	scal (6.3%)
VMAXSS -0x10(%RCX),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0.33	4	0.50	scal (6.3%)
VMAXSS -0xc(%RCX),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0.33	4	0.50	scal (6.3%)
VMAXSS -0x8(%RCX),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0.33	4	0.50	scal (6.3%)
VMAXSS -0x4(%RCX),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0.33	4	0.50	scal (6.3%)
VMAXSS (%RCX),%XMM0,%XMM8	1	0.50	0.50	0.33	0.33	0	0.33	4	0.50	scal (6.3%)
ADD $0x20,%RCX	1	0	0	0	0	0	0	1	0.17	N/A
DEC %RAX	1	0	0	0	0	0	0	1	0.17	N/A
JNE 4060e0 <main+0x2cc0>	1	0.50	0	0	0	0.50	0	0	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:47-48
Module	attention-gnr-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:47-48.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 16 data elements could be processed at once in vector registers.

By vectorizing your loop, you can lower the cost of an iteration from 32.00 to 2.00 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

8 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes (8 single precision FP elements).

General properties

nb instructions	11
nb uops	10
loop length	48
used x86 registers	2
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	1.67 cycles
front end	1.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.00	4.00	2.67	2.67	0.00	0.00	1.00	0.00	0.00	0.00	0.00	2.67
cycles	4.00	4.00	2.67	2.67	0.00	0.00	1.00	0.00	0.00	0.00	0.00	2.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	32.00

Cycles summary

Front-end	1.67
Dispatch	4.00
Data deps.	32.00
Overall L1	32.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	6%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 32.00 cycles. At this rate:

0% of peak load performance is reached (1.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4060e0

Instruction	Nb FU	P0	P1	P2	P3	P6	P11	Latency	Recip. throughput	Vectorization
VMAXSS -0x1c(%RCX),%XMM8,%XMM0	1	0.50	0.50	0.33	0.33	0	0.33	4	0.50	scal (6.3%)
VMAXSS -0x18(%RCX),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0.33	4	0.50	scal (6.3%)
VMAXSS -0x14(%RCX),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0.33	4	0.50	scal (6.3%)
VMAXSS -0x10(%RCX),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0.33	4	0.50	scal (6.3%)
VMAXSS -0xc(%RCX),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0.33	4	0.50	scal (6.3%)
VMAXSS -0x8(%RCX),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0.33	4	0.50	scal (6.3%)
VMAXSS -0x4(%RCX),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0.33	4	0.50	scal (6.3%)
VMAXSS (%RCX),%XMM0,%XMM8	1	0.50	0.50	0.33	0.33	0	0.33	4	0.50	scal (6.3%)
ADD $0x20,%RCX	1	0	0	0	0	0	0	1	0.17	N/A
DEC %RAX	1	0	0	0	0	0	0	1	0.17	N/A
JNE 4060e0 <main+0x2cc0>	1	0.50	0	0	0	0.50	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code