OV - attention-gnr-256 - Loop 21

	Loop Id: 21	Module: attention-gnr-256	Source: attention_v2.cpp:43-273 [...]	Coverage: 0.37%

0x406060 MOV	0x110(%RSP),%RAX

0x406068 MOV	0x30(%RSP),%R8

0x40606d VMOVSS	%XMM11,(%RAX,%R8,4)

0x406073 MOV	0x158(%RSP),%RAX

0x40607b MOV	0xb0(%RSP),%RDX

0x406083 ADD	%RAX,%RDX

0x406086 MOV	0xa8(%RSP),%RSI

0x40608e INC	%RSI

0x406091 ADD	%RAX,%RDI

0x406094 MOV	0x98(%RSP),%RCX

0x40609c ADD	%RAX,%RCX

0x40609f MOV	%RCX,%RAX

0x4060a2 CMP	0x170(%RSP),%R8

0x4060aa MOV	%R9,%R8

0x4060ad JE	406450

0x4060b3 MOV	%RAX,0x98(%RSP)

0x4060bb LEA	0x1(%R8),%R9

0x4060bf VMOVSS	0x9081(%RIP),%XMM8

0x4060c7 CMP	$0x8,%R9

0x4060cb JB	406110

0x4060cd MOV	%RSI,%RAX

0x4060d0 SHR	$0x3,%RAX

0x4060d4 MOV	%RDX,%RCX

0x4060d7 VMOVSS	0x9069(%RIP),%XMM8

0x4060df NOP

  (25) 0x4060e0 VMAXSS	-0x1c(%RCX),%XMM8,%XMM0

  (25) 0x4060e5 VMAXSS	-0x18(%RCX),%XMM0,%XMM0

  (25) 0x4060ea VMAXSS	-0x14(%RCX),%XMM0,%XMM0

  (25) 0x4060ef VMAXSS	-0x10(%RCX),%XMM0,%XMM0

  (25) 0x4060f4 VMAXSS	-0xc(%RCX),%XMM0,%XMM0

  (25) 0x4060f9 VMAXSS	-0x8(%RCX),%XMM0,%XMM0

  (25) 0x4060fe VMAXSS	-0x4(%RCX),%XMM0,%XMM0

  (25) 0x406103 VMAXSS	(%RCX),%XMM0,%XMM8

  (25) 0x406107 ADD	$0x20,%RCX

  (25) 0x40610b DEC	%RAX

  (25) 0x40610e JNE	4060e0

0x406110 MOV	%R9,%RCX

0x406113 AND	$-0x8,%RCX

0x406117 CMP	%R9,%RCX

0x40611a JE	40612d

0x40611c MOV	%RCX,%RAX

0x40611f NOP

  (24) 0x406120 VMAXSS	(%RDI,%RAX,4),%XMM8,%XMM8

  (24) 0x406125 INC	%RAX

  (24) 0x406128 CMP	%RAX,%RSI

  (24) 0x40612b JNE	406120

0x40612d MOV	%RSI,0xa8(%RSP)

0x406135 MOV	%RDX,0xb0(%RSP)

0x40613d VPBROADCASTQ	%RCX,%YMM9

0x406143 TEST	%RCX,%RCX

0x406146 MOV	%R8,0x30(%RSP)

0x40614b MOV	%R9,0x60(%RSP)

0x406150 MOV	%RCX,0x88(%RSP)

0x406158 MOV	%RDI,0x28(%RSP)

0x40615d VPBROADCASTQ	%R9,%YMM12

0x406163 JE	4061e0

0x406165 LEA	-0x1(%RCX),%RSI

0x406169 MOV	0xc0(%RSP),%RAX

0x406171 IMUL	%R8,%RAX

0x406175 MOV	%RAX,0x18(%RSP)

0x40617a VBROADCASTSS	%XMM8,%YMM11

0x40617f VPXOR	%XMM10,%XMM10,%XMM10

0x406184 XOR	%EDI,%EDI

0x406186 NOPW	%CS:(%RAX,%RAX,1)

  (23) 0x406190 MOV	0x28(%RSP),%RAX

  (23) 0x406195 VMOVUPS	(%RAX,%RDI,4),%YMM0

  (23) 0x40619a VSUBPS	%YMM11,%YMM0,%YMM0

  (23) 0x40619f MOV	$0x407900,%RAX

  (23) 0x4061a6 CALL	%RAX

  (23) 0x4061a8 VADDPS	%YMM0,%YMM10,%YMM10

  (23) 0x4061ac ADD	$0x8,%RDI

  (23) 0x4061b0 CMP	%RSI,%RDI

  (23) 0x4061b3 JLE	406190

0x4061b5 VPCMPEQQ	%YMM9,%YMM12,%K0

0x4061bb KMOVD	%K0,%ECX

0x4061bf MOV	0x88(%RSP),%RDX

0x4061c7 MOV	%RDX,%RAX

0x4061ca TEST	$0x1,%CL

0x4061cd MOV	0x28(%RSP),%RDI

0x4061d2 MOV	0x18(%RSP),%RCX

0x4061d7 JE	4061f8

0x4061d9 JMP	406260

0x4061e0 MOV	0xc0(%RSP),%RCX

0x4061e8 IMUL	%R8,%RCX

0x4061ec VBROADCASTSS	%XMM8,%YMM11

0x4061f1 VPXOR	%XMM10,%XMM10,%XMM10

0x4061f6 XOR	%EAX,%EAX

0x4061f8 VPBROADCASTQ	%RAX,%YMM0

0x4061fe VPSUBQ	%YMM0,%YMM12,%YMM1

0x406202 VPSUBQ	%YMM0,%YMM12,%YMM0

0x406206 VPCMPNLEUQ	0x8e8f(%RIP),%YMM0,%K0

0x406211 VPCMPNLEUQ	0x8ea4(%RIP),%YMM1,%K1

0x40621c KSHIFTLB	$0x4,%K1,%K1

0x406222 KORB	%K1,%K0,%K1

0x406226 KMOVW	%K1,0x18(%RSP)

0x40622c ADD	%RAX,%RCX

0x40622f MOV	0x50(%RSP),%RAX

0x406234 VMOVUPS	(%RAX,%RCX,4),%YMM0{%K1}{z}

0x40623b VSUBPS	%YMM11,%YMM0,%YMM0

0x406240 VPMOVM2D	%K1,%YMM1

0x406246 CALL	407ca0 <__svml_expf8_mask_e9>

0x40624c MOV	0x88(%RSP),%RDX

0x406254 KMOVW	0x18(%RSP),%K1

0x40625a VADDPS	%YMM0,%YMM10,%YMM10{%K1}

0x406260 VEXTRACTF128	$0x1,%YMM10,%XMM0

0x406266 VADDPS	%XMM0,%XMM10,%XMM0

0x40626a VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x40626f VADDPS	%XMM1,%XMM0,%XMM0

0x406273 VMOVSHDUP	%XMM0,%XMM1

0x406277 VADDSS	%XMM1,%XMM0,%XMM11

0x40627b VMOVSS	0x8ec9(%RIP),%XMM0

0x406283 VDIVSS	%XMM11,%XMM0,%XMM1

0x406288 TEST	%RDX,%RDX

0x40628b JE	406340

0x406291 LEA	-0x1(%RDX),%RAX

0x406295 MOV	%RAX,0x18(%RSP)

0x40629a MOV	0xc0(%RSP),%RAX

0x4062a2 IMUL	0x30(%RSP),%RAX

0x4062a8 MOV	%RAX,0xa0(%RSP)

0x4062b0 VBROADCASTSS	%XMM8,%YMM10

0x4062b5 VBROADCASTSS	%XMM1,%YMM8

0x4062ba XOR	%EDI,%EDI

0x4062bc MOV	0x98(%RSP),%RSI

0x4062c4 NOPW	%CS:(%RAX,%RAX,1)

  (22) 0x4062d0 MOV	0x28(%RSP),%RAX

  (22) 0x4062d5 VMOVUPS	(%RAX,%RDI,4),%YMM0

  (22) 0x4062da VSUBPS	%YMM10,%YMM0,%YMM0

  (22) 0x4062df MOV	$0x407900,%RAX

  (22) 0x4062e6 CALL	%RAX

  (22) 0x4062e8 VMULPS	%YMM0,%YMM8,%YMM0

  (22) 0x4062ec VMOVUPS	%YMM0,(%RSI,%RDI,4)

  (22) 0x4062f1 ADD	$0x8,%RDI

  (22) 0x4062f5 CMP	0x18(%RSP),%RDI

  (22) 0x4062fa JLE	4062d0

0x4062fc MOV	0x60(%RSP),%R9

0x406301 VPBROADCASTQ	%R9,%YMM0

0x406307 VPCMPEQQ	%YMM9,%YMM0,%K0

0x40630d KMOVD	%K0,%EAX

0x406311 TEST	$0x1,%AL

0x406313 MOV	0x28(%RSP),%RDI

0x406318 MOV	0x88(%RSP),%RAX

0x406320 MOV	0xa0(%RSP),%RSI

0x406328 JE	406365

0x40632a CMP	0xc0(%RSP),%R9

0x406332 JAE	406060

0x406338 JMP	4063e2

0x406340 MOV	0x60(%RSP),%RAX

0x406345 VPBROADCASTQ	%RAX,%YMM0

0x40634b MOV	0xc0(%RSP),%RSI

0x406353 IMUL	0x30(%RSP),%RSI

0x406359 VBROADCASTSS	%XMM8,%YMM10

0x40635e VBROADCASTSS	%XMM1,%YMM8

0x406363 XOR	%EAX,%EAX

0x406365 VPBROADCASTQ	%RAX,%YMM1

0x40636b VPSUBQ	%YMM1,%YMM0,%YMM2

0x40636f VPSUBQ	%YMM1,%YMM0,%YMM0

0x406373 VPCMPNLEUQ	0x8d22(%RIP),%YMM0,%K0

0x40637e VPCMPNLEUQ	0x8d37(%RIP),%YMM2,%K1

0x406389 KSHIFTLB	$0x4,%K1,%K1

0x40638f KORB	%K1,%K0,%K1

0x406393 KMOVW	%K1,0x18(%RSP)

0x406399 ADD	%RAX,%RSI

0x40639c MOV	0x50(%RSP),%RAX

0x4063a1 VMOVUPS	(%RAX,%RSI,4),%YMM0{%K1}{z}

0x4063a8 VSUBPS	%YMM10,%YMM0,%YMM0

0x4063ad VPMOVM2D	%K1,%YMM1

0x4063b3 CALL	407ca0 <__svml_expf8_mask_e9>

0x4063b9 MOV	0x60(%RSP),%R9

0x4063be VMULPS	%YMM0,%YMM8,%YMM0

0x4063c2 MOV	0x40(%RSP),%RAX

0x4063c7 KMOVW	0x18(%RSP),%K1

0x4063cd VMOVUPS	%YMM0,(%RAX,%RSI,4){%K1}

0x4063d4 CMP	0xc0(%RSP),%R9

0x4063dc JAE	406060

0x4063e2 MOV	0x2a8(%RSP),%RDI

0x4063ea MOV	0x30(%RSP),%RAX

0x4063ef IMUL	%RAX,%RDI

0x4063f3 ADD	$0x4,%RDI

0x4063f7 MOV	0x2b0(%RSP),%RDX

0x4063ff SUB	%RAX,%RDX

0x406402 MOV	$0x3fffffffc,%RAX

0x40640c AND	%RAX,%RDI

0x40640f ADD	0x40(%RSP),%RDI

0x406414 SAL	$0x2,%RDX

0x406418 AND	%RAX,%RDX

0x40641b ADD	$0x4,%RDX

0x40641f XOR	%ESI,%ESI

0x406421 VMOVSS	%XMM11,0x18(%RSP)

0x406427 VZEROUPPER

0x40642a CALL	4097a0 <_intel_fast_memset>

0x40642f VMOVSS	0x18(%RSP),%XMM11

0x406435 MOV	0x60(%RSP),%R9

0x40643a MOV	0x28(%RSP),%RDI

0x40643f JMP	406060

/home/eoseret/llm-attention/attention_v2.cpp: 43 - 273

--------------------------------------------------------------------------------

43:    for (int row = 0; row < N; ++row) {

44:       const float *S_row = &S[row * N];

45:

46:       float max_val = -FLT_MAX;

47:       for (int idx = 0; idx <= row; ++idx) // vectorised

48:          if (S_row[idx] > max_val) max_val = S_row[idx];

49:

50:       float sum = 0.0f;

51: #pragma clang loop vectorize(enable)

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

54:

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

57:

58:       for (int idx = row + 1; idx < N; ++idx)

59:          P[row * N + idx] = 0.0f;

60:

61:       D[row] = sum;

[...]

98:    if (argc < 4) {

[...]

273:       start = std::chrono::steady_clock::now();

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.82
CQA speedup if FP arith vectorized	1.79
CQA speedup if fully vectorized	9.76
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.44
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:43-44,attention_v2.cpp:47-47,attention_v2.cpp:52-61,attention_v2.cpp:98-98,attention_v2.cpp:273-273
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.33
CQA cycles if no scalar integer	15.00
CQA cycles if FP arith vectorized	15.25
CQA cycles if fully vectorized	2.80
Front-end cycles	27.33
P0 cycles	14.03
P1 cycles	14.07
P2 cycles	14.33
P3 cycles	14.33
P4 cycles	9.00
P5 cycles	19.00
P6 cycles	13.90
P7 cycles	9.00
P8 cycles	9.00
P9 cycles	9.00
P10 cycles	14.00
P11 cycles	14.33
DIV/SQRT cycles	3.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	160.00
Nb uops	164.00
Nb loads	47.00
Nb stores	15.00
Nb stack references	17.00
FLOP/cycle	1.54
Nb FLOP add-sub	33.00
Nb FLOP mul	8.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.54
Bytes prefetched	0.00
Bytes loaded	492.00
Bytes stored	124.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	32.05
Vectorization ratio load	28.57
Vectorization ratio store	7.69
Vectorization ratio mul	50.00
Vectorization ratio add_sub	69.23
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	33.33
Vector-efficiency ratio all	20.23
Vector-efficiency ratio load	22.02
Vector-efficiency ratio store	14.42
Vector-efficiency ratio mul	31.25
Vector-efficiency ratio add_sub	34.13
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	18.49

Metric	Value
CQA speedup if no scalar integer	1.82
CQA speedup if FP arith vectorized	1.79
CQA speedup if fully vectorized	9.76
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.44
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:43-44,attention_v2.cpp:47-47,attention_v2.cpp:52-61,attention_v2.cpp:98-98,attention_v2.cpp:273-273
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	27.33
CQA cycles if no scalar integer	15.00
CQA cycles if FP arith vectorized	15.25
CQA cycles if fully vectorized	2.80
Front-end cycles	27.33
P0 cycles	14.03
P1 cycles	14.07
P2 cycles	14.33
P3 cycles	14.33
P4 cycles	9.00
P5 cycles	19.00
P6 cycles	13.90
P7 cycles	9.00
P8 cycles	9.00
P9 cycles	9.00
P10 cycles	14.00
P11 cycles	14.33
DIV/SQRT cycles	3.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	160.00
Nb uops	164.00
Nb loads	47.00
Nb stores	15.00
Nb stack references	17.00
FLOP/cycle	1.54
Nb FLOP add-sub	33.00
Nb FLOP mul	8.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.54
Bytes prefetched	0.00
Bytes loaded	492.00
Bytes stored	124.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	32.05
Vectorization ratio load	28.57
Vectorization ratio store	7.69
Vectorization ratio mul	50.00
Vectorization ratio add_sub	69.23
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	33.33
Vector-efficiency ratio all	20.23
Vector-efficiency ratio load	22.02
Vector-efficiency ratio store	14.42
Vector-efficiency ratio mul	31.25
Vector-efficiency ratio add_sub	34.13
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	18.49

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:43-273
Module	attention-gnr-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:43-61,98,273.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:43-44,47,52-61,98,273.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 72 paths individually, rerun with max-paths=72
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 72 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 27.33 to 15.00 cycles (1.82x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 20% of vector register length is used (average across all SSE/AVX instructions).

Details

32% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

28% of SSE/AVX loads are used in vector version.
7% of SSE/AVX stores are used in vector version.
69% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
33% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. Estimated speedup by perfect pairing: 1.01x. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__svml_expf8_mask_e9: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:56
_intel_fast_memset: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:59

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KMOVW: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:56
VZEROUPPER: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:59

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (four at a time). 4 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 42 FP arithmetical operations:

33: addition or subtraction
8: multiply
1: divide

The binary loop is loading 492 bytes (123 single precision FP elements). The binary loop is storing 124 bytes (31 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.07 FP operations per loaded or stored byte.

General properties

nb instructions	160
nb uops	164
loop length	849
used x86 registers	8
used mmx registers	0
used xmm registers	5
used ymm registers	8
used zmm registers	0
nb stack references	17
ADD-SUB / MUL ratio	6.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	27.33 cycles
front end	27.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	14.03	14.07	14.33	14.33	9.00	19.00	13.90	9.00	9.00	9.00	14.00	14.33
cycles	14.03	14.07	14.33	14.33	9.00	19.00	13.90	9.00	9.00	9.00	14.00	14.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

3.00

Cycles summary

Front-end	27.33
Dispatch	19.00
DIV/SQRT	3.00
Overall L1	27.33

Vectorization ratios

INT

all	25%
load	26%
store	0%
mul	0%
add-sub	57%
fma	NA (no fma vectorizable/vectorized instructions)
other	33%

all	46%
load	33%
store	33%
mul	100%
add-sub	83%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	33%

INT+FP

all	32%
load	28%
store	7%
mul	50%
add-sub	69%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	33%

Vector efficiency ratios

INT

all	19%
load	22%
store	12%
mul	12%
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	21%
load	20%
store	20%
mul	50%
add-sub	34%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	11%

INT+FP

all	20%
load	22%
store	14%
mul	31%
add-sub	34%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	18%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 27.33 cycles. At this rate:

9% of peak load performance is reached (18.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.54 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 27.33 to 19.00 cycles (1.44x speedup).

ASM code

In the binary file, the address of the loop is: 4060b3

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV 0x110(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM11,(%RAX,%R8,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x158(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xb0(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0xa8(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x98(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP 0x170(%RSP),%R8	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 406450 <main+0x3030>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,0x98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x1(%R8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSS 0x9081(%RIP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
CMP $0x8,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 406110 <main+0x2cf0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS 0x9069(%RIP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %R9,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40612d <main+0x2d0d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,0xa8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,0xb0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %RCX,%YMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
TEST %RCX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV %R8,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,0x88(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %R9,%YMM12	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
JE 4061e0 <main+0x2dc0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RCX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xc0(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R8,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSS %XMM8,%YMM11	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VPXOR %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPCMPEQQ %YMM9,%YMM12,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
KMOVD %K0,%ECX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x88(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST $0x1,%CL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV 0x28(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 4061f8 <main+0x2dd8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 406260 <main+0x2e40>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV 0xc0(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R8,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VBROADCASTSS %XMM8,%YMM11	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VPXOR %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RAX,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %YMM0,%YMM12,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
VPSUBQ %YMM0,%YMM12,%YMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
VPCMPNLEUQ 0x8e8f(%RIP),%YMM0,%K0																vect (50.0%)
VPCMPNLEUQ 0x8ea4(%RIP),%YMM1,%K1																vect (50.0%)
KSHIFTLB $0x4,%K1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KORB %K1,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
KMOVW %K1,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x50(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPS (%RAX,%RCX,4),%YMM0{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPS %YMM11,%YMM0,%YMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPMOVM2D %K1,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (1.6%)
CALL 407ca0 <__svml_expf8_mask_e9>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x88(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
KMOVW 0x18(%RSP),%K1	3	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	N/A
VADDPS %YMM0,%YMM10,%YMM10{%K1}	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM10,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPS %XMM0,%XMM10,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
VADDSS %XMM1,%XMM0,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VMOVSS 0x8ec9(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VDIVSS %XMM11,%XMM0,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	11-12	3	scal (6.3%)
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 406340 <main+0x2f20>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RDX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc0(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL 0x30(%RSP),%RAX	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
MOV %RAX,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSS %XMM8,%YMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM1,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV 0x98(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x60(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPBROADCASTQ %R9,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPCMPEQQ %YMM9,%YMM0,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
KMOVD %K0,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
TEST $0x1,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV 0x28(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x88(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xa0(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 406365 <main+0x2f45>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP 0xc0(%RSP),%R9	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JAE 406060 <main+0x2c40>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 4063e2 <main+0x2fc2>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV 0x60(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VPBROADCASTQ %RAX,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV 0xc0(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL 0x30(%RSP),%RSI	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
VBROADCASTSS %XMM8,%YMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM1,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RAX,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %YMM1,%YMM0,%YMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
VPSUBQ %YMM1,%YMM0,%YMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
VPCMPNLEUQ 0x8d22(%RIP),%YMM0,%K0																vect (50.0%)
VPCMPNLEUQ 0x8d37(%RIP),%YMM2,%K1																vect (50.0%)
KSHIFTLB $0x4,%K1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KORB %K1,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
KMOVW %K1,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x50(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPS (%RAX,%RSI,4),%YMM0{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPS %YMM10,%YMM0,%YMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPMOVM2D %K1,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (1.6%)
CALL 407ca0 <__svml_expf8_mask_e9>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x60(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULPS %YMM0,%YMM8,%YMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
MOV 0x40(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
KMOVW 0x18(%RSP),%K1	3	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	N/A
VMOVUPS %YMM0,(%RAX,%RSI,4){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
CMP 0xc0(%RSP),%R9	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JAE 406060 <main+0x2c40>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x2a8(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RAX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD $0x4,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x2b0(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x3fffffffc,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
AND %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
ADD 0x40(%RSP),%RDI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
SAL $0x2,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $0x4,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSS %XMM11,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 4097a0 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSS 0x18(%RSP),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x60(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x28(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 406060 <main+0x2c40>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	main
Source file and lines	attention_v2.cpp:43-273
Module	attention-gnr-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:43-61,98,273.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:43-44,47,52-61,98,273.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 72 paths individually, rerun with max-paths=72
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 20% of vector register length is used (average across all SSE/AVX instructions).

Details

32% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

28% of SSE/AVX loads are used in vector version.
7% of SSE/AVX stores are used in vector version.
69% of SSE/AVX addition or subtraction instructions are used in vector version.
50% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
33% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. Estimated speedup by perfect pairing: 1.01x. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

CALL instructions

Detected function call instructions.

Details

__svml_expf8_mask_e9: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:56
_intel_fast_memset: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:59

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

KMOVW: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:56
VZEROUPPER: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:59

Vector unaligned load/store instructions

Detected 1 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 42 FP arithmetical operations:

33: addition or subtraction
8: multiply
1: divide

The binary loop is loading 492 bytes (123 single precision FP elements). The binary loop is storing 124 bytes (31 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.07 FP operations per loaded or stored byte.

General properties

nb instructions	160
nb uops	164
loop length	849
used x86 registers	8
used mmx registers	0
used xmm registers	5
used ymm registers	8
used zmm registers	0
nb stack references	17
ADD-SUB / MUL ratio	6.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	27.33 cycles
front end	27.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	14.03	14.07	14.33	14.33	9.00	19.00	13.90	9.00	9.00	9.00	14.00	14.33
cycles	14.03	14.07	14.33	14.33	9.00	19.00	13.90	9.00	9.00	9.00	14.00	14.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

3.00

Cycles summary

Front-end	27.33
Dispatch	19.00
DIV/SQRT	3.00
Overall L1	27.33

Vectorization ratios

INT

all	25%
load	26%
store	0%
mul	0%
add-sub	57%
fma	NA (no fma vectorizable/vectorized instructions)
other	33%

all	46%
load	33%
store	33%
mul	100%
add-sub	83%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	33%

INT+FP

all	32%
load	28%
store	7%
mul	50%
add-sub	69%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	33%

Vector efficiency ratios

INT

all	19%
load	22%
store	12%
mul	12%
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	21%
load	20%
store	20%
mul	50%
add-sub	34%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	11%

INT+FP

all	20%
load	22%
store	14%
mul	31%
add-sub	34%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	18%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 27.33 cycles. At this rate:

9% of peak load performance is reached (18.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.54 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4060b3

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV 0x110(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM11,(%RAX,%R8,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x158(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xb0(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0xa8(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x98(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP 0x170(%RSP),%R8	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 406450 <main+0x3030>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RAX,0x98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x1(%R8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSS 0x9081(%RIP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
CMP $0x8,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JB 406110 <main+0x2cf0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x3,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %RDX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS 0x9069(%RIP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R9,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %R9,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 40612d <main+0x2d0d>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RCX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,0xa8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,0xb0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %RCX,%YMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
TEST %RCX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
MOV %R8,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,0x88(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %R9,%YMM12	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
JE 4061e0 <main+0x2dc0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RCX),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xc0(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R8,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RAX,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSS %XMM8,%YMM11	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VPXOR %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPCMPEQQ %YMM9,%YMM12,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
KMOVD %K0,%ECX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x88(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
TEST $0x1,%CL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV 0x28(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x18(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 4061f8 <main+0x2dd8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 406260 <main+0x2e40>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV 0xc0(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R8,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VBROADCASTSS %XMM8,%YMM11	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VPXOR %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RAX,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %YMM0,%YMM12,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
VPSUBQ %YMM0,%YMM12,%YMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
VPCMPNLEUQ 0x8e8f(%RIP),%YMM0,%K0																vect (50.0%)
VPCMPNLEUQ 0x8ea4(%RIP),%YMM1,%K1																vect (50.0%)
KSHIFTLB $0x4,%K1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KORB %K1,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
KMOVW %K1,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
ADD %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x50(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPS (%RAX,%RCX,4),%YMM0{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPS %YMM11,%YMM0,%YMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPMOVM2D %K1,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (1.6%)
CALL 407ca0 <__svml_expf8_mask_e9>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x88(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
KMOVW 0x18(%RSP),%K1	3	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	N/A
VADDPS %YMM0,%YMM10,%YMM10{%K1}	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM10,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPS %XMM0,%XMM10,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDPS %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VMOVSHDUP %XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (12.5%)
VADDSS %XMM1,%XMM0,%XMM11	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (6.3%)
VMOVSS 0x8ec9(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VDIVSS %XMM11,%XMM0,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	11-12	3	scal (6.3%)
TEST %RDX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (12.5%)
JE 406340 <main+0x2f20>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x1(%RDX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc0(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL 0x30(%RSP),%RAX	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
MOV %RAX,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSS %XMM8,%YMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM1,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
XOR %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV 0x98(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x60(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPBROADCASTQ %R9,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPCMPEQQ %YMM9,%YMM0,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (50.0%)
KMOVD %K0,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
TEST $0x1,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
MOV 0x28(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x88(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xa0(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
JE 406365 <main+0x2f45>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP 0xc0(%RSP),%R9	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JAE 406060 <main+0x2c40>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 4063e2 <main+0x2fc2>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV 0x60(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VPBROADCASTQ %RAX,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV 0xc0(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL 0x30(%RSP),%RSI	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
VBROADCASTSS %XMM8,%YMM10	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
VBROADCASTSS %XMM1,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (6.3%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RAX,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPSUBQ %YMM1,%YMM0,%YMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
VPSUBQ %YMM1,%YMM0,%YMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (50.0%)
VPCMPNLEUQ 0x8d22(%RIP),%YMM0,%K0																vect (50.0%)
VPCMPNLEUQ 0x8d37(%RIP),%YMM2,%K1																vect (50.0%)
KSHIFTLB $0x4,%K1,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	4	1	N/A
KORB %K1,%K0,%K1	1	1	0	0	0	0	0	0	0	0	0	0	0	1	1	N/A
KMOVW %K1,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	3	0.50	N/A
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x50(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVUPS (%RAX,%RSI,4),%YMM0{%K1}{z}	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPS %YMM10,%YMM0,%YMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPMOVM2D %K1,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (1.6%)
CALL 407ca0 <__svml_expf8_mask_e9>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x60(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMULPS %YMM0,%YMM8,%YMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
MOV 0x40(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
KMOVW 0x18(%RSP),%K1	3	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	3	1	N/A
VMOVUPS %YMM0,(%RAX,%RSI,4){%K1}	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
CMP 0xc0(%RSP),%R9	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
JAE 406060 <main+0x2c40>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x2a8(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RAX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD $0x4,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x2b0(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV $0x3fffffffc,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.28	N/A
AND %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
ADD 0x40(%RSP),%RDI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
SAL $0x2,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND %RAX,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $0x4,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVSS %XMM11,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 4097a0 <_intel_fast_memset>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVSS 0x18(%RSP),%XMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x60(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x28(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 406060 <main+0x2c40>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Masked instructions

Details

Workaround

FMA

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Masked instructions

Details

Workaround

FMA

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code