OV - attention-gnr-256 - Loop 17

	Loop Id: 17	Module: attention-gnr-256	Source: random.tcc:330-336 [...]	Coverage: 0.27%

0x403ee0 MOV	%RCX,%RDX

0x403ee3 SHR	$0x1e,%RDX

0x403ee7 XOR	%RCX,%RDX

0x403eea IMUL	$0x6c078965,%RDX,%RCX

0x403ef1 LEA	0x1(%RAX,%RCX,1),%RCX

0x403ef6 MOV	%ECX,%EDX

0x403ef8 MOV	%RDX,0x3a0(%RSP,%RAX,8)    [1]

0x403f00 MOV	%ECX,%EDX

0x403f02 SHR	$0x1e,%EDX

0x403f05 XOR	%RCX,%RDX

0x403f08 IMUL	$0x6c078965,%RDX,%RCX

0x403f0f LEA	0x2(%RAX,%RCX,1),%RCX

0x403f14 MOV	%ECX,%EDX

0x403f16 MOV	%RDX,0x3a8(%RSP,%RAX,8)    [1]

0x403f1e MOV	%ECX,%EDX

0x403f20 SHR	$0x1e,%EDX

0x403f23 XOR	%RCX,%RDX

0x403f26 IMUL	$0x6c078965,%RDX,%RCX

0x403f2d LEA	0x3(%RAX,%RCX,1),%RCX

0x403f32 MOV	%ECX,%EDX

0x403f34 MOV	%RDX,0x3b0(%RSP,%RAX,8)    [1]

0x403f3c MOV	%ECX,%EDX

0x403f3e SHR	$0x1e,%EDX

0x403f41 XOR	%RCX,%RDX

0x403f44 IMUL	$0x6c078965,%RDX,%RCX

0x403f4b LEA	0x4(%RAX,%RCX,1),%RCX

0x403f50 MOV	%ECX,%EDX

0x403f52 MOV	%RDX,0x3b8(%RSP,%RAX,8)    [1]

0x403f5a MOV	%ECX,%EDX

0x403f5c SHR	$0x1e,%EDX

0x403f5f XOR	%RCX,%RDX

0x403f62 IMUL	$0x6c078965,%RDX,%RCX

0x403f69 LEA	0x5(%RAX,%RCX,1),%RCX

0x403f6e MOV	%ECX,%EDX

0x403f70 MOV	%RDX,0x3c0(%RSP,%RAX,8)    [1]

0x403f78 MOV	%ECX,%EDX

0x403f7a SHR	$0x1e,%EDX

0x403f7d XOR	%RCX,%RDX

0x403f80 IMUL	$0x6c078965,%RDX,%RCX

0x403f87 LEA	0x6(%RAX,%RCX,1),%RCX

0x403f8c MOV	%ECX,%EDX

0x403f8e MOV	%RDX,0x3c8(%RSP,%RAX,8)    [1]

0x403f96 MOV	%ECX,%EDX

0x403f98 SHR	$0x1e,%EDX

0x403f9b XOR	%RCX,%RDX

0x403f9e IMUL	$0x6c078965,%RDX,%RCX

0x403fa5 LEA	0x7(%RAX,%RCX,1),%RCX

0x403faa MOV	%ECX,%EDX

0x403fac MOV	%RDX,0x3d0(%RSP,%RAX,8)    [1]

0x403fb4 MOV	%ECX,%EDX

0x403fb6 SHR	$0x1e,%EDX

0x403fb9 XOR	%RCX,%RDX

0x403fbc IMUL	$0x6c078965,%EDX,%ECX

0x403fc2 LEA	0x8(%RAX,%RCX,1),%ECX

0x403fc6 MOV	%RCX,0x3d8(%RSP,%RAX,8)    [1]

0x403fce ADD	$0x8,%RAX

0x403fd2 CMP	$0x268,%RAX

0x403fd8 JNE	403ee0

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.h: 140 - 140

--------------------------------------------------------------------------------

140: 	    __res %= __m;

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc: 330 - 336

--------------------------------------------------------------------------------

330:       for (size_t __i = 1; __i < state_size; ++__i)

331: 	{

332: 	  _UIntType __x = _M_x[__i - 1];

333: 	  __x ^= __x >> (__w - 2);

334: 	  __x *= __f;

335: 	  __x += __detail::__mod<_UIntType, __n>(__i);

336: 	  _M_x[__i] = __detail::__mod<_UIntType,

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	16.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.85
Bottlenecks	P1,
Function	main
Source	random.h:140-140,random.tcc:330-336
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.60
CQA cycles if no scalar integer	17.60
CQA cycles if FP arith vectorized	17.60
CQA cycles if fully vectorized	1.10
Front-end cycles	9.50
P0 cycles	4.50
P1 cycles	17.60
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	4.00
P5 cycles	4.00
P6 cycles	4.50
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	58.00
Nb uops	57.00
Nb loads	0.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.64
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	9.13
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.27

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	16.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.85
Bottlenecks	P1,
Function	main
Source	random.h:140-140,random.tcc:330-336
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	17.60
CQA cycles if no scalar integer	17.60
CQA cycles if FP arith vectorized	17.60
CQA cycles if fully vectorized	1.10
Front-end cycles	9.50
P0 cycles	4.50
P1 cycles	17.60
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	4.00
P5 cycles	4.00
P6 cycles	4.50
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	0
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	58.00
Nb uops	57.00
Nb loads	0.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.64
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	64.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	9.13
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.27

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	random.tcc:330-336
Module	attention-gnr-256

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.h:140
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:330-336

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 17.60 to 1.10 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 64 bytes.

General properties

nb instructions	58
nb uops	57
loop length	254
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.50	16.00	0.00	0.00	4.00	4.00	4.50	4.00	4.00	4.00	4.00	0.00
cycles	4.50	17.60	0.00	0.00	4.00	4.00	4.50	4.00	4.00	4.00	4.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	9.50
Dispatch	17.60
Data deps.	0.00
Overall L1	17.60

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.60 cycles. At this rate:

2% of peak store performance is reached (3.64 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 403ee0

Instruction	Nb FU	P0	P1	P4	P5	P6	P7	P8	P9	P10	Latency	Recip. throughput	Vectorization
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x1e,%RDX	1	0.50	0	0	0	0.50	0	0	0	0	0-2	0.50	scal (12.5%)
XOR %RCX,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
LEA 0x1(%RAX,%RCX,1),%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x3a0(%RSP,%RAX,8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x1e,%EDX	1	0.50	0	0	0	0.50	0	0	0	0	0-2	0.50	scal (6.3%)
XOR %RCX,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
LEA 0x2(%RAX,%RCX,1),%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x3a8(%RSP,%RAX,8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x1e,%EDX	1	0.50	0	0	0	0.50	0	0	0	0	0-2	0.50	scal (6.3%)
XOR %RCX,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
LEA 0x3(%RAX,%RCX,1),%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x3b0(%RSP,%RAX,8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x1e,%EDX	1	0.50	0	0	0	0.50	0	0	0	0	0-2	0.50	scal (6.3%)
XOR %RCX,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
LEA 0x4(%RAX,%RCX,1),%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x3b8(%RSP,%RAX,8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x1e,%EDX	1	0.50	0	0	0	0.50	0	0	0	0	0-2	0.50	scal (6.3%)
XOR %RCX,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
LEA 0x5(%RAX,%RCX,1),%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x3c0(%RSP,%RAX,8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x1e,%EDX	1	0.50	0	0	0	0.50	0	0	0	0	0-2	0.50	scal (6.3%)
XOR %RCX,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
LEA 0x6(%RAX,%RCX,1),%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x3c8(%RSP,%RAX,8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x1e,%EDX	1	0.50	0	0	0	0.50	0	0	0	0	0-2	0.50	scal (6.3%)
XOR %RCX,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
LEA 0x7(%RAX,%RCX,1),%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x3d0(%RSP,%RAX,8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x1e,%EDX	1	0.50	0	0	0	0.50	0	0	0	0	0-2	0.50	scal (6.3%)
XOR %RCX,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	scal (12.5%)
IMUL $0x6c078965,%EDX,%ECX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
LEA 0x8(%RAX,%RCX,1),%ECX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
MOV %RCX,0x3d8(%RSP,%RAX,8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x268,%RAX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1	0.20	N/A
JNE 403ee0 <main+0xac0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	random.tcc:330-336
Module	attention-gnr-256

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.h:140
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:330-336

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 64 bytes.

General properties

nb instructions	58
nb uops	57
loop length	254
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.50	16.00	0.00	0.00	4.00	4.00	4.50	4.00	4.00	4.00	4.00	0.00
cycles	4.50	17.60	0.00	0.00	4.00	4.00	4.50	4.00	4.00	4.00	4.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	0.00

Cycles summary

Front-end	9.50
Dispatch	17.60
Data deps.	0.00
Overall L1	17.60

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 17.60 cycles. At this rate:

2% of peak store performance is reached (3.64 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 403ee0

Instruction	Nb FU	P0	P1	P4	P5	P6	P7	P8	P9	P10	Latency	Recip. throughput	Vectorization
MOV %RCX,%RDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x1e,%RDX	1	0.50	0	0	0	0.50	0	0	0	0	0-2	0.50	scal (12.5%)
XOR %RCX,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
LEA 0x1(%RAX,%RCX,1),%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x3a0(%RSP,%RAX,8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x1e,%EDX	1	0.50	0	0	0	0.50	0	0	0	0	0-2	0.50	scal (6.3%)
XOR %RCX,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
LEA 0x2(%RAX,%RCX,1),%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x3a8(%RSP,%RAX,8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x1e,%EDX	1	0.50	0	0	0	0.50	0	0	0	0	0-2	0.50	scal (6.3%)
XOR %RCX,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
LEA 0x3(%RAX,%RCX,1),%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x3b0(%RSP,%RAX,8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x1e,%EDX	1	0.50	0	0	0	0.50	0	0	0	0	0-2	0.50	scal (6.3%)
XOR %RCX,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
LEA 0x4(%RAX,%RCX,1),%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x3b8(%RSP,%RAX,8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x1e,%EDX	1	0.50	0	0	0	0.50	0	0	0	0	0-2	0.50	scal (6.3%)
XOR %RCX,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
LEA 0x5(%RAX,%RCX,1),%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x3c0(%RSP,%RAX,8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x1e,%EDX	1	0.50	0	0	0	0.50	0	0	0	0	0-2	0.50	scal (6.3%)
XOR %RCX,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
LEA 0x6(%RAX,%RCX,1),%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x3c8(%RSP,%RAX,8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x1e,%EDX	1	0.50	0	0	0	0.50	0	0	0	0	0-2	0.50	scal (6.3%)
XOR %RCX,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	scal (12.5%)
IMUL $0x6c078965,%RDX,%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
LEA 0x7(%RAX,%RCX,1),%RCX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x3d0(%RSP,%RAX,8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x1e,%EDX	1	0.50	0	0	0	0.50	0	0	0	0	0-2	0.50	scal (6.3%)
XOR %RCX,%RDX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	scal (12.5%)
IMUL $0x6c078965,%EDX,%ECX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
LEA 0x8(%RAX,%RCX,1),%ECX	1	0	1	0	0	0	0	0	0	0	3	1	N/A
MOV %RCX,0x3d8(%RSP,%RAX,8)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (12.5%)
ADD $0x8,%RAX	1	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x268,%RAX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1	0.20	N/A
JNE 403ee0 <main+0xac0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code