OV - attention-clang-gnr256 - Loop 99 - attention-clang-gnr256

	Loop Id: 99	Module: attention-clang-gnr256	Source: random.tcc:401-3367 [...]	Coverage: 0.35%

0x3880 MOV	%RBX,%RDX

0x3883 INC	%RBX

0x3886 MOV	%RBX,0x17f8(%RSP)

0x388e MOV	0x478(%RSP,%RDX,8),%RDX

0x3896 MOV	%RDX,%RSI

0x3899 SHR	$0xb,%RSI

0x389d MOV	%ESI,%ESI

0x389f XOR	%RDX,%RSI

0x38a2 MOV	%ESI,%EDX

0x38a4 SAL	$0x7,%EDX

0x38a7 AND	$-0x62d3a980,%EDX

0x38ad XOR	%RSI,%RDX

0x38b0 MOV	%EDX,%ESI

0x38b2 SAL	$0xf,%ESI

0x38b5 AND	$-0x103a0000,%ESI

0x38bb XOR	%RDX,%RSI

0x38be MOV	%RSI,%RDX

0x38c1 SHR	$0x12,%RDX

0x38c5 XOR	%RSI,%RDX

0x38c8 VCVTUSI2SS	%RDX,%XMM15,%XMM2

0x38ce VFMADD231SS	%XMM2,%XMM1,%XMM0

0x38d3 VMULSS	0x372d(%RIP),%XMM1,%XMM1

0x38db DEC	%RCX

0x38de JE	3c40

0x38e4 CMP	$0x270,%RBX

0x38eb JB	3880

0x38ed VPBROADCASTQ	%R13,%YMM2

0x38f3 XOR	%EDX,%EDX

0x38f5 VPBROADCASTQ	0x3742(%RIP),%YMM14

0x38fe VPBROADCASTQ	0x3741(%RIP),%YMM15

0x3907 VPBROADCASTQ	0x373f(%RIP),%YMM16

0x3911 VPBROADCASTQ	0x373d(%RIP),%YMM17

0x391b NOPL	(%RAX,%RAX,1)

  (100) 0x3920 VMOVDQU	0x480(%RSP,%RDX,8),%YMM3

  (100) 0x3929 VMOVDQU	0x4a0(%RSP,%RDX,8),%YMM4

  (100) 0x3932 VMOVDQU	0x4c0(%RSP,%RDX,8),%YMM5

  (100) 0x393b VALIGNQ	$0x3,%YMM2,%YMM3,%YMM6

  (100) 0x3942 VMOVDQU	0x4e0(%RSP,%RDX,8),%YMM2

  (100) 0x394b VALIGNQ	$0x3,%YMM3,%YMM4,%YMM7

  (100) 0x3952 VALIGNQ	$0x3,%YMM4,%YMM5,%YMM8

  (100) 0x3959 VALIGNQ	$0x3,%YMM5,%YMM2,%YMM9

  (100) 0x3960 VPAND	%YMM3,%YMM15,%YMM10

  (100) 0x3964 VPAND	%YMM4,%YMM15,%YMM11

  (100) 0x3968 VPAND	%YMM5,%YMM15,%YMM12

  (100) 0x396c VPAND	%YMM2,%YMM15,%YMM13

  (100) 0x3970 VPTERNLOGQ	$-0x8,%YMM14,%YMM6,%YMM10

  (100) 0x3977 VPTERNLOGQ	$-0x8,%YMM14,%YMM7,%YMM11

  (100) 0x397e VPTERNLOGQ	$-0x8,%YMM14,%YMM8,%YMM12

  (100) 0x3985 VPTERNLOGQ	$-0x8,%YMM14,%YMM9,%YMM13

  (100) 0x398c VPSRLQ	$0x1,%YMM10,%YMM6

  (100) 0x3992 VPSRLQ	$0x1,%YMM11,%YMM7

  (100) 0x3998 VPSRLQ	$0x1,%YMM12,%YMM8

  (100) 0x399e VPSRLQ	$0x1,%YMM13,%YMM9

  (100) 0x39a4 VPXOR	0x10e0(%RSP,%RDX,8),%YMM6,%YMM6

  (100) 0x39ad VPXOR	0x1100(%RSP,%RDX,8),%YMM7,%YMM7

  (100) 0x39b6 VPXOR	0x1120(%RSP,%RDX,8),%YMM8,%YMM8

  (100) 0x39bf VPXOR	0x1140(%RSP,%RDX,8),%YMM9,%YMM9

  (100) 0x39c8 VPTESTMQ	%YMM16,%YMM3,%K1

  (100) 0x39ce VPTESTMQ	%YMM16,%YMM4,%K2

  (100) 0x39d4 VPTESTMQ	%YMM16,%YMM5,%K3

  (100) 0x39da VPTESTMQ	%YMM16,%YMM2,%K4

  (100) 0x39e0 VPXORQ	%YMM17,%YMM6,%YMM6{%K1}

  (100) 0x39e6 VPXORQ	%YMM17,%YMM7,%YMM7{%K2}

  (100) 0x39ec VPXORQ	%YMM17,%YMM8,%YMM8{%K3}

  (100) 0x39f2 VPXORQ	%YMM17,%YMM9,%YMM9{%K4}

  (100) 0x39f8 VMOVDQU	%YMM6,0x478(%RSP,%RDX,8)

  (100) 0x3a01 VMOVDQU	%YMM7,0x498(%RSP,%RDX,8)

  (100) 0x3a0a VMOVDQU	%YMM8,0x4b8(%RSP,%RDX,8)

  (100) 0x3a13 VMOVDQU	%YMM9,0x4d8(%RSP,%RDX,8)

  (100) 0x3a1c ADD	$0x10,%RDX

  (100) 0x3a20 CMP	$0xe0,%RDX

  (100) 0x3a27 JNE	3920

0x3a2d VEXTRACTI128	$0x1,%YMM2,%XMM2

0x3a33 VPEXTRQ	$0x1,%XMM2,%RDI

0x3a39 AND	$-0x80000000,%RDI

0x3a40 MOV	0xb80(%RSP),%RSI

0x3a48 MOV	0xb88(%RSP),%RDX

0x3a50 MOV	%ESI,%R8D

0x3a53 AND	$0x7ffffffe,%R8D

0x3a5a OR	%RDI,%R8

0x3a5d SHR	$0x1,%R8

0x3a60 XOR	0x17e0(%RSP),%R8

0x3a68 MOV	%ESI,%EDI

0x3a6a AND	$0x1,%EDI

0x3a6d NEG	%EDI

0x3a6f AND	%R12D,%EDI

0x3a72 XOR	%R8,%RDI

0x3a75 MOV	%RDI,0xb78(%RSP)

0x3a7d AND	$-0x80000000,%RSI

0x3a84 MOV	%EDX,%EDI

0x3a86 AND	$0x7ffffffe,%EDI

0x3a8c OR	%RSI,%RDI

0x3a8f SHR	$0x1,%RDI

0x3a92 XOR	0x17e8(%RSP),%RDI

0x3a9a MOV	%EDX,%ESI

0x3a9c AND	$0x1,%ESI

0x3a9f NEG	%ESI

0x3aa1 AND	%R12D,%ESI

0x3aa4 XOR	%RDI,%RSI

0x3aa7 MOV	%RSI,0xb80(%RSP)

0x3aaf AND	$-0x80000000,%RDX

0x3ab6 MOV	0xb90(%RSP),%RSI

0x3abe MOV	%ESI,%EDI

0x3ac0 VPBROADCASTQ	%RSI,%XMM2

0x3ac6 AND	$0x7ffffffe,%ESI

0x3acc OR	%RDX,%RSI

0x3acf SHR	$0x1,%RSI

0x3ad2 XOR	0x17f0(%RSP),%RSI

0x3ada AND	$0x1,%EDI

0x3add NEG	%EDI

0x3adf AND	%R12D,%EDI

0x3ae2 XOR	%RSI,%RDI

0x3ae5 MOV	%RDI,0xb88(%RSP)

0x3aed MOV	$0xe8,%EDX

0x3af2 VPBROADCASTQ	0x3545(%RIP),%XMM7

0x3afb VPBROADCASTQ	0x3544(%RIP),%XMM8

0x3b04 VPBROADCASTQ	0x3543(%RIP),%XMM9

0x3b0d VPBROADCASTQ	0x3542(%RIP),%XMM10

0x3b16 NOPW	%CS:(%RAX,%RAX,1)

  (101) 0x3b20 VMOVDQU	0x458(%RSP,%RDX,8),%XMM3

  (101) 0x3b29 VMOVDQU	0x468(%RSP,%RDX,8),%XMM4

  (101) 0x3b32 VPALIGNR	$0x8,%XMM2,%XMM3,%XMM2

  (101) 0x3b38 VMOVDQU	0x478(%RSP,%RDX,8),%XMM5

  (101) 0x3b41 VPAND	%XMM3,%XMM8,%XMM6

  (101) 0x3b45 VPTERNLOGQ	$-0x8,%XMM7,%XMM2,%XMM6

  (101) 0x3b4c VPSRLQ	$0x1,%XMM6,%XMM2

  (101) 0x3b51 VPXOR	-0x2c8(%RSP,%RDX,8),%XMM2,%XMM2

  (101) 0x3b5a VPTESTMQ	%XMM9,%XMM3,%K1

  (101) 0x3b60 VPXORQ	%XMM10,%XMM2,%XMM2{%K1}

  (101) 0x3b66 VMOVDQU	%XMM2,0x450(%RSP,%RDX,8)

  (101) 0x3b6f VPALIGNR	$0x8,%XMM3,%XMM4,%XMM2

  (101) 0x3b75 VPAND	%XMM4,%XMM8,%XMM3

  (101) 0x3b79 VPTERNLOGQ	$-0x8,%XMM7,%XMM2,%XMM3

  (101) 0x3b80 VPSRLQ	$0x1,%XMM3,%XMM2

  (101) 0x3b85 VPXOR	-0x2b8(%RSP,%RDX,8),%XMM2,%XMM2

  (101) 0x3b8e VPTESTMQ	%XMM9,%XMM4,%K1

  (101) 0x3b94 VPXORQ	%XMM10,%XMM2,%XMM2{%K1}

  (101) 0x3b9a VMOVDQU	%XMM2,0x460(%RSP,%RDX,8)

  (101) 0x3ba3 VPALIGNR	$0x8,%XMM4,%XMM5,%XMM2

  (101) 0x3ba9 VPAND	%XMM5,%XMM8,%XMM3

  (101) 0x3bad VPTERNLOGQ	$-0x8,%XMM7,%XMM2,%XMM3

  (101) 0x3bb4 VPSRLQ	$0x1,%XMM3,%XMM2

  (101) 0x3bb9 VPXOR	-0x2a8(%RSP,%RDX,8),%XMM2,%XMM2

  (101) 0x3bc2 VPTESTMQ	%XMM9,%XMM5,%K1

  (101) 0x3bc8 VPXORQ	%XMM10,%XMM2,%XMM2{%K1}

  (101) 0x3bce VMOVDQU	%XMM2,0x470(%RSP,%RDX,8)

  (101) 0x3bd7 ADD	$0x6,%RDX

  (101) 0x3bdb VMOVDQA	%XMM5,%XMM2

  (101) 0x3bdf CMP	$0x274,%RDX

  (101) 0x3be6 JNE	3b20

0x3bec MOV	0x17f0(%RSP),%RDX

0x3bf4 MOV	$-0x80000000,%RSI

0x3bfb AND	%RSI,%RDX

0x3bfe MOV	0x478(%RSP),%R13

0x3c06 MOV	%R13D,%ESI

0x3c09 AND	$0x7ffffffe,%ESI

0x3c0f OR	%RDX,%RSI

0x3c12 SHR	$0x1,%RSI

0x3c15 XOR	0x10d8(%RSP),%RSI

0x3c1d MOV	%R13D,%EDX

0x3c20 AND	$0x1,%EDX

0x3c23 NEG	%EDX

0x3c25 AND	%R12D,%EDX

0x3c28 XOR	%RSI,%RDX

0x3c2b MOV	%RDX,0x17f0(%RSP)

0x3c33 XOR	%EBX,%EBX

0x3c35 JMP	3880

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc: 401 - 3367

--------------------------------------------------------------------------------

401:       for (size_t __k = 0; __k < (__n - __m); ++__k)

402:         {

403: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

404: 			   | (_M_x[__k + 1] & __lower_mask));

405: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

406: 		       ^ ((__y & 0x01) ? __a : 0));

407:         }

408:

409:       for (size_t __k = (__n - __m); __k < (__n - 1); ++__k)

410: 	{

411: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

412: 			   | (_M_x[__k + 1] & __lower_mask));

413: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

414: 		       ^ ((__y & 0x01) ? __a : 0));

415: 	}

416:

417:       _UIntType __y = ((_M_x[__n - 1] & __upper_mask)

418: 		       | (_M_x[0] & __lower_mask));

419:       _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1)

420: 		       ^ ((__y & 0x01) ? __a : 0));

[...]

455:       if (_M_p >= state_size)

456: 	_M_gen_rand();

457:

458:       // Calculate o(x(i)).

459:       result_type __z = _M_x[_M_p++];

460:       __z ^= (__z >> __u) & __d;

461:       __z ^= (__z << __s) & __b;

462:       __z ^= (__z << __t) & __c;

463:       __z ^= (__z >> __l);

[...]

3364:       for (size_t __k = __m; __k != 0; --__k)

3365: 	{

3366: 	  __sum += _RealType(__urng() - __urng.min()) * __tmp;

3367: 	  __tmp *= __r;

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.35
CQA speedup if FP arith vectorized	1.84
CQA speedup if fully vectorized	11.86
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.34
Bottlenecks
Function	main
Source	random.tcc:401-406,random.tcc:409-409,random.tcc:413-413,random.tcc:417-420,random.tcc:455-455,random.tcc:459-463,random.tcc:3364-3367
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.58
CQA cycles if no scalar integer	4.50
CQA cycles if FP arith vectorized	5.75
CQA cycles if fully vectorized	0.89
Front-end cycles	10.58
P0 cycles	7.85
P1 cycles	7.70
P2 cycles	3.50
P3 cycles	3.50
P4 cycles	1.50
P5 cycles	7.80
P6 cycles	7.85
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	1.50
P10 cycles	7.80
P11 cycles	3.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	61.50
Nb uops	63.50
Nb loads	10.50
Nb stores	3.00
Nb stack references	5.50
FLOP/cycle	0.28
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.86
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	24.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	0.72
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.86
Vector-efficiency ratio all	9.97
Vector-efficiency ratio load	9.18
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	6.25
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.93

Metric	Value
CQA speedup if no scalar integer	3.33
CQA speedup if FP arith vectorized	1.75
CQA speedup if fully vectorized	11.41
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.36
Bottlenecks	micro-operation queue,
Function	main
Source	random.tcc:401-406,random.tcc:409-409,random.tcc:413-413,random.tcc:417-420,random.tcc:455-455,random.tcc:459-463,random.tcc:3364-3367
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.67
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	9.50
CQA cycles if fully vectorized	1.46
Front-end cycles	16.67
P0 cycles	12.20
P1 cycles	12.10
P2 cycles	6.33
P3 cycles	6.33
P4 cycles	2.50
P5 cycles	12.20
P6 cycles	12.30
P7 cycles	2.50
P8 cycles	2.50
P9 cycles	2.50
P10 cycles	12.20
P11 cycles	6.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	97.00
Nb uops	100.00
Nb loads	19.00
Nb stores	5.00
Nb stack references	10.00
FLOP/cycle	0.18
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.28
Bytes prefetched	0.00
Bytes loaded	148.00
Bytes stored	40.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	1.45
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	1.72
Vector-efficiency ratio all	10.33
Vector-efficiency ratio load	12.11
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	6.25
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.13

Metric	Value
CQA speedup if no scalar integer	1.13
CQA speedup if FP arith vectorized	2.25
CQA speedup if fully vectorized	13.87
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.29
Bottlenecks	micro-operation queue,
Function	main
Source	random.tcc:401-406,random.tcc:409-409,random.tcc:413-413,random.tcc:417-420,random.tcc:455-455,random.tcc:459-463,random.tcc:3364-3367
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.50
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	2.00
CQA cycles if fully vectorized	0.32
Front-end cycles	4.50
P0 cycles	3.50
P1 cycles	3.30
P2 cycles	0.67
P3 cycles	0.67
P4 cycles	0.50
P5 cycles	3.40
P6 cycles	3.40
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	3.40
P11 cycles	0.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.00
Nb uops	27.00
Nb loads	2.00
Nb stores	1.00
Nb stack references	1.00
FLOP/cycle	0.67
Nb FLOP add-sub	0.00
Nb FLOP mul	1.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.44
Bytes prefetched	0.00
Bytes loaded	12.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	9.62
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	6.25
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.72

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	random.tcc:401-3367
Module	attention-clang-gnr256

The loop is defined in /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:401-420,455-463,3364-3367.

Analyzed code is defined in /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:401-406,409,413,417-420,455,459-463,3364-3367.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 1 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTUSI2SS: 0 occurrences
VPEXTRQ: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
2: multiply (1 inside FMA instructions)

The binary loop is loading 80 bytes (20 single precision FP elements). The binary loop is storing 24 bytes (6 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	61.50
nb uops	63.50
loop length	295
used x86 registers	7.50
used mmx registers	0
used xmm registers	6
used ymm registers	2.50
used zmm registers	0
nb stack references	5.50

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	10.58 cycles
front end	10.58 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.85	7.70	3.50	3.50	1.50	7.80	7.85	1.50	1.50	1.50	7.80	3.50
cycles	7.85	7.70	3.50	3.50	1.50	7.80	7.85	1.50	1.50	1.50	7.80	3.50

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	10.58
Dispatch	7.90
Data deps.	4.00
Overall L1	10.58

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	6%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	9%
load	9%
store	12%
mul	6%
add-sub	12%
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.58 cycles. At this rate:

3% of peak load performance is reached (5.77 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.09 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	main
Source file and lines	random.tcc:401-3367
Module	attention-clang-gnr256

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.67 to 5.00 cycles (3.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 1 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTUSI2SS: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366
VPEXTRQ: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:404

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
2: multiply (1 inside FMA instructions)

The binary loop is loading 148 bytes (37 single precision FP elements). The binary loop is storing 40 bytes (10 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	97
nb uops	100
loop length	481
used x86 registers	10
used mmx registers	0
used xmm registers	8
used ymm registers	5
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.67 cycles
front end	16.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	12.20	12.10	6.33	6.33	2.50	12.20	12.30	2.50	2.50	2.50	12.20	6.33
cycles	12.20	12.10	6.33	6.33	2.50	12.20	12.30	2.50	2.50	2.50	12.20	6.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	16.67
Dispatch	12.30
Data deps.	4.00
Overall L1	16.67

Vectorization ratios

INT

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	1%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	1%

Vector efficiency ratios

INT

all	10%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	6%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	10%
load	12%
store	12%
mul	6%
add-sub	12%
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.67 cycles. At this rate:

4% of peak load performance is reached (8.88 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 16.67 to 12.30 cycles (1.36x speedup).

ASM code

In the binary file, the address of the loop is: 38e4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,0x17f8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x478(%RSP,%RDX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0xb,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %RDX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %ESI,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x7,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $-0x62d3a980,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0xf,%ESI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
AND $-0x103a0000,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RDX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RSI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x12,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
XOR %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VCVTUSI2SS %RDX,%XMM15,%XMM2	3	0.50	0.50	0	0	0	2	0	0	0	0	0	0	8	2	scal (12.5%)
VFMADD231SS %XMM2,%XMM1,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VMULSS 0x372d(%RIP),%XMM1,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
DEC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 3c40 <main+0xf30>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x270,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JB 3880 <main+0xb70>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPBROADCASTQ %R13,%YMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ 0x3742(%RIP),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x3741(%RIP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x373f(%RIP),%YMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x373d(%RIP),%YMM17	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VEXTRACTI128 $0x1,%YMM2,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPEXTRQ $0x1,%XMM2,%RDI	2	1	0.50	0	0	0	0.50	0	0	0	0	0	0	4	1	scal (12.5%)
AND $-0x80000000,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV 0xb80(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0xb88(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %ESI,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $0x7ffffffe,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
OR %RDI,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
SHR $0x1,%R8	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
XOR 0x17e0(%RSP),%R8	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	scal (12.5%)
MOV %ESI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $0x1,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
NEG %EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
AND %R12D,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %R8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RDI,0xb78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
AND $-0x80000000,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %EDX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $0x7ffffffe,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
OR %RSI,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
SHR $0x1,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
XOR 0x17e8(%RSP),%RDI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	scal (12.5%)
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $0x1,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
NEG %ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
AND %R12D,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RDI,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RSI,0xb80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
AND $-0x80000000,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV 0xb90(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %ESI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
VPBROADCASTQ %RSI,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
AND $0x7ffffffe,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
OR %RDX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
SHR $0x1,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
XOR 0x17f0(%RSP),%RSI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	scal (12.5%)
AND $0x1,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
NEG %EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
AND %R12D,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RSI,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RDI,0xb88(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV $0xe8,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VPBROADCASTQ 0x3545(%RIP),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x3544(%RIP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x3543(%RIP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
VPBROADCASTQ 0x3542(%RIP),%XMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x17f0(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV $-0x80000000,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
AND %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV 0x478(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R13D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
AND $0x7ffffffe,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
OR %RDX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
SHR $0x1,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
XOR 0x10d8(%RSP),%RSI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	scal (12.5%)
MOV %R13D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $0x1,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
NEG %EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
AND %R12D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RDX,0x17f0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 3880 <main+0xb70>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	main
Source file and lines	random.tcc:401-3367
Module	attention-clang-gnr256

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.50 to 4.00 cycles (1.12x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.50 to 0.32 cycles (13.87x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 1 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTUSI2SS: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3366

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

1: addition or subtraction (all inside FMA instructions)
2: multiply (1 inside FMA instructions)

The binary loop is loading 12 bytes (3 single precision FP elements). The binary loop is storing 8 bytes (2 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.

General properties

nb instructions	26
nb uops	27
loop length	109
used x86 registers	5
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.50 cycles
front end	4.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.50	3.30	0.67	0.67	0.50	3.40	3.40	0.50	0.50	0.50	3.40	0.67
cycles	3.50	3.30	0.67	0.67	0.50	3.40	3.40	0.50	0.50	0.50	3.40	0.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	4.50
Dispatch	3.50
Data deps.	4.00
Overall L1	4.50

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	6%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	9%
load	6%
store	12%
mul	6%
add-sub	12%
fma	6%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.50 cycles. At this rate:

1% of peak load performance is reached (2.67 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.78 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 38e4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,0x17f8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x478(%RSP,%RDX,8),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0xb,%RSI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
MOV %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
XOR %RDX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %ESI,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x7,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $-0x62d3a980,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SAL $0xf,%ESI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
AND $-0x103a0000,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RDX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RSI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x12,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
XOR %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VCVTUSI2SS %RDX,%XMM15,%XMM2	3	0.50	0.50	0	0	0	2	0	0	0	0	0	0	8	2	scal (12.5%)
VFMADD231SS %XMM2,%XMM1,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VMULSS 0x372d(%RIP),%XMM1,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	scal (6.3%)
DEC %RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JE 3c40 <main+0xf30>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x270,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JB 3880 <main+0xb70>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

512-bits vectorization

Workaround

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

FMA

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code