OV - attention-clang-gnr256 - Loop 98 - attention-clang-gnr256

	Loop Id: 98	Module: attention-clang-gnr256	Source: attention_v2.cpp:163-164 [...]	Coverage: 0.17%

0x3860 VPXOR	%XMM0,%XMM0,%XMM0

0x3864 MOV	%RAX,%RCX

0x3867 VMOVSS	0x37a5(%RIP),%XMM1

0x386f JMP	38e4

  (99) 0x3880 MOV	%RBX,%RDX

  (99) 0x3883 INC	%RBX

  (99) 0x3886 MOV	%RBX,0x17f8(%RSP)

  (99) 0x388e MOV	0x478(%RSP,%RDX,8),%RDX

  (99) 0x3896 MOV	%RDX,%RSI

  (99) 0x3899 SHR	$0xb,%RSI

  (99) 0x389d MOV	%ESI,%ESI

  (99) 0x389f XOR	%RDX,%RSI

  (99) 0x38a2 MOV	%ESI,%EDX

  (99) 0x38a4 SAL	$0x7,%EDX

  (99) 0x38a7 AND	$-0x62d3a980,%EDX

  (99) 0x38ad XOR	%RSI,%RDX

  (99) 0x38b0 MOV	%EDX,%ESI

  (99) 0x38b2 SAL	$0xf,%ESI

  (99) 0x38b5 AND	$-0x103a0000,%ESI

  (99) 0x38bb XOR	%RDX,%RSI

  (99) 0x38be MOV	%RSI,%RDX

  (99) 0x38c1 SHR	$0x12,%RDX

  (99) 0x38c5 XOR	%RSI,%RDX

  (99) 0x38c8 VCVTUSI2SS	%RDX,%XMM15,%XMM2

  (99) 0x38ce VFMADD231SS	%XMM2,%XMM1,%XMM0

  (99) 0x38d3 VMULSS	0x372d(%RIP),%XMM1,%XMM1

  (99) 0x38db DEC	%RCX

  (99) 0x38de JE	3c40

  (99) 0x38e4 CMP	$0x270,%RBX

  (99) 0x38eb JB	3880

  (99) 0x38ed VPBROADCASTQ	%R13,%YMM2

  (99) 0x38f3 XOR	%EDX,%EDX

  (99) 0x38f5 VPBROADCASTQ	0x3742(%RIP),%YMM14

  (99) 0x38fe VPBROADCASTQ	0x3741(%RIP),%YMM15

  (99) 0x3907 VPBROADCASTQ	0x373f(%RIP),%YMM16

  (99) 0x3911 VPBROADCASTQ	0x373d(%RIP),%YMM17

  (99) 0x391b NOPL	(%RAX,%RAX,1)

    (100) 0x3920 VMOVDQU	0x480(%RSP,%RDX,8),%YMM3

    (100) 0x3929 VMOVDQU	0x4a0(%RSP,%RDX,8),%YMM4

    (100) 0x3932 VMOVDQU	0x4c0(%RSP,%RDX,8),%YMM5

    (100) 0x393b VALIGNQ	$0x3,%YMM2,%YMM3,%YMM6

    (100) 0x3942 VMOVDQU	0x4e0(%RSP,%RDX,8),%YMM2

    (100) 0x394b VALIGNQ	$0x3,%YMM3,%YMM4,%YMM7

    (100) 0x3952 VALIGNQ	$0x3,%YMM4,%YMM5,%YMM8

    (100) 0x3959 VALIGNQ	$0x3,%YMM5,%YMM2,%YMM9

    (100) 0x3960 VPAND	%YMM3,%YMM15,%YMM10

    (100) 0x3964 VPAND	%YMM4,%YMM15,%YMM11

    (100) 0x3968 VPAND	%YMM5,%YMM15,%YMM12

    (100) 0x396c VPAND	%YMM2,%YMM15,%YMM13

    (100) 0x3970 VPTERNLOGQ	$-0x8,%YMM14,%YMM6,%YMM10

    (100) 0x3977 VPTERNLOGQ	$-0x8,%YMM14,%YMM7,%YMM11

    (100) 0x397e VPTERNLOGQ	$-0x8,%YMM14,%YMM8,%YMM12

    (100) 0x3985 VPTERNLOGQ	$-0x8,%YMM14,%YMM9,%YMM13

    (100) 0x398c VPSRLQ	$0x1,%YMM10,%YMM6

    (100) 0x3992 VPSRLQ	$0x1,%YMM11,%YMM7

    (100) 0x3998 VPSRLQ	$0x1,%YMM12,%YMM8

    (100) 0x399e VPSRLQ	$0x1,%YMM13,%YMM9

    (100) 0x39a4 VPXOR	0x10e0(%RSP,%RDX,8),%YMM6,%YMM6

    (100) 0x39ad VPXOR	0x1100(%RSP,%RDX,8),%YMM7,%YMM7

    (100) 0x39b6 VPXOR	0x1120(%RSP,%RDX,8),%YMM8,%YMM8

    (100) 0x39bf VPXOR	0x1140(%RSP,%RDX,8),%YMM9,%YMM9

    (100) 0x39c8 VPTESTMQ	%YMM16,%YMM3,%K1

    (100) 0x39ce VPTESTMQ	%YMM16,%YMM4,%K2

    (100) 0x39d4 VPTESTMQ	%YMM16,%YMM5,%K3

    (100) 0x39da VPTESTMQ	%YMM16,%YMM2,%K4

    (100) 0x39e0 VPXORQ	%YMM17,%YMM6,%YMM6{%K1}

    (100) 0x39e6 VPXORQ	%YMM17,%YMM7,%YMM7{%K2}

    (100) 0x39ec VPXORQ	%YMM17,%YMM8,%YMM8{%K3}

    (100) 0x39f2 VPXORQ	%YMM17,%YMM9,%YMM9{%K4}

    (100) 0x39f8 VMOVDQU	%YMM6,0x478(%RSP,%RDX,8)

    (100) 0x3a01 VMOVDQU	%YMM7,0x498(%RSP,%RDX,8)

    (100) 0x3a0a VMOVDQU	%YMM8,0x4b8(%RSP,%RDX,8)

    (100) 0x3a13 VMOVDQU	%YMM9,0x4d8(%RSP,%RDX,8)

    (100) 0x3a1c ADD	$0x10,%RDX

    (100) 0x3a20 CMP	$0xe0,%RDX

    (100) 0x3a27 JNE	3920

  (99) 0x3a2d VEXTRACTI128	$0x1,%YMM2,%XMM2

  (99) 0x3a33 VPEXTRQ	$0x1,%XMM2,%RDI

  (99) 0x3a39 AND	$-0x80000000,%RDI

  (99) 0x3a40 MOV	0xb80(%RSP),%RSI

  (99) 0x3a48 MOV	0xb88(%RSP),%RDX

  (99) 0x3a50 MOV	%ESI,%R8D

  (99) 0x3a53 AND	$0x7ffffffe,%R8D

  (99) 0x3a5a OR	%RDI,%R8

  (99) 0x3a5d SHR	$0x1,%R8

  (99) 0x3a60 XOR	0x17e0(%RSP),%R8

  (99) 0x3a68 MOV	%ESI,%EDI

  (99) 0x3a6a AND	$0x1,%EDI

  (99) 0x3a6d NEG	%EDI

  (99) 0x3a6f AND	%R12D,%EDI

  (99) 0x3a72 XOR	%R8,%RDI

  (99) 0x3a75 MOV	%RDI,0xb78(%RSP)

  (99) 0x3a7d AND	$-0x80000000,%RSI

  (99) 0x3a84 MOV	%EDX,%EDI

  (99) 0x3a86 AND	$0x7ffffffe,%EDI

  (99) 0x3a8c OR	%RSI,%RDI

  (99) 0x3a8f SHR	$0x1,%RDI

  (99) 0x3a92 XOR	0x17e8(%RSP),%RDI

  (99) 0x3a9a MOV	%EDX,%ESI

  (99) 0x3a9c AND	$0x1,%ESI

  (99) 0x3a9f NEG	%ESI

  (99) 0x3aa1 AND	%R12D,%ESI

  (99) 0x3aa4 XOR	%RDI,%RSI

  (99) 0x3aa7 MOV	%RSI,0xb80(%RSP)

  (99) 0x3aaf AND	$-0x80000000,%RDX

  (99) 0x3ab6 MOV	0xb90(%RSP),%RSI

  (99) 0x3abe MOV	%ESI,%EDI

  (99) 0x3ac0 VPBROADCASTQ	%RSI,%XMM2

  (99) 0x3ac6 AND	$0x7ffffffe,%ESI

  (99) 0x3acc OR	%RDX,%RSI

  (99) 0x3acf SHR	$0x1,%RSI

  (99) 0x3ad2 XOR	0x17f0(%RSP),%RSI

  (99) 0x3ada AND	$0x1,%EDI

  (99) 0x3add NEG	%EDI

  (99) 0x3adf AND	%R12D,%EDI

  (99) 0x3ae2 XOR	%RSI,%RDI

  (99) 0x3ae5 MOV	%RDI,0xb88(%RSP)

  (99) 0x3aed MOV	$0xe8,%EDX

  (99) 0x3af2 VPBROADCASTQ	0x3545(%RIP),%XMM7

  (99) 0x3afb VPBROADCASTQ	0x3544(%RIP),%XMM8

  (99) 0x3b04 VPBROADCASTQ	0x3543(%RIP),%XMM9

  (99) 0x3b0d VPBROADCASTQ	0x3542(%RIP),%XMM10

  (99) 0x3b16 NOPW	%CS:(%RAX,%RAX,1)

    (101) 0x3b20 VMOVDQU	0x458(%RSP,%RDX,8),%XMM3

    (101) 0x3b29 VMOVDQU	0x468(%RSP,%RDX,8),%XMM4

    (101) 0x3b32 VPALIGNR	$0x8,%XMM2,%XMM3,%XMM2

    (101) 0x3b38 VMOVDQU	0x478(%RSP,%RDX,8),%XMM5

    (101) 0x3b41 VPAND	%XMM3,%XMM8,%XMM6

    (101) 0x3b45 VPTERNLOGQ	$-0x8,%XMM7,%XMM2,%XMM6

    (101) 0x3b4c VPSRLQ	$0x1,%XMM6,%XMM2

    (101) 0x3b51 VPXOR	-0x2c8(%RSP,%RDX,8),%XMM2,%XMM2

    (101) 0x3b5a VPTESTMQ	%XMM9,%XMM3,%K1

    (101) 0x3b60 VPXORQ	%XMM10,%XMM2,%XMM2{%K1}

    (101) 0x3b66 VMOVDQU	%XMM2,0x450(%RSP,%RDX,8)

    (101) 0x3b6f VPALIGNR	$0x8,%XMM3,%XMM4,%XMM2

    (101) 0x3b75 VPAND	%XMM4,%XMM8,%XMM3

    (101) 0x3b79 VPTERNLOGQ	$-0x8,%XMM7,%XMM2,%XMM3

    (101) 0x3b80 VPSRLQ	$0x1,%XMM3,%XMM2

    (101) 0x3b85 VPXOR	-0x2b8(%RSP,%RDX,8),%XMM2,%XMM2

    (101) 0x3b8e VPTESTMQ	%XMM9,%XMM4,%K1

    (101) 0x3b94 VPXORQ	%XMM10,%XMM2,%XMM2{%K1}

    (101) 0x3b9a VMOVDQU	%XMM2,0x460(%RSP,%RDX,8)

    (101) 0x3ba3 VPALIGNR	$0x8,%XMM4,%XMM5,%XMM2

    (101) 0x3ba9 VPAND	%XMM5,%XMM8,%XMM3

    (101) 0x3bad VPTERNLOGQ	$-0x8,%XMM7,%XMM2,%XMM3

    (101) 0x3bb4 VPSRLQ	$0x1,%XMM3,%XMM2

    (101) 0x3bb9 VPXOR	-0x2a8(%RSP,%RDX,8),%XMM2,%XMM2

    (101) 0x3bc2 VPTESTMQ	%XMM9,%XMM5,%K1

    (101) 0x3bc8 VPXORQ	%XMM10,%XMM2,%XMM2{%K1}

    (101) 0x3bce VMOVDQU	%XMM2,0x470(%RSP,%RDX,8)

    (101) 0x3bd7 ADD	$0x6,%RDX

    (101) 0x3bdb VMOVDQA	%XMM5,%XMM2

    (101) 0x3bdf CMP	$0x274,%RDX

    (101) 0x3be6 JNE	3b20

  (99) 0x3bec MOV	0x17f0(%RSP),%RDX

  (99) 0x3bf4 MOV	$-0x80000000,%RSI

  (99) 0x3bfb AND	%RSI,%RDX

  (99) 0x3bfe MOV	0x478(%RSP),%R13

  (99) 0x3c06 MOV	%R13D,%ESI

  (99) 0x3c09 AND	$0x7ffffffe,%ESI

  (99) 0x3c0f OR	%RDX,%RSI

  (99) 0x3c12 SHR	$0x1,%RSI

  (99) 0x3c15 XOR	0x10d8(%RSP),%RSI

  (99) 0x3c1d MOV	%R13D,%EDX

  (99) 0x3c20 AND	$0x1,%EDX

  (99) 0x3c23 NEG	%EDX

  (99) 0x3c25 AND	%R12D,%EDX

  (99) 0x3c28 XOR	%RSI,%RDX

  (99) 0x3c2b MOV	%RDX,0x17f0(%RSP)

  (99) 0x3c33 XOR	%EBX,%EBX

  (99) 0x3c35 JMP	3880

0x3c40 VDIVSS	%XMM1,%XMM0,%XMM0

0x3c44 VUCOMISS	0x33c8(%RIP),%XMM0

0x3c4c JAE	3c6a

0x3c4e VMOVSS	%XMM0,(%R14,%R9,4)

0x3c54 INC	%R9

0x3c57 CMP	0x90(%RSP),%R9

0x3c5f JNE	3860

0x3c6a VXORPS	%XMM1,%XMM1,%XMM1

0x3c6e VMOVSS	0x339e(%RIP),%XMM0

0x3c76 MOV	%RAX,0x60(%RSP)

0x3c7b MOV	%R9,0x20(%RSP)

0x3c80 VZEROUPPER

0x3c83 CALL	10a0 <nextafterf@plt>

0x3c88 MOV	0x20(%RSP),%R9

0x3c8d MOV	0x60(%RSP),%RAX

0x3c92 JMP	3c4e

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath: 1661 - 1661

--------------------------------------------------------------------------------

1661:   { return __builtin_nextafterf(__x, __y); }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc: 401 - 3370

--------------------------------------------------------------------------------

401:       for (size_t __k = 0; __k < (__n - __m); ++__k)

402:         {

403: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

404: 			   | (_M_x[__k + 1] & __lower_mask));

405: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

406: 		       ^ ((__y & 0x01) ? __a : 0));

407:         }

408:

409:       for (size_t __k = (__n - __m); __k < (__n - 1); ++__k)

410: 	{

411: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

412: 			   | (_M_x[__k + 1] & __lower_mask));

413: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

414: 		       ^ ((__y & 0x01) ? __a : 0));

415: 	}

416:

417:       _UIntType __y = ((_M_x[__n - 1] & __upper_mask)

418: 		       | (_M_x[0] & __lower_mask));

419:       _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1)

420: 		       ^ ((__y & 0x01) ? __a : 0));

[...]

455:       if (_M_p >= state_size)

456: 	_M_gen_rand();

457:

458:       // Calculate o(x(i)).

459:       result_type __z = _M_x[_M_p++];

460:       __z ^= (__z >> __u) & __d;

461:       __z ^= (__z << __s) & __b;

462:       __z ^= (__z << __t) & __c;

463:       __z ^= (__z >> __l);

[...]

3364:       for (size_t __k = __m; __k != 0; --__k)

3365: 	{

3366: 	  __sum += _RealType(__urng() - __urng.min()) * __tmp;

3367: 	  __tmp *= __r;

3368: 	}

3369:       __ret = __sum / __tmp;

3370:       if (__builtin_expect(__ret >= _RealType(1), 0))

/home/eoseret/llm-attention/attention_v2.cpp: 163 - 164

--------------------------------------------------------------------------------

163:       for (size_t i = 0; i < elemsX; ++i) h_X[i] = dist(rng);

164:       for (size_t i = 0; i < elemsW; ++i) {

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.14
CQA speedup if FP arith vectorized	2.49
CQA speedup if fully vectorized	4.56
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.71
Bottlenecks
Function	main
Source	cmath:1661-1661,random.tcc:3369-3370,attention_v2.cpp:163-164
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.42
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	1.37
CQA cycles if fully vectorized	0.75
Front-end cycles	2.83
P0 cycles	2.00
P1 cycles	0.20
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	1.25
P5 cycles	0.20
P6 cycles	2.00
P7 cycles	1.25
P8 cycles	1.25
P9 cycles	1.25
P10 cycles	0.10
P11 cycles	1.50
DIV/SQRT cycles	3.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	15.50
Nb uops	17.00
Nb loads	4.50
Nb stores	2.00
Nb stack references	2.00
FLOP/cycle	0.29
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.64
Bytes prefetched	0.00
Bytes loaded	26.00
Bytes stored	12.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	20.83
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	46.67
Vector-efficiency ratio all	11.72
Vector-efficiency ratio load	7.03
Vector-efficiency ratio store	8.33
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	16.67

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.82
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P0,
Function	main
Source	cmath:1661-1661,random.tcc:3369-3370,attention_v2.cpp:163-164
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	1.06
CQA cycles if fully vectorized	0.75
Front-end cycles	1.83
P0 cycles	2.00
P1 cycles	0.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	0.50
P5 cycles	0.00
P6 cycles	2.00
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	0.00
P11 cycles	1.00
DIV/SQRT cycles	3.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	11.00
Nb loads	3.00
Nb stores	1.00
Nb stack references	1.00
FLOP/cycle	0.33
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.67
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	16.67
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	33.33
Vector-efficiency ratio all	10.42
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	14.58

Metric	Value
CQA speedup if no scalar integer	1.28
CQA speedup if FP arith vectorized	2.29
CQA speedup if fully vectorized	5.11
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	micro-operation queue,
Function	main
Source	cmath:1661-1661,random.tcc:3369-3370,attention_v2.cpp:163-164
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.83
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	1.68
CQA cycles if fully vectorized	0.75
Front-end cycles	3.83
P0 cycles	2.00
P1 cycles	0.40
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	0.40
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.20
P11 cycles	2.00
DIV/SQRT cycles	3.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.00
Nb uops	23.00
Nb loads	6.00
Nb stores	3.00
Nb stack references	3.00
FLOP/cycle	0.26
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.61
Bytes prefetched	0.00
Bytes loaded	36.00
Bytes stored	20.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	25.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	60.00
Vector-efficiency ratio all	13.02
Vector-efficiency ratio load	7.81
Vector-efficiency ratio store	10.42
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	18.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:163-164
Module	attention-clang-gnr256

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:401-420,455-463,3364-3370
/home/eoseret/llm-attention/attention_v2.cpp:163-164

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.42 to 0.75 cycles (4.56x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.42 to 2.83 cycles (1.21x speedup).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISS: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: divide

The binary loop is loading 26 bytes (6 single precision FP elements). The binary loop is storing 12 bytes (3 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	15.50
nb uops	17
loop length	75
used x86 registers	5
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	2.83 cycles
front end	2.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.00	0.20	1.50	1.50	1.25	0.20	2.00	1.25	1.25	1.25	0.10	1.50
cycles	2.00	0.20	1.50	1.50	1.25	0.20	2.00	1.25	1.25	1.25	0.10	1.50

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	3.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.83
Dispatch	2.00
DIV/SQRT	3.00
Data deps.	1.00
Overall L1	3.42

Vectorization ratios

INT

all	41%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	58%

all	8%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	25%

INT+FP

all	20%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	46%

Vector efficiency ratios

INT

all	17%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	19%

all	7%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

INT+FP

all	11%
load	7%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.42 cycles. At this rate:

3% of peak load performance is reached (7.36 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.28 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	main
Source file and lines	attention_v2.cpp:163-164
Module	attention-clang-gnr256

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:401-420,455-463,3364-3370
/home/eoseret/llm-attention/attention_v2.cpp:163-164

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.75 cycles (4.00x speedup).

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.00 to 2.00 cycles (1.50x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.00 to 1.83 cycles (1.64x speedup).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISS: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: divide

The binary loop is loading 16 bytes (4 single precision FP elements). The binary loop is storing 4 bytes (1 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	11
nb uops	11
loop length	54
used x86 registers	5
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	1.83 cycles
front end	1.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.00	0.00	1.00	1.00	0.50	0.00	2.00	0.50	0.50	0.50	0.00	1.00
cycles	2.00	0.00	1.00	1.00	0.50	0.00	2.00	0.50	0.50	0.50	0.00	1.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	3.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.83
Dispatch	2.00
DIV/SQRT	3.00
Data deps.	1.00
Overall L1	3.00

Vectorization ratios

INT

all	50%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

INT+FP

all	16%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	33%

Vector efficiency ratios

INT

all	18%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	6%

INT+FP

all	10%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

2% of peak load performance is reached (5.33 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 3860

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVSS 0x37a5(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
JMP 38e4 <main+0xbd4>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
VDIVSS %XMM1,%XMM0,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	11-12	3	scal (6.3%)
VUCOMISS 0x33c8(%RIP),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (6.3%)
JAE 3c6a <main+0xf5a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSS %XMM0,(%R14,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
INC %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP 0x90(%RSP),%R9	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JNE 3860 <main+0xb50>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:163-164
Module	attention-clang-gnr256

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:401-420,455-463,3364-3370
/home/eoseret/llm-attention/attention_v2.cpp:163-164

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.83 to 3.00 cycles (1.28x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.83 to 0.75 cycles (5.11x speedup).

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

nextafterf@plt: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VUCOMISS: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:3370
VZEROUPPER: 1 occurrences►
- /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/cmath:1661

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: divide

The binary loop is loading 36 bytes (9 single precision FP elements). The binary loop is storing 20 bytes (5 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	20
nb uops	23
loop length	96
used x86 registers	5
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.83 cycles
front end	3.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.00	0.40	2.00	2.00	2.00	0.40	2.00	2.00	2.00	2.00	0.20	2.00
cycles	2.00	0.40	2.00	2.00	2.00	0.40	2.00	2.00	2.00	2.00	0.20	2.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	3.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.83
Dispatch	2.00
DIV/SQRT	3.00
Data deps.	1.00
Overall L1	3.83

Vectorization ratios

INT

all	33%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	66%

all	16%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	50%

INT+FP

all	25%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	60%

Vector efficiency ratios

INT

all	16%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	9%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	15%

INT+FP

all	13%
load	7%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.83 cycles. At this rate:

4% of peak load performance is reached (9.39 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.22 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 3860

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVSS 0x37a5(%RIP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
JMP 38e4 <main+0xbd4>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
VDIVSS %XMM1,%XMM0,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	11-12	3	scal (6.3%)
VUCOMISS 0x33c8(%RIP),%XMM0	2	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	scal (6.3%)
JAE 3c6a <main+0xf5a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSS %XMM0,(%R14,%R9,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
INC %R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP 0x90(%RSP),%R9	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JNE 3860 <main+0xb50>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVSS 0x339e(%RIP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %RAX,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 10a0 <nextafterf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x20(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x60(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 3c4e <main+0xf3e>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code