OV - attention-clang-gnr256 - Loop 91 - attention-clang-gnr256

	Loop Id: 91	Module: attention-clang-gnr256	Source: random.tcc:412-414	Coverage: 0.04%

0x4760 VMOVDQU	0x458(%RSP,%RCX,8),%XMM3    [1]

0x4769 VMOVDQU	0x468(%RSP,%RCX,8),%XMM4    [1]

0x4772 VPALIGNR	$0x8,%XMM2,%XMM3,%XMM2

0x4778 VMOVDQU	0x478(%RSP,%RCX,8),%XMM5    [1]

0x4781 VPAND	%XMM3,%XMM8,%XMM6

0x4785 VPTERNLOGQ	$-0x8,%XMM7,%XMM2,%XMM6

0x478c VPSRLQ	$0x1,%XMM6,%XMM2

0x4791 VPXOR	-0x2c8(%RSP,%RCX,8),%XMM2,%XMM2    [1]

0x479a VPTESTMQ	%XMM9,%XMM3,%K1

0x47a0 VPXORQ	%XMM10,%XMM2,%XMM2{%K1}

0x47a6 VMOVDQU	%XMM2,0x450(%RSP,%RCX,8)    [1]

0x47af VPALIGNR	$0x8,%XMM3,%XMM4,%XMM2

0x47b5 VPAND	%XMM4,%XMM8,%XMM3

0x47b9 VPTERNLOGQ	$-0x8,%XMM7,%XMM2,%XMM3

0x47c0 VPSRLQ	$0x1,%XMM3,%XMM2

0x47c5 VPXOR	-0x2b8(%RSP,%RCX,8),%XMM2,%XMM2    [1]

0x47ce VPTESTMQ	%XMM9,%XMM4,%K1

0x47d4 VPXORQ	%XMM10,%XMM2,%XMM2{%K1}

0x47da VMOVDQU	%XMM2,0x460(%RSP,%RCX,8)    [1]

0x47e3 VPALIGNR	$0x8,%XMM4,%XMM5,%XMM2

0x47e9 VPAND	%XMM5,%XMM8,%XMM3

0x47ed VPTERNLOGQ	$-0x8,%XMM7,%XMM2,%XMM3

0x47f4 VPSRLQ	$0x1,%XMM3,%XMM2

0x47f9 VPXOR	-0x2a8(%RSP,%RCX,8),%XMM2,%XMM2    [1]

0x4802 VPTESTMQ	%XMM9,%XMM5,%K1

0x4808 VPXORQ	%XMM10,%XMM2,%XMM2{%K1}

0x480e VMOVDQU	%XMM2,0x470(%RSP,%RCX,8)    [1]

0x4817 ADD	$0x6,%RCX

0x481b VMOVDQA	%XMM5,%XMM2

0x481f CMP	$0x274,%RCX

0x4826 JNE	4760

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc: 412 - 414

--------------------------------------------------------------------------------

412: 			   | (_M_x[__k + 1] & __lower_mask));

413: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

414: 		       ^ ((__y & 0x01) ? __a : 0));

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.78
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P0,
Function	main
Source	random.tcc:412-414
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.17
CQA cycles if no scalar integer	7.17
CQA cycles if FP arith vectorized	7.17
CQA cycles if fully vectorized	1.50
Front-end cycles	5.50
P0 cycles	7.17
P1 cycles	6.83
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	1.50
P5 cycles	7.00
P6 cycles	1.00
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	1.50
P10 cycles	0.00
P11 cycles	2.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	30.00
Nb loads	6.00
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.09
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	48.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	89.29
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	86.36
Vector-efficiency ratio all	23.66
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	23.30

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.78
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P0,
Function	main
Source	random.tcc:412-414
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.17
CQA cycles if no scalar integer	7.17
CQA cycles if FP arith vectorized	7.17
CQA cycles if fully vectorized	1.50
Front-end cycles	5.50
P0 cycles	7.17
P1 cycles	6.83
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	1.50
P5 cycles	7.00
P6 cycles	1.00
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	1.50
P10 cycles	0.00
P11 cycles	2.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	30.00
Nb loads	6.00
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.09
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	48.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	89.29
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	86.36
Vector-efficiency ratio all	23.66
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	23.30

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	random.tcc:412-414
Module	attention-clang-gnr256

The loop is defined in /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:412-414.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 23% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 7.17 to 1.50 cycles (4.78x speedup).

Details

89% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

86% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 96 bytes. The binary loop is storing 48 bytes.

General properties

nb instructions	31
nb uops	30
loop length	204
used x86 registers	2
used mmx registers	0
used xmm registers	9
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.50 cycles
front end	5.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.17	6.83	2.00	2.00	1.50	7.00	1.00	1.50	1.50	1.50	0.00	2.00
cycles	7.17	6.83	2.00	2.00	1.50	7.00	1.00	1.50	1.50	1.50	0.00	2.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.50
Dispatch	7.17
Data deps.	1.00
Overall L1	7.17

Vectorization ratios

all	89%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	86%

Vector efficiency ratios

all	23%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.17 cycles. At this rate:

6% of peak load performance is reached (13.40 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.70 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4760

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVDQU 0x458(%RSP,%RCX,8),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVDQU 0x468(%RSP,%RCX,8),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VPALIGNR $0x8,%XMM2,%XMM3,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VMOVDQU 0x478(%RSP,%RCX,8),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VPAND %XMM3,%XMM8,%XMM6	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM7,%XMM2,%XMM6	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM6,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VPXOR -0x2c8(%RSP,%RCX,8),%XMM2,%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VPTESTMQ %XMM9,%XMM3,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPXORQ %XMM10,%XMM2,%XMM2{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVDQU %XMM2,0x450(%RSP,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPALIGNR $0x8,%XMM3,%XMM4,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VPAND %XMM4,%XMM8,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM7,%XMM2,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM3,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VPXOR -0x2b8(%RSP,%RCX,8),%XMM2,%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VPTESTMQ %XMM9,%XMM4,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPXORQ %XMM10,%XMM2,%XMM2{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVDQU %XMM2,0x460(%RSP,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPALIGNR $0x8,%XMM4,%XMM5,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VPAND %XMM5,%XMM8,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM7,%XMM2,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM3,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VPXOR -0x2a8(%RSP,%RCX,8),%XMM2,%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VPTESTMQ %XMM9,%XMM5,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPXORQ %XMM10,%XMM2,%XMM2{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVDQU %XMM2,0x470(%RSP,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
ADD $0x6,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQA %XMM5,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
CMP $0x274,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 4760 <main+0x1a50>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	random.tcc:412-414
Module	attention-clang-gnr256

The loop is defined in /usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc:412-414.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Details

89% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

86% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 96 bytes. The binary loop is storing 48 bytes.

General properties

nb instructions	31
nb uops	30
loop length	204
used x86 registers	2
used mmx registers	0
used xmm registers	9
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.50 cycles
front end	5.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.17	6.83	2.00	2.00	1.50	7.00	1.00	1.50	1.50	1.50	0.00	2.00
cycles	7.17	6.83	2.00	2.00	1.50	7.00	1.00	1.50	1.50	1.50	0.00	2.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.50
Dispatch	7.17
Data deps.	1.00
Overall L1	7.17

Vectorization ratios

all	89%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	86%

Vector efficiency ratios

all	23%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.17 cycles. At this rate:

6% of peak load performance is reached (13.40 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.70 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4760

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVDQU 0x458(%RSP,%RCX,8),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VMOVDQU 0x468(%RSP,%RCX,8),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VPALIGNR $0x8,%XMM2,%XMM3,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VMOVDQU 0x478(%RSP,%RCX,8),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VPAND %XMM3,%XMM8,%XMM6	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM7,%XMM2,%XMM6	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM6,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VPXOR -0x2c8(%RSP,%RCX,8),%XMM2,%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VPTESTMQ %XMM9,%XMM3,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPXORQ %XMM10,%XMM2,%XMM2{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVDQU %XMM2,0x450(%RSP,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPALIGNR $0x8,%XMM3,%XMM4,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VPAND %XMM4,%XMM8,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM7,%XMM2,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM3,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VPXOR -0x2b8(%RSP,%RCX,8),%XMM2,%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VPTESTMQ %XMM9,%XMM4,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPXORQ %XMM10,%XMM2,%XMM2{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVDQU %XMM2,0x460(%RSP,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPALIGNR $0x8,%XMM4,%XMM5,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (12.5%)
VPAND %XMM5,%XMM8,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VPTERNLOGQ $-0x8,%XMM7,%XMM2,%XMM3	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VPSRLQ $0x1,%XMM3,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VPXOR -0x2a8(%RSP,%RCX,8),%XMM2,%XMM2	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VPTESTMQ %XMM9,%XMM5,%K1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VPXORQ %XMM10,%XMM2,%XMM2{%K1}	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	0-1	0.33	vect (25.0%)
VMOVDQU %XMM2,0x470(%RSP,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
ADD $0x6,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQA %XMM5,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
CMP $0x274,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 4760 <main+0x1a50>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Masked instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code