| Loop Id: 90 | Module: attention-clang-gnr256 | Source: random.tcc:404-406 | Coverage: 0.09% |
|---|
| Loop Id: 90 | Module: attention-clang-gnr256 | Source: random.tcc:404-406 | Coverage: 0.09% |
|---|
0x4560 VMOVDQU 0x480(%RSP,%RCX,8),%YMM3 [1] |
0x4569 VMOVDQU 0x4a0(%RSP,%RCX,8),%YMM4 [1] |
0x4572 VMOVDQU 0x4c0(%RSP,%RCX,8),%YMM5 [1] |
0x457b VALIGNQ $0x3,%YMM2,%YMM3,%YMM6 |
0x4582 VMOVDQU 0x4e0(%RSP,%RCX,8),%YMM2 [1] |
0x458b VALIGNQ $0x3,%YMM3,%YMM4,%YMM7 |
0x4592 VALIGNQ $0x3,%YMM4,%YMM5,%YMM8 |
0x4599 VALIGNQ $0x3,%YMM5,%YMM2,%YMM9 |
0x45a0 VPAND %YMM3,%YMM15,%YMM10 |
0x45a4 VPAND %YMM4,%YMM15,%YMM11 |
0x45a8 VPAND %YMM5,%YMM15,%YMM12 |
0x45ac VPAND %YMM2,%YMM15,%YMM13 |
0x45b0 VPTERNLOGQ $-0x8,%YMM14,%YMM6,%YMM10 |
0x45b7 VPTERNLOGQ $-0x8,%YMM14,%YMM7,%YMM11 |
0x45be VPTERNLOGQ $-0x8,%YMM14,%YMM8,%YMM12 |
0x45c5 VPTERNLOGQ $-0x8,%YMM14,%YMM9,%YMM13 |
0x45cc VPSRLQ $0x1,%YMM10,%YMM6 |
0x45d2 VPSRLQ $0x1,%YMM11,%YMM7 |
0x45d8 VPSRLQ $0x1,%YMM12,%YMM8 |
0x45de VPSRLQ $0x1,%YMM13,%YMM9 |
0x45e4 VPXOR 0x10e0(%RSP,%RCX,8),%YMM6,%YMM6 [1] |
0x45ed VPXOR 0x1100(%RSP,%RCX,8),%YMM7,%YMM7 [1] |
0x45f6 VPXOR 0x1120(%RSP,%RCX,8),%YMM8,%YMM8 [1] |
0x45ff VPXOR 0x1140(%RSP,%RCX,8),%YMM9,%YMM9 [1] |
0x4608 VPTESTMQ %YMM16,%YMM3,%K1 |
0x460e VPTESTMQ %YMM16,%YMM4,%K2 |
0x4614 VPTESTMQ %YMM16,%YMM5,%K3 |
0x461a VPTESTMQ %YMM16,%YMM2,%K4 |
0x4620 VPXORQ %YMM17,%YMM6,%YMM6{%K1} |
0x4626 VPXORQ %YMM17,%YMM7,%YMM7{%K2} |
0x462c VPXORQ %YMM17,%YMM8,%YMM8{%K3} |
0x4632 VPXORQ %YMM17,%YMM9,%YMM9{%K4} |
0x4638 VMOVDQU %YMM6,0x478(%RSP,%RCX,8) [1] |
0x4641 VMOVDQU %YMM7,0x498(%RSP,%RCX,8) [1] |
0x464a VMOVDQU %YMM8,0x4b8(%RSP,%RCX,8) [1] |
0x4653 VMOVDQU %YMM9,0x4d8(%RSP,%RCX,8) [1] |
0x465c ADD $0x10,%RCX |
0x4660 CMP $0xe0,%RCX |
0x4667 JNE 4560 |
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc: 404 - 406 |
-------------------------------------------------------------------------------- |
404: | (_M_x[__k + 1] & __lower_mask)); |
405: _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1) |
406: ^ ((__y & 0x01) ? __a : 0)); |
| Coverage (%) | Name | Source Location | Module |
|---|
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 2.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.33 |
| Bottlenecks | P0, P1, P5, |
| Function | main |
| Source | random.tcc:404-406 |
| Source loop unroll info | multi-versionned |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 9.33 |
| CQA cycles if no scalar integer | 9.33 |
| CQA cycles if FP arith vectorized | 9.33 |
| CQA cycles if fully vectorized | 4.67 |
| Front-end cycles | 7.00 |
| P0 cycles | 9.33 |
| P1 cycles | 9.33 |
| P2 cycles | 2.67 |
| P3 cycles | 2.67 |
| P4 cycles | 2.00 |
| P5 cycles | 9.33 |
| P6 cycles | 1.00 |
| P7 cycles | 2.00 |
| P8 cycles | 2.00 |
| P9 cycles | 2.00 |
| P10 cycles | 0.00 |
| P11 cycles | 2.67 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 39.00 |
| Nb uops | 38.00 |
| Nb loads | 8.00 |
| Nb stores | 4.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 41.14 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 256.00 |
| Bytes stored | 128.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 100.00 |
| Vector-efficiency ratio all | 50.00 |
| Vector-efficiency ratio load | 50.00 |
| Vector-efficiency ratio store | 50.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 50.00 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 2.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.33 |
| Bottlenecks | P0, P1, P5, |
| Function | main |
| Source | random.tcc:404-406 |
| Source loop unroll info | multi-versionned |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 9.33 |
| CQA cycles if no scalar integer | 9.33 |
| CQA cycles if FP arith vectorized | 9.33 |
| CQA cycles if fully vectorized | 4.67 |
| Front-end cycles | 7.00 |
| P0 cycles | 9.33 |
| P1 cycles | 9.33 |
| P2 cycles | 2.67 |
| P3 cycles | 2.67 |
| P4 cycles | 2.00 |
| P5 cycles | 9.33 |
| P6 cycles | 1.00 |
| P7 cycles | 2.00 |
| P8 cycles | 2.00 |
| P9 cycles | 2.00 |
| P10 cycles | 0.00 |
| P11 cycles | 2.67 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 39.00 |
| Nb uops | 38.00 |
| Nb loads | 8.00 |
| Nb stores | 4.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 41.14 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 256.00 |
| Bytes stored | 128.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 100.00 |
| Vector-efficiency ratio all | 50.00 |
| Vector-efficiency ratio load | 50.00 |
| Vector-efficiency ratio store | 50.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 50.00 |
| Path / |
| Function | main |
| Source file and lines | random.tcc:404-406 |
| Module | attention-clang-gnr256 |
| nb instructions | 39 |
| nb uops | 38 |
| loop length | 269 |
| used x86 registers | 2 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 16 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 7.00 cycles |
| front end | 7.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 9.33 | 9.33 | 2.67 | 2.67 | 2.00 | 9.33 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 2.67 |
| cycles | 9.33 | 9.33 | 2.67 | 2.67 | 2.00 | 9.33 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 2.67 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 7.00 |
| Dispatch | 9.33 |
| Data deps. | 1.00 |
| Overall L1 | 9.33 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 50% |
| load | 50% |
| store | 50% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 50% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVDQU 0x480(%RSP,%RCX,8),%YMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VMOVDQU 0x4a0(%RSP,%RCX,8),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VMOVDQU 0x4c0(%RSP,%RCX,8),%YMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VALIGNQ $0x3,%YMM2,%YMM3,%YMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VMOVDQU 0x4e0(%RSP,%RCX,8),%YMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VALIGNQ $0x3,%YMM3,%YMM4,%YMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VALIGNQ $0x3,%YMM4,%YMM5,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VALIGNQ $0x3,%YMM5,%YMM2,%YMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VPAND %YMM3,%YMM15,%YMM10 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPAND %YMM4,%YMM15,%YMM11 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPAND %YMM5,%YMM15,%YMM12 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPAND %YMM2,%YMM15,%YMM13 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPTERNLOGQ $-0x8,%YMM14,%YMM6,%YMM10 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPTERNLOGQ $-0x8,%YMM14,%YMM7,%YMM11 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPTERNLOGQ $-0x8,%YMM14,%YMM8,%YMM12 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPTERNLOGQ $-0x8,%YMM14,%YMM9,%YMM13 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPSRLQ $0x1,%YMM10,%YMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 | vect (50.0%) |
| VPSRLQ $0x1,%YMM11,%YMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 | vect (50.0%) |
| VPSRLQ $0x1,%YMM12,%YMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 | vect (50.0%) |
| VPSRLQ $0x1,%YMM13,%YMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 | vect (50.0%) |
| VPXOR 0x10e0(%RSP,%RCX,8),%YMM6,%YMM6 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.40 | vect (50.0%) |
| VPXOR 0x1100(%RSP,%RCX,8),%YMM7,%YMM7 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.40 | vect (50.0%) |
| VPXOR 0x1120(%RSP,%RCX,8),%YMM8,%YMM8 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.40 | vect (50.0%) |
| VPXOR 0x1140(%RSP,%RCX,8),%YMM9,%YMM9 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.40 | vect (50.0%) |
| VPTESTMQ %YMM16,%YMM3,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VPTESTMQ %YMM16,%YMM4,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VPTESTMQ %YMM16,%YMM5,%K3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VPTESTMQ %YMM16,%YMM2,%K4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VPXORQ %YMM17,%YMM6,%YMM6{%K1} | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 | vect (50.0%) |
| VPXORQ %YMM17,%YMM7,%YMM7{%K2} | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 | vect (50.0%) |
| VPXORQ %YMM17,%YMM8,%YMM8{%K3} | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 | vect (50.0%) |
| VPXORQ %YMM17,%YMM9,%YMM9{%K4} | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 | vect (50.0%) |
| VMOVDQU %YMM6,0x478(%RSP,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 | vect (50.0%) |
| VMOVDQU %YMM7,0x498(%RSP,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 | vect (50.0%) |
| VMOVDQU %YMM8,0x4b8(%RSP,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 | vect (50.0%) |
| VMOVDQU %YMM9,0x4d8(%RSP,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 | vect (50.0%) |
| ADD $0x10,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| CMP $0xe0,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| JNE 4560 <main+0x1850> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| Function | main |
| Source file and lines | random.tcc:404-406 |
| Module | attention-clang-gnr256 |
| nb instructions | 39 |
| nb uops | 38 |
| loop length | 269 |
| used x86 registers | 2 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 16 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 7.00 cycles |
| front end | 7.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 9.33 | 9.33 | 2.67 | 2.67 | 2.00 | 9.33 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 2.67 |
| cycles | 9.33 | 9.33 | 2.67 | 2.67 | 2.00 | 9.33 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 2.67 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 7.00 |
| Dispatch | 9.33 |
| Data deps. | 1.00 |
| Overall L1 | 9.33 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 50% |
| load | 50% |
| store | 50% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 50% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVDQU 0x480(%RSP,%RCX,8),%YMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VMOVDQU 0x4a0(%RSP,%RCX,8),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VMOVDQU 0x4c0(%RSP,%RCX,8),%YMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VALIGNQ $0x3,%YMM2,%YMM3,%YMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VMOVDQU 0x4e0(%RSP,%RCX,8),%YMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 | vect (50.0%) |
| VALIGNQ $0x3,%YMM3,%YMM4,%YMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VALIGNQ $0x3,%YMM4,%YMM5,%YMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VALIGNQ $0x3,%YMM5,%YMM2,%YMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VPAND %YMM3,%YMM15,%YMM10 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPAND %YMM4,%YMM15,%YMM11 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPAND %YMM5,%YMM15,%YMM12 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPAND %YMM2,%YMM15,%YMM13 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPTERNLOGQ $-0x8,%YMM14,%YMM6,%YMM10 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPTERNLOGQ $-0x8,%YMM14,%YMM7,%YMM11 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPTERNLOGQ $-0x8,%YMM14,%YMM8,%YMM12 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPTERNLOGQ $-0x8,%YMM14,%YMM9,%YMM13 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 | vect (50.0%) |
| VPSRLQ $0x1,%YMM10,%YMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 | vect (50.0%) |
| VPSRLQ $0x1,%YMM11,%YMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 | vect (50.0%) |
| VPSRLQ $0x1,%YMM12,%YMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 | vect (50.0%) |
| VPSRLQ $0x1,%YMM13,%YMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 | vect (50.0%) |
| VPXOR 0x10e0(%RSP,%RCX,8),%YMM6,%YMM6 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.40 | vect (50.0%) |
| VPXOR 0x1100(%RSP,%RCX,8),%YMM7,%YMM7 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.40 | vect (50.0%) |
| VPXOR 0x1120(%RSP,%RCX,8),%YMM8,%YMM8 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.40 | vect (50.0%) |
| VPXOR 0x1140(%RSP,%RCX,8),%YMM9,%YMM9 | 1 | 0.33 | 0.33 | 0.33 | 0.33 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.40 | vect (50.0%) |
| VPTESTMQ %YMM16,%YMM3,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VPTESTMQ %YMM16,%YMM4,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VPTESTMQ %YMM16,%YMM5,%K3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VPTESTMQ %YMM16,%YMM2,%K4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (50.0%) |
| VPXORQ %YMM17,%YMM6,%YMM6{%K1} | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 | vect (50.0%) |
| VPXORQ %YMM17,%YMM7,%YMM7{%K2} | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 | vect (50.0%) |
| VPXORQ %YMM17,%YMM8,%YMM8{%K3} | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 | vect (50.0%) |
| VPXORQ %YMM17,%YMM9,%YMM9{%K4} | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 | vect (50.0%) |
| VMOVDQU %YMM6,0x478(%RSP,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 | vect (50.0%) |
| VMOVDQU %YMM7,0x498(%RSP,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 | vect (50.0%) |
| VMOVDQU %YMM8,0x4b8(%RSP,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 | vect (50.0%) |
| VMOVDQU %YMM9,0x4d8(%RSP,%RCX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 | vect (50.0%) |
| ADD $0x10,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| CMP $0xe0,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| JNE 4560 <main+0x1850> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
