| Loop Id: 89 | Module: attention-clang-gnr256 | Source: random.tcc:401-3367 [...] | Coverage: 0.09% |
|---|
| Loop Id: 89 | Module: attention-clang-gnr256 | Source: random.tcc:401-3367 [...] | Coverage: 0.09% |
|---|
0x44c0 MOV %RBX,%RCX |
0x44c3 INC %RBX |
0x44c6 MOV %RBX,0x17f8(%RSP) |
0x44ce MOV 0x478(%RSP,%RCX,8),%RCX |
0x44d6 MOV %RCX,%RDX |
0x44d9 SHR $0xb,%RDX |
0x44dd MOV %EDX,%EDX |
0x44df XOR %RCX,%RDX |
0x44e2 MOV %EDX,%ECX |
0x44e4 SAL $0x7,%ECX |
0x44e7 AND $-0x62d3a980,%ECX |
0x44ed XOR %RDX,%RCX |
0x44f0 MOV %ECX,%EDX |
0x44f2 SAL $0xf,%EDX |
0x44f5 AND $-0x103a0000,%EDX |
0x44fb XOR %RCX,%RDX |
0x44fe MOV %RDX,%RCX |
0x4501 SHR $0x12,%RCX |
0x4505 XOR %RDX,%RCX |
0x4508 VCVTUSI2SS %RCX,%XMM15,%XMM2 |
0x450e VFMADD231SS %XMM2,%XMM1,%XMM0 |
0x4513 VMULSS 0x2aed(%RIP),%XMM1,%XMM1 |
0x451b DEC %RAX |
0x451e JE 4880 |
0x4524 CMP $0x270,%RBX |
0x452b JB 44c0 |
0x452d VPBROADCASTQ %R13,%YMM2 |
0x4533 XOR %ECX,%ECX |
0x4535 VPBROADCASTQ 0x2b02(%RIP),%YMM14 |
0x453e VPBROADCASTQ 0x2b01(%RIP),%YMM15 |
0x4547 VPBROADCASTQ 0x2aff(%RIP),%YMM16 |
0x4551 VPBROADCASTQ 0x2afd(%RIP),%YMM17 |
0x455b NOPL (%RAX,%RAX,1) |
(90) 0x4560 VMOVDQU 0x480(%RSP,%RCX,8),%YMM3 |
(90) 0x4569 VMOVDQU 0x4a0(%RSP,%RCX,8),%YMM4 |
(90) 0x4572 VMOVDQU 0x4c0(%RSP,%RCX,8),%YMM5 |
(90) 0x457b VALIGNQ $0x3,%YMM2,%YMM3,%YMM6 |
(90) 0x4582 VMOVDQU 0x4e0(%RSP,%RCX,8),%YMM2 |
(90) 0x458b VALIGNQ $0x3,%YMM3,%YMM4,%YMM7 |
(90) 0x4592 VALIGNQ $0x3,%YMM4,%YMM5,%YMM8 |
(90) 0x4599 VALIGNQ $0x3,%YMM5,%YMM2,%YMM9 |
(90) 0x45a0 VPAND %YMM3,%YMM15,%YMM10 |
(90) 0x45a4 VPAND %YMM4,%YMM15,%YMM11 |
(90) 0x45a8 VPAND %YMM5,%YMM15,%YMM12 |
(90) 0x45ac VPAND %YMM2,%YMM15,%YMM13 |
(90) 0x45b0 VPTERNLOGQ $-0x8,%YMM14,%YMM6,%YMM10 |
(90) 0x45b7 VPTERNLOGQ $-0x8,%YMM14,%YMM7,%YMM11 |
(90) 0x45be VPTERNLOGQ $-0x8,%YMM14,%YMM8,%YMM12 |
(90) 0x45c5 VPTERNLOGQ $-0x8,%YMM14,%YMM9,%YMM13 |
(90) 0x45cc VPSRLQ $0x1,%YMM10,%YMM6 |
(90) 0x45d2 VPSRLQ $0x1,%YMM11,%YMM7 |
(90) 0x45d8 VPSRLQ $0x1,%YMM12,%YMM8 |
(90) 0x45de VPSRLQ $0x1,%YMM13,%YMM9 |
(90) 0x45e4 VPXOR 0x10e0(%RSP,%RCX,8),%YMM6,%YMM6 |
(90) 0x45ed VPXOR 0x1100(%RSP,%RCX,8),%YMM7,%YMM7 |
(90) 0x45f6 VPXOR 0x1120(%RSP,%RCX,8),%YMM8,%YMM8 |
(90) 0x45ff VPXOR 0x1140(%RSP,%RCX,8),%YMM9,%YMM9 |
(90) 0x4608 VPTESTMQ %YMM16,%YMM3,%K1 |
(90) 0x460e VPTESTMQ %YMM16,%YMM4,%K2 |
(90) 0x4614 VPTESTMQ %YMM16,%YMM5,%K3 |
(90) 0x461a VPTESTMQ %YMM16,%YMM2,%K4 |
(90) 0x4620 VPXORQ %YMM17,%YMM6,%YMM6{%K1} |
(90) 0x4626 VPXORQ %YMM17,%YMM7,%YMM7{%K2} |
(90) 0x462c VPXORQ %YMM17,%YMM8,%YMM8{%K3} |
(90) 0x4632 VPXORQ %YMM17,%YMM9,%YMM9{%K4} |
(90) 0x4638 VMOVDQU %YMM6,0x478(%RSP,%RCX,8) |
(90) 0x4641 VMOVDQU %YMM7,0x498(%RSP,%RCX,8) |
(90) 0x464a VMOVDQU %YMM8,0x4b8(%RSP,%RCX,8) |
(90) 0x4653 VMOVDQU %YMM9,0x4d8(%RSP,%RCX,8) |
(90) 0x465c ADD $0x10,%RCX |
(90) 0x4660 CMP $0xe0,%RCX |
(90) 0x4667 JNE 4560 |
0x466d VEXTRACTI128 $0x1,%YMM2,%XMM2 |
0x4673 VPEXTRQ $0x1,%XMM2,%RSI |
0x4679 AND $-0x80000000,%RSI |
0x4680 MOV 0xb80(%RSP),%RDX |
0x4688 MOV 0xb88(%RSP),%RCX |
0x4690 MOV %EDX,%EDI |
0x4692 AND $0x7ffffffe,%EDI |
0x4698 OR %RSI,%RDI |
0x469b SHR $0x1,%RDI |
0x469e XOR 0x17e0(%RSP),%RDI |
0x46a6 MOV %EDX,%ESI |
0x46a8 AND $0x1,%ESI |
0x46ab NEG %ESI |
0x46ad AND %R12D,%ESI |
0x46b0 XOR %RDI,%RSI |
0x46b3 MOV %RSI,0xb78(%RSP) |
0x46bb AND $-0x80000000,%RDX |
0x46c2 MOV %ECX,%ESI |
0x46c4 AND $0x7ffffffe,%ESI |
0x46ca OR %RDX,%RSI |
0x46cd SHR $0x1,%RSI |
0x46d0 XOR 0x17e8(%RSP),%RSI |
0x46d8 MOV %ECX,%EDX |
0x46da AND $0x1,%EDX |
0x46dd NEG %EDX |
0x46df AND %R12D,%EDX |
0x46e2 XOR %RSI,%RDX |
0x46e5 MOV %RDX,0xb80(%RSP) |
0x46ed AND $-0x80000000,%RCX |
0x46f4 MOV 0xb90(%RSP),%RDX |
0x46fc MOV %EDX,%ESI |
0x46fe VPBROADCASTQ %RDX,%XMM2 |
0x4704 AND $0x7ffffffe,%EDX |
0x470a OR %RCX,%RDX |
0x470d SHR $0x1,%RDX |
0x4710 XOR 0x17f0(%RSP),%RDX |
0x4718 AND $0x1,%ESI |
0x471b NEG %ESI |
0x471d AND %R12D,%ESI |
0x4720 XOR %RDX,%RSI |
0x4723 MOV %RSI,0xb88(%RSP) |
0x472b MOV $0xe8,%ECX |
0x4730 VPBROADCASTQ 0x2907(%RIP),%XMM7 |
0x4739 VPBROADCASTQ 0x2906(%RIP),%XMM8 |
0x4742 VPBROADCASTQ 0x2905(%RIP),%XMM9 |
0x474b VPBROADCASTQ 0x2904(%RIP),%XMM10 |
0x4754 NOPW %CS:(%RAX,%RAX,1) |
(91) 0x4760 VMOVDQU 0x458(%RSP,%RCX,8),%XMM3 |
(91) 0x4769 VMOVDQU 0x468(%RSP,%RCX,8),%XMM4 |
(91) 0x4772 VPALIGNR $0x8,%XMM2,%XMM3,%XMM2 |
(91) 0x4778 VMOVDQU 0x478(%RSP,%RCX,8),%XMM5 |
(91) 0x4781 VPAND %XMM3,%XMM8,%XMM6 |
(91) 0x4785 VPTERNLOGQ $-0x8,%XMM7,%XMM2,%XMM6 |
(91) 0x478c VPSRLQ $0x1,%XMM6,%XMM2 |
(91) 0x4791 VPXOR -0x2c8(%RSP,%RCX,8),%XMM2,%XMM2 |
(91) 0x479a VPTESTMQ %XMM9,%XMM3,%K1 |
(91) 0x47a0 VPXORQ %XMM10,%XMM2,%XMM2{%K1} |
(91) 0x47a6 VMOVDQU %XMM2,0x450(%RSP,%RCX,8) |
(91) 0x47af VPALIGNR $0x8,%XMM3,%XMM4,%XMM2 |
(91) 0x47b5 VPAND %XMM4,%XMM8,%XMM3 |
(91) 0x47b9 VPTERNLOGQ $-0x8,%XMM7,%XMM2,%XMM3 |
(91) 0x47c0 VPSRLQ $0x1,%XMM3,%XMM2 |
(91) 0x47c5 VPXOR -0x2b8(%RSP,%RCX,8),%XMM2,%XMM2 |
(91) 0x47ce VPTESTMQ %XMM9,%XMM4,%K1 |
(91) 0x47d4 VPXORQ %XMM10,%XMM2,%XMM2{%K1} |
(91) 0x47da VMOVDQU %XMM2,0x460(%RSP,%RCX,8) |
(91) 0x47e3 VPALIGNR $0x8,%XMM4,%XMM5,%XMM2 |
(91) 0x47e9 VPAND %XMM5,%XMM8,%XMM3 |
(91) 0x47ed VPTERNLOGQ $-0x8,%XMM7,%XMM2,%XMM3 |
(91) 0x47f4 VPSRLQ $0x1,%XMM3,%XMM2 |
(91) 0x47f9 VPXOR -0x2a8(%RSP,%RCX,8),%XMM2,%XMM2 |
(91) 0x4802 VPTESTMQ %XMM9,%XMM5,%K1 |
(91) 0x4808 VPXORQ %XMM10,%XMM2,%XMM2{%K1} |
(91) 0x480e VMOVDQU %XMM2,0x470(%RSP,%RCX,8) |
(91) 0x4817 ADD $0x6,%RCX |
(91) 0x481b VMOVDQA %XMM5,%XMM2 |
(91) 0x481f CMP $0x274,%RCX |
(91) 0x4826 JNE 4760 |
0x482c MOV 0x17f0(%RSP),%RCX |
0x4834 MOV $-0x80000000,%RDX |
0x483b AND %RDX,%RCX |
0x483e MOV 0x478(%RSP),%R13 |
0x4846 MOV %R13D,%EDX |
0x4849 AND $0x7ffffffe,%EDX |
0x484f OR %RCX,%RDX |
0x4852 SHR $0x1,%RDX |
0x4855 XOR 0x10d8(%RSP),%RDX |
0x485d MOV %R13D,%ECX |
0x4860 AND $0x1,%ECX |
0x4863 NEG %ECX |
0x4865 AND %R12D,%ECX |
0x4868 XOR %RDX,%RCX |
0x486b MOV %RCX,0x17f0(%RSP) |
0x4873 XOR %EBX,%EBX |
0x4875 JMP 44c0 |
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/random.tcc: 401 - 3367 |
-------------------------------------------------------------------------------- |
401: for (size_t __k = 0; __k < (__n - __m); ++__k) |
402: { |
403: _UIntType __y = ((_M_x[__k] & __upper_mask) |
404: | (_M_x[__k + 1] & __lower_mask)); |
405: _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1) |
406: ^ ((__y & 0x01) ? __a : 0)); |
407: } |
408: |
409: for (size_t __k = (__n - __m); __k < (__n - 1); ++__k) |
410: { |
411: _UIntType __y = ((_M_x[__k] & __upper_mask) |
412: | (_M_x[__k + 1] & __lower_mask)); |
413: _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1) |
414: ^ ((__y & 0x01) ? __a : 0)); |
415: } |
416: |
417: _UIntType __y = ((_M_x[__n - 1] & __upper_mask) |
418: | (_M_x[0] & __lower_mask)); |
419: _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1) |
420: ^ ((__y & 0x01) ? __a : 0)); |
[...] |
455: if (_M_p >= state_size) |
456: _M_gen_rand(); |
457: |
458: // Calculate o(x(i)). |
459: result_type __z = _M_x[_M_p++]; |
460: __z ^= (__z >> __u) & __d; |
461: __z ^= (__z << __s) & __b; |
462: __z ^= (__z << __t) & __c; |
463: __z ^= (__z >> __l); |
[...] |
3364: for (size_t __k = __m; __k != 0; --__k) |
3365: { |
3366: __sum += _RealType(__urng() - __urng.min()) * __tmp; |
3367: __tmp *= __r; |
| Coverage (%) | Name | Source Location | Module |
|---|
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 2.35 |
| CQA speedup if FP arith vectorized | 1.87 |
| CQA speedup if fully vectorized | 11.93 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.34 |
| Bottlenecks | |
| Function | main |
| Source | random.tcc:401-406,random.tcc:409-409,random.tcc:413-413,random.tcc:417-420,random.tcc:455-455,random.tcc:459-463,random.tcc:3364-3367 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 10.58 |
| CQA cycles if no scalar integer | 4.50 |
| CQA cycles if FP arith vectorized | 5.67 |
| CQA cycles if fully vectorized | 0.89 |
| Front-end cycles | 10.58 |
| P0 cycles | 7.85 |
| P1 cycles | 7.70 |
| P2 cycles | 3.50 |
| P3 cycles | 3.50 |
| P4 cycles | 1.50 |
| P5 cycles | 7.80 |
| P6 cycles | 7.85 |
| P7 cycles | 1.50 |
| P8 cycles | 1.50 |
| P9 cycles | 1.50 |
| P10 cycles | 7.80 |
| P11 cycles | 3.50 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 4 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 61.50 |
| Nb uops | 63.50 |
| Nb loads | 10.50 |
| Nb stores | 3.00 |
| Nb stack references | 5.50 |
| FLOP/cycle | 0.28 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 1.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 7.86 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 80.00 |
| Bytes stored | 24.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 2.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 0.74 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.86 |
| Vector-efficiency ratio all | 9.95 |
| Vector-efficiency ratio load | 9.18 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | 6.25 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | 6.25 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 9.93 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 3.33 |
| CQA speedup if FP arith vectorized | 1.78 |
| CQA speedup if fully vectorized | 11.50 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.36 |
| Bottlenecks | micro-operation queue, |
| Function | main |
| Source | random.tcc:401-406,random.tcc:409-409,random.tcc:413-413,random.tcc:417-420,random.tcc:455-455,random.tcc:459-463,random.tcc:3364-3367 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 16.67 |
| CQA cycles if no scalar integer | 5.00 |
| CQA cycles if FP arith vectorized | 9.34 |
| CQA cycles if fully vectorized | 1.45 |
| Front-end cycles | 16.67 |
| P0 cycles | 12.20 |
| P1 cycles | 12.10 |
| P2 cycles | 6.33 |
| P3 cycles | 6.33 |
| P4 cycles | 2.50 |
| P5 cycles | 12.20 |
| P6 cycles | 12.30 |
| P7 cycles | 2.50 |
| P8 cycles | 2.50 |
| P9 cycles | 2.50 |
| P10 cycles | 12.20 |
| P11 cycles | 6.33 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 4 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 97.00 |
| Nb uops | 100.00 |
| Nb loads | 19.00 |
| Nb stores | 5.00 |
| Nb stack references | 10.00 |
| FLOP/cycle | 0.18 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 1.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 11.28 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 148.00 |
| Bytes stored | 40.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 2.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 1.47 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 1.72 |
| Vector-efficiency ratio all | 10.29 |
| Vector-efficiency ratio load | 12.11 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | 6.25 |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | 6.25 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 10.13 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.13 |
| CQA speedup if FP arith vectorized | 2.25 |
| CQA speedup if fully vectorized | 13.87 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.29 |
| Bottlenecks | micro-operation queue, |
| Function | main |
| Source | random.tcc:401-406,random.tcc:409-409,random.tcc:413-413,random.tcc:417-420,random.tcc:455-455,random.tcc:459-463,random.tcc:3364-3367 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 4.50 |
| CQA cycles if no scalar integer | 4.00 |
| CQA cycles if FP arith vectorized | 2.00 |
| CQA cycles if fully vectorized | 0.32 |
| Front-end cycles | 4.50 |
| P0 cycles | 3.50 |
| P1 cycles | 3.30 |
| P2 cycles | 0.67 |
| P3 cycles | 0.67 |
| P4 cycles | 0.50 |
| P5 cycles | 3.40 |
| P6 cycles | 3.40 |
| P7 cycles | 0.50 |
| P8 cycles | 0.50 |
| P9 cycles | 0.50 |
| P10 cycles | 3.40 |
| P11 cycles | 0.67 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | 4 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 26.00 |
| Nb uops | 27.00 |
| Nb loads | 2.00 |
| Nb stores | 1.00 |
| Nb stack references | 1.00 |
| FLOP/cycle | 0.67 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 1.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 4.44 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 12.00 |
| Bytes stored | 8.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 9.62 |
| Vector-efficiency ratio load | 6.25 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | 6.25 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | 6.25 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 9.72 |
| Path / |
| Function | main |
| Source file and lines | random.tcc:401-3367 |
| Module | attention-clang-gnr256 |
| nb instructions | 61.50 |
| nb uops | 63.50 |
| loop length | 295 |
| used x86 registers | 7 |
| used mmx registers | 0 |
| used xmm registers | 6 |
| used ymm registers | 2.50 |
| used zmm registers | 0 |
| nb stack references | 5.50 |
| micro-operation queue | 10.58 cycles |
| front end | 10.58 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 7.85 | 7.70 | 3.50 | 3.50 | 1.50 | 7.80 | 7.85 | 1.50 | 1.50 | 1.50 | 7.80 | 3.50 |
| cycles | 7.85 | 7.70 | 3.50 | 3.50 | 1.50 | 7.80 | 7.85 | 1.50 | 1.50 | 1.50 | 7.80 | 3.50 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 4.00 |
| Front-end | 10.58 |
| Dispatch | 7.90 |
| Data deps. | 4.00 |
| Overall L1 | 10.58 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 10% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 9% |
| all | 6% |
| load | 6% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 6% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 6% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 9% |
| load | 9% |
| store | 12% |
| mul | 6% |
| add-sub | 12% |
| fma | 6% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 9% |
| Function | main |
| Source file and lines | random.tcc:401-3367 |
| Module | attention-clang-gnr256 |
| nb instructions | 97 |
| nb uops | 100 |
| loop length | 481 |
| used x86 registers | 9 |
| used mmx registers | 0 |
| used xmm registers | 8 |
| used ymm registers | 5 |
| used zmm registers | 0 |
| nb stack references | 10 |
| micro-operation queue | 16.67 cycles |
| front end | 16.67 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 12.20 | 12.10 | 6.33 | 6.33 | 2.50 | 12.20 | 12.30 | 2.50 | 2.50 | 2.50 | 12.20 | 6.33 |
| cycles | 12.20 | 12.10 | 6.33 | 6.33 | 2.50 | 12.20 | 12.30 | 2.50 | 2.50 | 2.50 | 12.20 | 6.33 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 4.00 |
| Front-end | 16.67 |
| Dispatch | 12.30 |
| Data deps. | 4.00 |
| Overall L1 | 16.67 |
| all | 1% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 1% |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 1% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 1% |
| all | 10% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 10% |
| all | 6% |
| load | 6% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 6% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 6% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 10% |
| load | 12% |
| store | 12% |
| mul | 6% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 6% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 10% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV %RBX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| INC %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| MOV %RBX,0x17f8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV 0x478(%RSP,%RCX,8),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV %RCX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| SHR $0xb,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 | scal (12.5%) |
| MOV %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| XOR %RCX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | scal (12.5%) |
| MOV %EDX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| SAL $0x7,%ECX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 | N/A |
| AND $-0x62d3a980,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| XOR %RDX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| MOV %ECX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| SAL $0xf,%EDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 | scal (6.3%) |
| AND $-0x103a0000,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | scal (6.3%) |
| XOR %RCX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | scal (12.5%) |
| MOV %RDX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| SHR $0x12,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 | N/A |
| XOR %RDX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| VCVTUSI2SS %RCX,%XMM15,%XMM2 | 3 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 2 | scal (12.5%) |
| VFMADD231SS %XMM2,%XMM1,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (6.3%) |
| VMULSS 0x2aed(%RIP),%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | scal (6.3%) |
| DEC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| JE 4880 <main+0x1b70> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| CMP $0x270,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| JB 44c0 <main+0x17b0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| VPBROADCASTQ %R13,%YMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | scal (12.5%) |
| XOR %ECX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| VPBROADCASTQ 0x2b02(%RIP),%YMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 | scal (12.5%) |
| VPBROADCASTQ 0x2b01(%RIP),%YMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 | scal (12.5%) |
| VPBROADCASTQ 0x2aff(%RIP),%YMM16 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 | scal (12.5%) |
| VPBROADCASTQ 0x2afd(%RIP),%YMM17 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 | scal (12.5%) |
| NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| VEXTRACTI128 $0x1,%YMM2,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | vect (25.0%) |
| VPEXTRQ $0x1,%XMM2,%RSI | 2 | 1 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 1 | scal (12.5%) |
| AND $-0x80000000,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | scal (12.5%) |
| MOV 0xb80(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| MOV 0xb88(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV %EDX,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| AND $0x7ffffffe,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | scal (6.3%) |
| OR %RSI,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | scal (12.5%) |
| SHR $0x1,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 | scal (12.5%) |
| XOR 0x17e0(%RSP),%RDI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1-2 | 0.33 | scal (12.5%) |
| MOV %EDX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| AND $0x1,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | scal (6.3%) |
| NEG %ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | scal (6.3%) |
| AND %R12D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | scal (6.3%) |
| XOR %RDI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | scal (12.5%) |
| MOV %RSI,0xb78(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| AND $-0x80000000,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | scal (12.5%) |
| MOV %ECX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| AND $0x7ffffffe,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | scal (6.3%) |
| OR %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | scal (12.5%) |
| SHR $0x1,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 | scal (12.5%) |
| XOR 0x17e8(%RSP),%RSI | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1-2 | 0.33 | scal (12.5%) |
| MOV %ECX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| AND $0x1,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | scal (6.3%) |
| NEG %EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | scal (6.3%) |
| AND %R12D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | scal (6.3%) |
| XOR %RSI,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | scal (12.5%) |
| MOV %RDX,0xb80(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| AND $-0x80000000,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| MOV 0xb90(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| MOV %EDX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| VPBROADCASTQ %RDX,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | scal (12.5%) |
| AND $0x7ffffffe,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | scal (6.3%) |
| OR %RCX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | scal (12.5%) |
| SHR $0x1,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 | scal (12.5%) |
| XOR 0x17f0(%RSP),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1-2 | 0.33 | scal (12.5%) |
| AND $0x1,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | scal (6.3%) |
| NEG %ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | scal (6.3%) |
| AND %R12D,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | scal (6.3%) |
| XOR %RDX,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | scal (12.5%) |
| MOV %RSI,0xb88(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV $0xe8,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| VPBROADCASTQ 0x2907(%RIP),%XMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 | scal (12.5%) |
| VPBROADCASTQ 0x2906(%RIP),%XMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 | scal (12.5%) |
| VPBROADCASTQ 0x2905(%RIP),%XMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 | scal (12.5%) |
| VPBROADCASTQ 0x2904(%RIP),%XMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.33 | scal (12.5%) |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV 0x17f0(%RSP),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV $-0x80000000,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | scal (6.3%) |
| AND %RDX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| MOV 0x478(%RSP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| MOV %R13D,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| AND $0x7ffffffe,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | scal (6.3%) |
| OR %RCX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | scal (12.5%) |
| SHR $0x1,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 | scal (12.5%) |
| XOR 0x10d8(%RSP),%RDX | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1-2 | 0.33 | scal (12.5%) |
| MOV %R13D,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| AND $0x1,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| NEG %ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| AND %R12D,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| XOR %RDX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| MOV %RCX,0x17f0(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| XOR %EBX,%EBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| JMP 44c0 <main+0x17b0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 | N/A |
| Function | main |
| Source file and lines | random.tcc:401-3367 |
| Module | attention-clang-gnr256 |
| nb instructions | 26 |
| nb uops | 27 |
| loop length | 109 |
| used x86 registers | 5 |
| used mmx registers | 0 |
| used xmm registers | 4 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 1 |
| micro-operation queue | 4.50 cycles |
| front end | 4.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 3.50 | 3.30 | 0.67 | 0.67 | 0.50 | 3.40 | 3.40 | 0.50 | 0.50 | 0.50 | 3.40 | 0.67 |
| cycles | 3.50 | 3.30 | 0.67 | 0.67 | 0.50 | 3.40 | 3.40 | 0.50 | 0.50 | 0.50 | 3.40 | 0.67 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 4.00 |
| Front-end | 4.50 |
| Dispatch | 3.50 |
| Data deps. | 4.00 |
| Overall L1 | 4.50 |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 10% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 9% |
| all | 6% |
| load | 6% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 6% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 6% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 9% |
| load | 6% |
| store | 12% |
| mul | 6% |
| add-sub | 12% |
| fma | 6% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 9% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV %RBX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| INC %RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| MOV %RBX,0x17f8(%RSP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (12.5%) |
| MOV 0x478(%RSP,%RCX,8),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV %RCX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| SHR $0xb,%RDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 | scal (12.5%) |
| MOV %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| XOR %RCX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | scal (12.5%) |
| MOV %EDX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| SAL $0x7,%ECX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 | N/A |
| AND $-0x62d3a980,%ECX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| XOR %RDX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| MOV %ECX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (6.3%) |
| SAL $0xf,%EDX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 | scal (6.3%) |
| AND $-0x103a0000,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | scal (6.3%) |
| XOR %RCX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | scal (12.5%) |
| MOV %RDX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| SHR $0x12,%RCX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 | N/A |
| XOR %RDX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| VCVTUSI2SS %RCX,%XMM15,%XMM2 | 3 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 8 | 2 | scal (12.5%) |
| VFMADD231SS %XMM2,%XMM1,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 | scal (6.3%) |
| VMULSS 0x2aed(%RIP),%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 | scal (6.3%) |
| DEC %RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| JE 4880 <main+0x1b70> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| CMP $0x270,%RBX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| JB 44c0 <main+0x17b0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
