| Loop Id: 79 | Module: attention-clang-gnr256 | Source: attention_v2.cpp:27-33 | Coverage: 0.66% |
|---|
| Loop Id: 79 | Module: attention-clang-gnr256 | Source: attention_v2.cpp:27-33 | Coverage: 0.66% |
|---|
0x4be0 VCVTSD2SS %XMM0,%XMM0,%XMM0 |
0x4be4 MOV 0x60(%RSP),%RAX |
0x4be9 LEA (%RAX,%R8,1),%R9D |
0x4bed MOV 0xd8(%RSP),%RAX |
0x4bf5 VMOVSS %XMM0,(%RAX,%R9,4) |
0x4bfb INC %R8 |
0x4bfe MOV 0x28(%RSP),%R9 |
0x4c03 CMP %R9,%R8 |
0x4c06 JE 4b8c |
0x4c08 CMP $0x3,%R9D |
0x4c0c JBE 4c28 |
0x4c0e MOV %R8D,%R9D |
0x4c11 ADD 0x98(%RSP),%R9D |
0x4c19 SETB %R9B |
0x4c1d OR 0x20(%RSP),%R9B |
0x4c22 JE 6b47 |
0x4c28 CMPQ $0x3,0x98(%RSP) |
0x4c31 JAE 4c40 |
0x4c33 VXORPS %XMM0,%XMM0,%XMM0 |
0x4c37 XOR %R9D,%R9D |
0x4c3a JMP 4d0a |
0x4c40 VXORPS %XMM0,%XMM0,%XMM0 |
0x4c44 MOV %R8,%R10 |
0x4c47 XOR %R9D,%R9D |
0x4c4a MOV 0x218(%RSP),%RDX |
0x4c52 MOV 0x290(%RSP),%RAX |
0x4c5a MOV 0x220(%RSP),%RDI |
0x4c62 MOV 0x288(%RSP),%RSI |
0x4c6a NOPW (%RAX,%RAX,1) |
(42) 0x4c70 LEA (%RCX,%R9,1),%R11D |
(42) 0x4c74 VMOVSS (%R14,%R11,4),%XMM1 |
(42) 0x4c7a VCVTSS2SD %XMM1,%XMM1,%XMM1 |
(42) 0x4c7e MOV %R10D,%R11D |
(42) 0x4c81 VMOVSS (%R13,%R11,4),%XMM2 |
(42) 0x4c88 VCVTSS2SD %XMM2,%XMM2,%XMM2 |
(42) 0x4c8c VFMADD213SD %XMM0,%XMM1,%XMM2 |
(42) 0x4c91 LEA 0x1(%RCX,%R9,1),%R11D |
(42) 0x4c96 VMOVSS (%R14,%R11,4),%XMM0 |
(42) 0x4c9c VCVTSS2SD %XMM0,%XMM0,%XMM0 |
(42) 0x4ca0 LEA (%RBX,%R10,1),%R11D |
(42) 0x4ca4 VMOVSS (%R13,%R11,4),%XMM1 |
(42) 0x4cab VCVTSS2SD %XMM1,%XMM1,%XMM1 |
(42) 0x4caf LEA 0x2(%RCX,%R9,1),%R11D |
(42) 0x4cb4 VMOVSS (%R14,%R11,4),%XMM3 |
(42) 0x4cba VCVTSS2SD %XMM3,%XMM3,%XMM3 |
(42) 0x4cbe VFMADD213SD %XMM2,%XMM0,%XMM1 |
(42) 0x4cc3 LEA (%RSI,%R10,1),%R11D |
(42) 0x4cc7 VMOVSS (%R13,%R11,4),%XMM0 |
(42) 0x4cce VCVTSS2SD %XMM0,%XMM0,%XMM2 |
(42) 0x4cd2 VFMADD213SD %XMM1,%XMM3,%XMM2 |
(42) 0x4cd7 LEA 0x3(%RCX,%R9,1),%R11D |
(42) 0x4cdc VMOVSS (%R14,%R11,4),%XMM0 |
(42) 0x4ce2 VCVTSS2SD %XMM0,%XMM0,%XMM1 |
(42) 0x4ce6 LEA (%RAX,%R10,1),%R11D |
(42) 0x4cea VMOVSS (%R13,%R11,4),%XMM0 |
(42) 0x4cf1 VCVTSS2SD %XMM0,%XMM0,%XMM0 |
(42) 0x4cf5 VFMADD213SD %XMM2,%XMM1,%XMM0 |
(42) 0x4cfa ADD $0x4,%R9 |
(42) 0x4cfe ADD %RDI,%R10 |
(42) 0x4d01 CMP %R9,%RDX |
(42) 0x4d04 JNE 4c70 |
0x4d0a TEST $0x3,%BL |
0x4d0d JE 4be0 |
0x4d13 MOV %RBX,%R10 |
0x4d16 IMUL %R9,%R10 |
0x4d1a ADD %R8,%R10 |
0x4d1d ADD %ECX,%R9D |
0x4d20 MOV 0x1a0(%RSP),%R11 |
0x4d28 NOPL (%RAX,%RAX,1) |
(80) 0x4d30 MOV %R9D,%EBX |
(80) 0x4d33 VMOVSS (%R14,%RBX,4),%XMM1 |
(80) 0x4d39 VCVTSS2SD %XMM1,%XMM1,%XMM1 |
(80) 0x4d3d MOV %R10D,%EBX |
(80) 0x4d40 VMOVSS (%R13,%RBX,4),%XMM2 |
(80) 0x4d47 MOV 0x38(%RSP),%RBX |
(80) 0x4d4c VCVTSS2SD %XMM2,%XMM2,%XMM2 |
(80) 0x4d50 VFMADD231SD %XMM2,%XMM1,%XMM0 |
(80) 0x4d55 ADD %RBX,%R10 |
(80) 0x4d58 INC %R9D |
(80) 0x4d5b DEC %R11 |
(80) 0x4d5e JNE 4d30 |
0x4d60 JMP 4be0 |
/home/eoseret/llm-attention/attention_v2.cpp: 27 - 33 |
-------------------------------------------------------------------------------- |
27: for (unsigned int j = 0; j < N; ++j) { //vectorized |
28: double sum = 0.0; |
29: #pragma clang loop vectorize(enable) |
30: for (unsigned int k = 0; k < K; ++k) { //vectorized |
31: sum += (double)A[i * K + k] * (double)B[k * N + j]; |
32: } |
33: C[i * N + j] = alpha * static_cast<float>(sum); |
| Coverage (%) | Name | Source Location | Module |
|---|
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| min | med | avg | max |
|---|---|---|---|
| Percentile Index | 10 | 20 | 30 | 40 | 50 | 60 | 70 | 80 | 90 | 100 |
|---|---|---|---|---|---|---|---|---|---|---|
| Value |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 2.17 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 12.94 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.76 |
| Bottlenecks | micro-operation queue, |
| Function | main |
| Source | attention_v2.cpp:27-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 6.50 |
| CQA cycles if no scalar integer | 3.00 |
| CQA cycles if FP arith vectorized | 6.50 |
| CQA cycles if fully vectorized | 0.50 |
| Front-end cycles | 6.50 |
| P0 cycles | 3.70 |
| P1 cycles | 3.60 |
| P2 cycles | 3.67 |
| P3 cycles | 3.67 |
| P4 cycles | 0.50 |
| P5 cycles | 3.60 |
| P6 cycles | 3.50 |
| P7 cycles | 0.50 |
| P8 cycles | 0.50 |
| P9 cycles | 0.50 |
| P10 cycles | 3.60 |
| P11 cycles | 3.67 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 38.00 |
| Nb uops | 39.00 |
| Nb loads | 11.00 |
| Nb stores | 1.00 |
| Nb stack references | 10.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 12.46 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 77.00 |
| Bytes stored | 4.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 13.33 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 25.00 |
| Vector-efficiency ratio all | 13.33 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 6.25 |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 14.84 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 2.17 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 12.94 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.76 |
| Bottlenecks | micro-operation queue, |
| Function | main |
| Source | attention_v2.cpp:27-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 6.50 |
| CQA cycles if no scalar integer | 3.00 |
| CQA cycles if FP arith vectorized | 6.50 |
| CQA cycles if fully vectorized | 0.50 |
| Front-end cycles | 6.50 |
| P0 cycles | 3.70 |
| P1 cycles | 3.60 |
| P2 cycles | 3.67 |
| P3 cycles | 3.67 |
| P4 cycles | 0.50 |
| P5 cycles | 3.60 |
| P6 cycles | 3.50 |
| P7 cycles | 0.50 |
| P8 cycles | 0.50 |
| P9 cycles | 0.50 |
| P10 cycles | 3.60 |
| P11 cycles | 3.67 |
| DIV/SQRT cycles | 0.00 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 38.00 |
| Nb uops | 39.00 |
| Nb loads | 11.00 |
| Nb stores | 1.00 |
| Nb stack references | 10.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 12.46 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 77.00 |
| Bytes stored | 4.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 13.33 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 25.00 |
| Vector-efficiency ratio all | 13.33 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 6.25 |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 14.84 |
| Path / |
| Function | main |
| Source file and lines | attention_v2.cpp:27-33 |
| Module | attention-clang-gnr256 |
| nb instructions | 38 |
| nb uops | 39 |
| loop length | 186 |
| used x86 registers | 11 |
| used mmx registers | 0 |
| used xmm registers | 1 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 10 |
| micro-operation queue | 6.50 cycles |
| front end | 6.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 3.70 | 3.60 | 3.67 | 3.67 | 0.50 | 3.60 | 3.50 | 0.50 | 0.50 | 0.50 | 3.60 | 3.67 |
| cycles | 3.70 | 3.60 | 3.67 | 3.67 | 0.50 | 3.60 | 3.50 | 0.50 | 0.50 | 0.50 | 3.60 | 3.67 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 6.50 |
| Dispatch | 3.70 |
| Overall L1 | 6.50 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 50% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 66% |
| all | 13% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
| all | 11% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 11% |
| all | 17% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 6% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 20% |
| all | 13% |
| load | 12% |
| store | 6% |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 14% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VCVTSD2SS %XMM0,%XMM0,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | scal (12.5%) |
| MOV 0x60(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| LEA (%RAX,%R8,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| MOV 0xd8(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| VMOVSS %XMM0,(%RAX,%R9,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| INC %R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| MOV 0x28(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| CMP %R9,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | scal (12.5%) |
| JE 4b8c <main+0x1e7c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| CMP $0x3,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | scal (6.3%) |
| JBE 4c28 <main+0x1f18> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| MOV %R8D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ADD 0x98(%RSP),%R9D | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | N/A |
| SETB %R9B | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| OR 0x20(%RSP),%R9B | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1-2 | 0.33 | N/A |
| JE 6b47 <main+0x3e37> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| CMPQ $0x3,0x98(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | scal (12.5%) |
| JAE 4c40 <main+0x1f30> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| VXORPS %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| XOR %R9D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| JMP 4d0a <main+0x1ffa> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 | N/A |
| VXORPS %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| MOV %R8,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| XOR %R9D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV 0x218(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| MOV 0x290(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV 0x220(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| MOV 0x288(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| TEST $0x3,%BL | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 | N/A |
| JE 4be0 <main+0x1ed0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| MOV %RBX,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| IMUL %R9,%R10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | scal (12.5%) |
| ADD %R8,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | scal (12.5%) |
| ADD %ECX,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV 0x1a0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| JMP 4be0 <main+0x1ed0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 | N/A |
| Function | main |
| Source file and lines | attention_v2.cpp:27-33 |
| Module | attention-clang-gnr256 |
| nb instructions | 38 |
| nb uops | 39 |
| loop length | 186 |
| used x86 registers | 11 |
| used mmx registers | 0 |
| used xmm registers | 1 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 10 |
| micro-operation queue | 6.50 cycles |
| front end | 6.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 3.70 | 3.60 | 3.67 | 3.67 | 0.50 | 3.60 | 3.50 | 0.50 | 0.50 | 0.50 | 3.60 | 3.67 |
| cycles | 3.70 | 3.60 | 3.67 | 3.67 | 0.50 | 3.60 | 3.50 | 0.50 | 0.50 | 0.50 | 3.60 | 3.67 |
| Cycles executing div or sqrt instructions | NA |
| Front-end | 6.50 |
| Dispatch | 3.70 |
| Overall L1 | 6.50 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 50% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 66% |
| all | 13% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
| all | 11% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 11% |
| all | 17% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 6% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 20% |
| all | 13% |
| load | 12% |
| store | 6% |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 14% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput | Vectorization |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VCVTSD2SS %XMM0,%XMM0,%XMM0 | 2 | 0.50 | 0.50 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 5 | 1 | scal (12.5%) |
| MOV 0x60(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| LEA (%RAX,%R8,1),%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 | N/A |
| MOV 0xd8(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| VMOVSS %XMM0,(%RAX,%R9,4) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 | scal (6.3%) |
| INC %R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| MOV 0x28(%RSP),%R9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| CMP %R9,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | scal (12.5%) |
| JE 4b8c <main+0x1e7c> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| CMP $0x3,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | scal (6.3%) |
| JBE 4c28 <main+0x1f18> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| MOV %R8D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | N/A |
| ADD 0x98(%RSP),%R9D | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | N/A |
| SETB %R9B | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 | N/A |
| OR 0x20(%RSP),%R9B | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1-2 | 0.33 | N/A |
| JE 6b47 <main+0x3e37> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| CMPQ $0x3,0x98(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 | scal (12.5%) |
| JAE 4c40 <main+0x1f30> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| VXORPS %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| XOR %R9D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| JMP 4d0a <main+0x1ffa> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 | N/A |
| VXORPS %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | vect (25.0%) |
| MOV %R8,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| XOR %R9D,%R9D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| MOV 0x218(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| MOV 0x290(%RSP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | N/A |
| MOV 0x220(%RSP),%RDI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| MOV 0x288(%RSP),%RSI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| TEST $0x3,%BL | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 | N/A |
| JE 4be0 <main+0x1ed0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | N/A |
| MOV %RBX,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 | scal (12.5%) |
| IMUL %R9,%R10 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 | scal (12.5%) |
| ADD %R8,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | scal (12.5%) |
| ADD %ECX,%R9D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 | N/A |
| MOV 0x1a0(%RSP),%R11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 | scal (12.5%) |
| NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 | N/A |
| JMP 4be0 <main+0x1ed0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 | N/A |
