OV - attention-clang-gnr256 - Loop 78 - attention-clang-gnr256

0x4b8c MOV	0x160(%RSP),%EAX

0x4b93 INC	%EAX

0x4b95 ADD	%RBX,%RCX

0x4b98 CMP	0x50(%RSP),%EAX

0x4b9c JE	4d65

0x4ba2 CMP	$0x1,%RBX

0x4ba6 SETNE	%R8B

0x4baa MOV	%EAX,0x160(%RSP)

0x4bb1 IMUL	%EBX,%EAX

0x4bb4 MOV	%RAX,0x60(%RSP)

0x4bb9 MOV	%EAX,%EDI

0x4bbb ADD	0x98(%RSP),%EDI

0x4bc2 SETB	%AL

0x4bc5 OR	%R8B,%AL

0x4bc8 MOV	%AL,0x20(%RSP)

0x4bcc XOR	%R8D,%R8D

0x4bcf MOV	0x28(%RSP),%R9

0x4bd4 JMP	4c08

  (79) 0x4be0 VCVTSD2SS	%XMM0,%XMM0,%XMM0

  (79) 0x4be4 MOV	0x60(%RSP),%RAX

  (79) 0x4be9 LEA	(%RAX,%R8,1),%R9D

  (79) 0x4bed MOV	0xd8(%RSP),%RAX

  (79) 0x4bf5 VMOVSS	%XMM0,(%RAX,%R9,4)

  (79) 0x4bfb INC	%R8

  (79) 0x4bfe MOV	0x28(%RSP),%R9

  (79) 0x4c03 CMP	%R9,%R8

  (79) 0x4c06 JE	4b8c

  (79) 0x4c08 CMP	$0x3,%R9D

  (79) 0x4c0c JBE	4c28

  (79) 0x4c0e MOV	%R8D,%R9D

  (79) 0x4c11 ADD	0x98(%RSP),%R9D

  (79) 0x4c19 SETB	%R9B

  (79) 0x4c1d OR	0x20(%RSP),%R9B

  (79) 0x4c22 JE	6b47

  (79) 0x4c28 CMPQ	$0x3,0x98(%RSP)

  (79) 0x4c31 JAE	4c40

  (79) 0x4c33 VXORPS	%XMM0,%XMM0,%XMM0

  (79) 0x4c37 XOR	%R9D,%R9D

  (79) 0x4c3a JMP	4d0a

  (79) 0x4c40 VXORPS	%XMM0,%XMM0,%XMM0

  (79) 0x4c44 MOV	%R8,%R10

  (79) 0x4c47 XOR	%R9D,%R9D

  (79) 0x4c4a MOV	0x218(%RSP),%RDX

  (79) 0x4c52 MOV	0x290(%RSP),%RAX

  (79) 0x4c5a MOV	0x220(%RSP),%RDI

  (79) 0x4c62 MOV	0x288(%RSP),%RSI

  (79) 0x4c6a NOPW	(%RAX,%RAX,1)

    (42) 0x4c70 LEA	(%RCX,%R9,1),%R11D

    (42) 0x4c74 VMOVSS	(%R14,%R11,4),%XMM1

    (42) 0x4c7a VCVTSS2SD	%XMM1,%XMM1,%XMM1

    (42) 0x4c7e MOV	%R10D,%R11D

    (42) 0x4c81 VMOVSS	(%R13,%R11,4),%XMM2

    (42) 0x4c88 VCVTSS2SD	%XMM2,%XMM2,%XMM2

    (42) 0x4c8c VFMADD213SD	%XMM0,%XMM1,%XMM2

    (42) 0x4c91 LEA	0x1(%RCX,%R9,1),%R11D

    (42) 0x4c96 VMOVSS	(%R14,%R11,4),%XMM0

    (42) 0x4c9c VCVTSS2SD	%XMM0,%XMM0,%XMM0

    (42) 0x4ca0 LEA	(%RBX,%R10,1),%R11D

    (42) 0x4ca4 VMOVSS	(%R13,%R11,4),%XMM1

    (42) 0x4cab VCVTSS2SD	%XMM1,%XMM1,%XMM1

    (42) 0x4caf LEA	0x2(%RCX,%R9,1),%R11D

    (42) 0x4cb4 VMOVSS	(%R14,%R11,4),%XMM3

    (42) 0x4cba VCVTSS2SD	%XMM3,%XMM3,%XMM3

    (42) 0x4cbe VFMADD213SD	%XMM2,%XMM0,%XMM1

    (42) 0x4cc3 LEA	(%RSI,%R10,1),%R11D

    (42) 0x4cc7 VMOVSS	(%R13,%R11,4),%XMM0

    (42) 0x4cce VCVTSS2SD	%XMM0,%XMM0,%XMM2

    (42) 0x4cd2 VFMADD213SD	%XMM1,%XMM3,%XMM2

    (42) 0x4cd7 LEA	0x3(%RCX,%R9,1),%R11D

    (42) 0x4cdc VMOVSS	(%R14,%R11,4),%XMM0

    (42) 0x4ce2 VCVTSS2SD	%XMM0,%XMM0,%XMM1

    (42) 0x4ce6 LEA	(%RAX,%R10,1),%R11D

    (42) 0x4cea VMOVSS	(%R13,%R11,4),%XMM0

    (42) 0x4cf1 VCVTSS2SD	%XMM0,%XMM0,%XMM0

    (42) 0x4cf5 VFMADD213SD	%XMM2,%XMM1,%XMM0

    (42) 0x4cfa ADD	$0x4,%R9

    (42) 0x4cfe ADD	%RDI,%R10

    (42) 0x4d01 CMP	%R9,%RDX

    (42) 0x4d04 JNE	4c70

  (79) 0x4d0a TEST	$0x3,%BL

  (79) 0x4d0d JE	4be0

  (79) 0x4d13 MOV	%RBX,%R10

  (79) 0x4d16 IMUL	%R9,%R10

  (79) 0x4d1a ADD	%R8,%R10

  (79) 0x4d1d ADD	%ECX,%R9D

  (79) 0x4d20 MOV	0x1a0(%RSP),%R11

  (79) 0x4d28 NOPL	(%RAX,%RAX,1)

    (80) 0x4d30 MOV	%R9D,%EBX

    (80) 0x4d33 VMOVSS	(%R14,%RBX,4),%XMM1

    (80) 0x4d39 VCVTSS2SD	%XMM1,%XMM1,%XMM1

    (80) 0x4d3d MOV	%R10D,%EBX

    (80) 0x4d40 VMOVSS	(%R13,%RBX,4),%XMM2

    (80) 0x4d47 MOV	0x38(%RSP),%RBX

    (80) 0x4d4c VCVTSS2SD	%XMM2,%XMM2,%XMM2

    (80) 0x4d50 VFMADD231SD	%XMM2,%XMM1,%XMM0

    (80) 0x4d55 ADD	%RBX,%R10

    (80) 0x4d58 INC	%R9D

    (80) 0x4d5b DEC	%R11

    (80) 0x4d5e JNE	4d30

  (79) 0x4d60 JMP	4be0

/home/eoseret/llm-attention/attention_v2.cpp: 26 - 194

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

[...]

194:       start = std::chrono::steady_clock::now();

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.09
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.36
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-26,attention_v2.cpp:194-194
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.23
Front-end cycles	3.00
P0 cycles	2.10
P1 cycles	2.20
P2 cycles	1.33
P3 cycles	1.33
P4 cycles	1.50
P5 cycles	2.00
P6 cycles	1.90
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	1.50
P10 cycles	2.00
P11 cycles	1.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.00
Nb uops	18.00
Nb loads	4.00
Nb stores	3.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.00
Bytes prefetched	0.00
Bytes loaded	20.00
Bytes stored	13.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	8.75
Vector-efficiency ratio load	8.33
Vector-efficiency ratio store	9.38
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	9.38
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.33

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.09
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.36
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-26,attention_v2.cpp:194-194
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.23
Front-end cycles	3.00
P0 cycles	2.10
P1 cycles	2.20
P2 cycles	1.33
P3 cycles	1.33
P4 cycles	1.50
P5 cycles	2.00
P6 cycles	1.90
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	1.50
P10 cycles	2.00
P11 cycles	1.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.00
Nb uops	18.00
Nb loads	4.00
Nb stores	3.00
Nb stack references	6.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.00
Bytes prefetched	0.00
Bytes loaded	20.00
Bytes stored	13.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	8.75
Vector-efficiency ratio load	8.33
Vector-efficiency ratio store	9.38
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	9.38
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.33

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:26-194
Module	attention-clang-gnr256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-33,194.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:26,194.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 5 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.23 cycles (13.09x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 20 bytes. The binary loop is storing 13 bytes.

General properties

nb instructions	18
nb uops	18
loop length	74
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.00 cycles
front end	3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.10	2.00	1.33	1.33	1.50	2.00	1.90	1.50	1.50	1.50	2.00	1.33
cycles	2.10	2.20	1.33	1.33	1.50	2.00	1.90	1.50	1.50	1.50	2.00	1.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.00
Dispatch	2.20
Overall L1	3.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	8%
store	9%
mul	6%
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

3% of peak load performance is reached (6.67 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.00 to 2.20 cycles (1.36x speedup).

ASM code

In the binary file, the address of the loop is: 4ba2

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV 0x160(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
ADD %RBX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMP 0x50(%RSP),%EAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JE 4d65 <main+0x2055>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
SETNE %R8B	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV %EAX,0x160(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
IMUL %EBX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
MOV %RAX,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD 0x98(%RSP),%EDI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
SETB %AL	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
OR %R8B,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %AL,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV 0x28(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 4c08 <main+0x1ef8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

Function	main
Source file and lines	attention_v2.cpp:26-194
Module	attention-clang-gnr256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-33,194.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:26,194.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 5 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.23 cycles (13.09x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 20 bytes. The binary loop is storing 13 bytes.

General properties

nb instructions	18
nb uops	18
loop length	74
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.00 cycles
front end	3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.10	2.00	1.33	1.33	1.50	2.00	1.90	1.50	1.50	1.50	2.00	1.33
cycles	2.10	2.20	1.33	1.33	1.50	2.00	1.90	1.50	1.50	1.50	2.00	1.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.00
Dispatch	2.20
Overall L1	3.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	8%
store	9%
mul	6%
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

3% of peak load performance is reached (6.67 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.00 to 2.20 cycles (1.36x speedup).

ASM code

In the binary file, the address of the loop is: 4ba2

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV 0x160(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
ADD %RBX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMP 0x50(%RSP),%EAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JE 4d65 <main+0x2055>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
SETNE %R8B	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
MOV %EAX,0x160(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
IMUL %EBX,%EAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
MOV %RAX,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD 0x98(%RSP),%EDI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
SETB %AL	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
OR %R8B,%AL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %AL,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV 0x28(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 4c08 <main+0x1ef8>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code