OV - attention-clang-gnr256 - Loop 63 - attention-clang-gnr256

	Loop Id: 63	Module: attention-clang-gnr256	Source: attention_v2.cpp:27-33	Coverage: 5.29%

0x5351 VCVTSD2SS	%XMM0,%XMM0,%XMM0

0x5355 VDIVSS	0x29c(%RSP),%XMM0,%XMM0

0x535e MOV	0x20(%RSP),%RCX

0x5363 MOV	0x60(%RSP),%RDI

0x5368 LEA	(%RCX,%RDI,1),%R8D

0x536c MOV	0xf8(%RSP),%RCX

0x5374 VMOVSS	%XMM0,(%RCX,%R8,4)

0x537a INC	%RDI

0x537d MOV	0x88(%RSP),%R13

0x5385 CMP	%R13,%RDI

0x5388 JE	5306

0x538e VPXOR	%XMM0,%XMM0,%XMM0

0x5392 CMPL	$0x4,0x28(%RSP)

0x5397 MOV	%RDI,0x60(%RSP)

0x539c JB	53bb

0x539e MOV	%EDI,%R8D

0x53a1 ADD	0x98(%RSP),%R8D

0x53a9 SETB	%R8B

0x53ad OR	0x160(%RSP),%R8B

0x53b5 JE	5521

0x53bb XOR	%R9D,%R9D

0x53be TESTB	$0x3,0x38(%RSP)

0x53c3 JE	541b

0x53c5 MOV	0x50(%RSP),%R13

0x53ca MOV	%R13,%R10

0x53cd IMUL	%R9,%R10

0x53d1 ADD	0x60(%RSP),%R10

0x53d6 MOV	0x1a0(%RSP),%R11

0x53de MOV	%R9,%R8

0x53e1 MOV	0x58(%RSP),%RSI

0x53e6 MOV	0x30(%RSP),%RDI

0x53eb NOPL	(%RAX,%RAX,1)

  (65) 0x53f0 LEA	(%RAX,%R8,1),%EBX

  (65) 0x53f4 VMOVSS	(%RSI,%RBX,4),%XMM1

  (65) 0x53f9 VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (65) 0x53fd MOV	%R10D,%EBX

  (65) 0x5400 VMOVSS	(%RDI,%RBX,4),%XMM2

  (65) 0x5405 VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (65) 0x5409 VFMADD231SD	%XMM2,%XMM1,%XMM0

  (65) 0x540e INC	%R8

  (65) 0x5411 ADD	%R13,%R10

  (65) 0x5414 DEC	%R11

  (65) 0x5417 JNE	53f0

0x5419 JMP	5428

0x541b MOV	%R9,%R8

0x541e MOV	0x58(%RSP),%RSI

0x5423 MOV	0x30(%RSP),%RDI

0x5428 MOV	0x28(%RSP),%RCX

0x542d SUB	%RCX,%R9

0x5430 CMP	$-0x4,%R9

0x5434 MOV	0x378(%RSP),%RDX

0x543c JA	5351

0x5442 LEA	0x3(%R8),%R9

0x5446 MOV	0x50(%RSP),%R13

0x544b IMUL	%R13,%R9

0x544f MOV	0x60(%RSP),%RBX

0x5454 ADD	%RBX,%R9

0x5457 LEA	0x2(%R8),%R10

0x545b IMUL	%R13,%R10

0x545f ADD	%RBX,%R10

0x5462 MOV	%R13,%R11

0x5465 IMUL	%R8,%R11

0x5469 ADD	%RBX,%R11

0x546c LEA	0x1(%R8),%RBX

0x5470 IMUL	%R13,%RBX

0x5474 ADD	0x60(%RSP),%RBX

0x5479 NOPL	(%RAX)

  (64) 0x5480 LEA	(%RAX,%R8,1),%R13D

  (64) 0x5484 VMOVSS	(%RSI,%R13,4),%XMM1

  (64) 0x548a VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (64) 0x548e MOV	%R11D,%R13D

  (64) 0x5491 VMOVSS	(%RDI,%R13,4),%XMM2

  (64) 0x5497 VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (64) 0x549b LEA	0x1(%RAX,%R8,1),%R13D

  (64) 0x54a0 VMOVSS	(%RSI,%R13,4),%XMM3

  (64) 0x54a6 VCVTSS2SD	%XMM3,%XMM3,%XMM3

  (64) 0x54aa VFMADD213SD	%XMM0,%XMM1,%XMM2

  (64) 0x54af MOV	%EBX,%R13D

  (64) 0x54b2 VMOVSS	(%RDI,%R13,4),%XMM0

  (64) 0x54b8 VCVTSS2SD	%XMM0,%XMM0,%XMM0

  (64) 0x54bc VFMADD213SD	%XMM2,%XMM3,%XMM0

  (64) 0x54c1 LEA	0x2(%RAX,%R8,1),%R13D

  (64) 0x54c6 VMOVSS	(%RSI,%R13,4),%XMM1

  (64) 0x54cc VCVTSS2SD	%XMM1,%XMM1,%XMM1

  (64) 0x54d0 MOV	%R10D,%R13D

  (64) 0x54d3 VMOVSS	(%RDI,%R13,4),%XMM2

  (64) 0x54d9 VCVTSS2SD	%XMM2,%XMM2,%XMM2

  (64) 0x54dd LEA	0x3(%RAX,%R8,1),%R13D

  (64) 0x54e2 VMOVSS	(%RSI,%R13,4),%XMM3

  (64) 0x54e8 VCVTSS2SD	%XMM3,%XMM3,%XMM3

  (64) 0x54ec VFMADD213SD	%XMM0,%XMM1,%XMM2

  (64) 0x54f1 MOV	%R9D,%R13D

  (64) 0x54f4 VMOVSS	(%RDI,%R13,4),%XMM0

  (64) 0x54fa VCVTSS2SD	%XMM0,%XMM0,%XMM0

  (64) 0x54fe VFMADD213SD	%XMM2,%XMM3,%XMM0

  (64) 0x5503 ADD	$0x4,%R8

  (64) 0x5507 ADD	%RDX,%R9

  (64) 0x550a ADD	%RDX,%R10

  (64) 0x550d ADD	%RDX,%R11

  (64) 0x5510 ADD	%RDX,%RBX

  (64) 0x5513 CMP	%R8,%RCX

  (64) 0x5516 JNE	5480

0x551c JMP	5351

0x5521 CMPL	$0x10,0x28(%RSP)

0x5526 JAE	553a

0x5528 XOR	%R8D,%R8D

0x552b MOV	0x58(%RSP),%RCX

0x5530 MOV	0x30(%RSP),%RDX

0x5535 JMP	55fe

0x553a VPXOR	%XMM0,%XMM0,%XMM0

0x553e XOR	%R8D,%R8D

0x5541 VPXOR	%XMM1,%XMM1,%XMM1

0x5545 VXORPS	%XMM2,%XMM2,%XMM2

0x5549 VXORPS	%XMM3,%XMM3,%XMM3

0x554d MOV	0x58(%RSP),%RCX

0x5552 MOV	0x368(%RSP),%RSI

0x555a MOV	0x30(%RSP),%RDX

  (66) 0x555f LEA	(%RAX,%R8,1),%R9D

  (66) 0x5563 VCVTPS2PD	(%RCX,%R9,4),%YMM4

  (66) 0x5569 VCVTPS2PD	0x10(%RCX,%R9,4),%YMM5

  (66) 0x5570 VCVTPS2PD	0x20(%RCX,%R9,4),%YMM6

  (66) 0x5577 VCVTPS2PD	0x30(%RCX,%R9,4),%YMM7

  (66) 0x557e LEA	(%RDI,%R8,1),%R9D

  (66) 0x5582 VCVTPS2PD	(%RDX,%R9,4),%YMM8

  (66) 0x5588 VFMADD231PD	%YMM8,%YMM4,%YMM0

  (66) 0x558d VCVTPS2PD	0x10(%RDX,%R9,4),%YMM4

  (66) 0x5594 VFMADD231PD	%YMM4,%YMM5,%YMM1

  (66) 0x5599 VCVTPS2PD	0x20(%RDX,%R9,4),%YMM4

  (66) 0x55a0 VFMADD231PD	%YMM4,%YMM6,%YMM2

  (66) 0x55a5 VCVTPS2PD	0x30(%RDX,%R9,4),%YMM4

  (66) 0x55ac VFMADD231PD	%YMM4,%YMM7,%YMM3

  (66) 0x55b1 ADD	$0x10,%R8

  (66) 0x55b5 CMP	%R8,%RSI

  (66) 0x55b8 JNE	555f

0x55ba VADDPD	%YMM0,%YMM1,%YMM0

0x55be VADDPD	%YMM2,%YMM3,%YMM1

0x55c2 VADDPD	%YMM0,%YMM1,%YMM0

0x55c6 VEXTRACTF128	$0x1,%YMM0,%XMM1

0x55cc VADDPD	%XMM1,%XMM0,%XMM0

0x55d0 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x55d5 VADDSD	%XMM1,%XMM0,%XMM0

0x55d9 CMP	%ESI,0x28(%RSP)

0x55dd JE	5351

0x55e3 MOV	%RSI,%R8

0x55e6 MOV	%RSI,%R9

0x55e9 TESTB	$0xc,0x38(%RSP)

0x55ee MOV	0x58(%RSP),%RCX

0x55f3 MOV	0x30(%RSP),%RDX

0x55f8 JE	53be

0x55fe VMOVQ	%XMM0,%XMM0

0x5602 MOV	0x218(%RSP),%RSI

0x560a MOV	0x60(%RSP),%RDI

  (67) 0x560f LEA	(%RAX,%R8,1),%R9D

  (67) 0x5613 VCVTPS2PD	(%RCX,%R9,4),%YMM1

  (67) 0x5619 LEA	(%RDI,%R8,1),%R9D

  (67) 0x561d VCVTPS2PD	(%RDX,%R9,4),%YMM2

  (67) 0x5623 VFMADD231PD	%YMM2,%YMM1,%YMM0

  (67) 0x5628 ADD	$0x4,%R8

  (67) 0x562c CMP	%R8,%RSI

  (67) 0x562f JNE	560f

0x5631 VEXTRACTF128	$0x1,%YMM0,%XMM1

0x5637 VADDPD	%XMM1,%XMM0,%XMM0

0x563b VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

0x5640 VADDSD	%XMM1,%XMM0,%XMM0

0x5644 MOV	%RSI,%R9

0x5647 CMP	%ESI,0x28(%RSP)

0x564b JE	5351

0x5651 JMP	53be

/home/eoseret/llm-attention/attention_v2.cpp: 27 - 33

--------------------------------------------------------------------------------

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	2.51
CQA speedup if FP arith vectorized	2.14
CQA speedup if fully vectorized	8.17
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.44
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.33
CQA cycles if no scalar integer	6.50
CQA cycles if FP arith vectorized	7.65
CQA cycles if fully vectorized	2.00
Front-end cycles	16.33
P0 cycles	9.40
P1 cycles	9.50
P2 cycles	11.33
P3 cycles	11.33
P4 cycles	1.00
P5 cycles	9.30
P6 cycles	9.40
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	9.40
P11 cycles	11.33
DIV/SQRT cycles	3.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	97.00
Nb uops	98.00
Nb loads	34.00
Nb stores	2.00
Nb stack references	16.00
FLOP/cycle	1.16
Nb FLOP add-sub	18.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.63
Bytes prefetched	0.00
Bytes loaded	227.00
Bytes stored	12.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	26.42
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	38.46
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	39.13
Vector-efficiency ratio all	16.10
Vector-efficiency ratio load	9.74
Vector-efficiency ratio store	9.38
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	23.08
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	15.35

Metric	Value
CQA speedup if no scalar integer	2.51
CQA speedup if FP arith vectorized	2.14
CQA speedup if fully vectorized	8.17
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.44
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:27-27,attention_v2.cpp:30-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.33
CQA cycles if no scalar integer	6.50
CQA cycles if FP arith vectorized	7.65
CQA cycles if fully vectorized	2.00
Front-end cycles	16.33
P0 cycles	9.40
P1 cycles	9.50
P2 cycles	11.33
P3 cycles	11.33
P4 cycles	1.00
P5 cycles	9.30
P6 cycles	9.40
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	9.40
P11 cycles	11.33
DIV/SQRT cycles	3.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	97.00
Nb uops	98.00
Nb loads	34.00
Nb stores	2.00
Nb stack references	16.00
FLOP/cycle	1.16
Nb FLOP add-sub	18.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	14.63
Bytes prefetched	0.00
Bytes loaded	227.00
Bytes stored	12.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	26.42
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	38.46
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	39.13
Vector-efficiency ratio all	16.10
Vector-efficiency ratio load	9.74
Vector-efficiency ratio store	9.38
Vector-efficiency ratio mul	12.50
Vector-efficiency ratio add_sub	23.08
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	15.35

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-clang-gnr256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:27-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:27,30,33.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=23
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 23 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.33 to 6.50 cycles (2.51x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions).

Details

26% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
38% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
39% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:30
- /home/eoseret/llm-attention/attention_v2.cpp:30

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 3 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 19 FP arithmetical operations:

18: addition or subtraction
1: divide

The binary loop is loading 227 bytes (28 double precision FP elements). The binary loop is storing 12 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	97
nb uops	98
loop length	451
used x86 registers	12
used mmx registers	0
used xmm registers	4
used ymm registers	4
used zmm registers	0
nb stack references	16

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.33 cycles
front end	16.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	9.40	9.50	11.33	11.33	1.00	9.30	9.40	1.00	1.00	1.00	9.40	11.33
cycles	9.40	9.50	11.33	11.33	1.00	9.30	9.40	1.00	1.00	1.00	9.40	11.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

3.00

Cycles summary

Front-end	16.33
Dispatch	11.33
DIV/SQRT	3.00
Overall L1	16.33

Vectorization ratios

INT

all	8%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	68%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	71%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	85%

INT+FP

all	26%
load	0%
store	0%
mul	0%
add-sub	38%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	39%

Vector efficiency ratios

INT

all	12%
load	9%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	25%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	32%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	23%

INT+FP

all	16%
load	9%
store	9%
mul	12%
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.33 cycles. At this rate:

7% of peak load performance is reached (13.90 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.73 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 16.33 to 11.33 cycles (1.44x speedup).

ASM code

In the binary file, the address of the loop is: 538e

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VDIVSS 0x29c(%RSP),%XMM0,%XMM0	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	11-12	3	scal (6.3%)
MOV 0x20(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x60(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RCX,%RDI,1),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV 0xf8(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RCX,%R8,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x88(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %R13,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 5306 <main+0x25f6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CMPL $0x4,0x28(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
MOV %RDI,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JB 53bb <main+0x26ab>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDI,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD 0x98(%RSP),%R8D	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
SETB %R8B	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
OR 0x160(%RSP),%R8B	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	N/A
JE 5521 <main+0x2811>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
TESTB $0x3,0x38(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	2	0.33	scal (1.6%)
JE 541b <main+0x270b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x50(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R13,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
IMUL %R9,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD 0x60(%RSP),%R10	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV 0x1a0(%RSP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x58(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 5428 <main+0x2718>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x58(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %RCX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMP $-0x4,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x378(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JA 5351 <main+0x2641>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x3(%R8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x50(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
IMUL %R13,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOV 0x60(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RBX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
LEA 0x2(%R8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RBX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R13,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
IMUL %R8,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RBX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
LEA 0x1(%R8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13,%RBX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD 0x60(%RSP),%RBX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 5351 <main+0x2641>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
CMPL $0x10,0x28(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JAE 553a <main+0x282a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x58(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 55fe <main+0x28ee>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPXOR %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV 0x58(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x368(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDPD %YMM0,%YMM1,%YMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM2,%YMM3,%YMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM0,%YMM1,%YMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
CMP %ESI,0x28(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JE 5351 <main+0x2641>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
TESTB $0xc,0x38(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	2	0.33	scal (1.6%)
MOV 0x58(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JE 53be <main+0x26ae>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVQ %XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV 0x218(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x60(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
MOV %RSI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %ESI,0x28(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JE 5351 <main+0x2641>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 53be <main+0x26ae>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	main
Source file and lines	attention_v2.cpp:27-33
Module	attention-clang-gnr256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:27-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:27,30,33.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=23
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.33 to 6.50 cycles (2.51x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions).

Details

26% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
38% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
39% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33

Vector unaligned load/store instructions

Detected 2 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 2 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:30
- /home/eoseret/llm-attention/attention_v2.cpp:30

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 19 FP arithmetical operations:

18: addition or subtraction
1: divide

The binary loop is loading 227 bytes (28 double precision FP elements). The binary loop is storing 12 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	97
nb uops	98
loop length	451
used x86 registers	12
used mmx registers	0
used xmm registers	4
used ymm registers	4
used zmm registers	0
nb stack references	16

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.33 cycles
front end	16.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	9.40	9.50	11.33	11.33	1.00	9.30	9.40	1.00	1.00	1.00	9.40	11.33
cycles	9.40	9.50	11.33	11.33	1.00	9.30	9.40	1.00	1.00	1.00	9.40	11.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

3.00

Cycles summary

Front-end	16.33
Dispatch	11.33
DIV/SQRT	3.00
Overall L1	16.33

Vectorization ratios

INT

all	8%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	68%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	71%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	85%

INT+FP

all	26%
load	0%
store	0%
mul	0%
add-sub	38%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	39%

Vector efficiency ratios

INT

all	12%
load	9%
store	12%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	25%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	32%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	23%

INT+FP

all	16%
load	9%
store	9%
mul	12%
add-sub	23%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.33 cycles. At this rate:

7% of peak load performance is reached (13.90 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.73 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 538e

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VCVTSD2SS %XMM0,%XMM0,%XMM0	2	0.50	0.50	0	0	0	1	0	0	0	0	0	0	5	1	scal (12.5%)
VDIVSS 0x29c(%RSP),%XMM0,%XMM0	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	11-12	3	scal (6.3%)
MOV 0x20(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x60(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RCX,%RDI,1),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV 0xf8(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS %XMM0,(%RCX,%R8,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
INC %RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x88(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMP %R13,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 5306 <main+0x25f6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
CMPL $0x4,0x28(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
MOV %RDI,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JB 53bb <main+0x26ab>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %EDI,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD 0x98(%RSP),%R8D	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
SETB %R8B	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	N/A
OR 0x160(%RSP),%R8B	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	N/A
JE 5521 <main+0x2811>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
TESTB $0x3,0x38(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	2	0.33	scal (1.6%)
JE 541b <main+0x270b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x50(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R13,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
IMUL %R9,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD 0x60(%RSP),%R10	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
MOV 0x1a0(%RSP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x58(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 5428 <main+0x2718>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
MOV %R9,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x58(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %RCX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMP $-0x4,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x378(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JA 5351 <main+0x2641>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x3(%R8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x50(%RSP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
IMUL %R13,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOV 0x60(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %RBX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
LEA 0x2(%R8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RBX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R13,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
IMUL %R8,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %RBX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
LEA 0x1(%R8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R13,%RBX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD 0x60(%RSP),%RBX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 5351 <main+0x2641>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
CMPL $0x10,0x28(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JAE 553a <main+0x282a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x58(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JMP 55fe <main+0x28ee>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %R8D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPXOR %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VXORPS %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOV 0x58(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x368(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VADDPD %YMM0,%YMM1,%YMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM2,%YMM3,%YMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VADDPD %YMM0,%YMM1,%YMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
CMP %ESI,0x28(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JE 5351 <main+0x2641>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
TESTB $0xc,0x38(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	2	0.33	scal (1.6%)
MOV 0x58(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
JE 53be <main+0x26ae>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVQ %XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV 0x218(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x60(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VEXTRACTF128 $0x1,%YMM0,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VADDPD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (25.0%)
VSHUFPD $0x1,%XMM0,%XMM0,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VADDSD %XMM1,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	scal (12.5%)
MOV %RSI,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMP %ESI,0x28(%RSP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
JE 5351 <main+0x2641>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 53be <main+0x26ae>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code