OV - attention-clang-gnr256 - Loop 47 - attention-clang-gnr256

	Loop Id: 47	Module: attention-clang-gnr256	Source: attention_v2.cpp:52-53	Coverage: 0.26%

0x5886 VMOVAPS	%YMM1,0x440(%RSP)    [1]

0x588f VMOVUPS	-0x60(%RDX,%R13,4),%YMM0    [2]

0x5896 VMOVUPS	-0x40(%RDX,%R13,4),%YMM1    [2]

0x589d VMOVUPS	-0x20(%RDX,%R13,4),%YMM2    [2]

0x58a4 VMOVUPS	(%RDX,%R13,4),%YMM3    [2]

0x58aa VMOVAPS	0x420(%RSP),%YMM4    [1]

0x58b3 VSUBPS	%YMM4,%YMM0,%YMM5

0x58b7 VMOVAPS	%YMM5,0x100(%RSP)    [1]

0x58c0 VSUBPS	%YMM4,%YMM1,%YMM0

0x58c4 VMOVAPS	%YMM0,0xa0(%RSP)    [1]

0x58cd VSUBPS	%YMM4,%YMM2,%YMM0

0x58d1 VMOVAPS	%YMM0,0x160(%RSP)    [1]

0x58da VSUBPS	%YMM4,%YMM3,%YMM0

0x58de VMOVAPS	%YMM0,0x60(%RSP)    [1]

0x58e4 VEXTRACTF128	$0x1,%YMM5,%XMM0

0x58ea VMOVAPS	%XMM0,0xe0(%RSP)    [1]

0x58f3 VZEROUPPER

0x58f6 CALL	1160 <expf@plt>

0x58fb VMOVAPS	%XMM0,0x1b0(%RSP)    [1]

0x5904 VMOVSHDUP	0xe0(%RSP),%XMM0    [1]

0x590d CALL	1160 <expf@plt>

0x5912 VMOVAPS	0x1b0(%RSP),%XMM1    [1]

0x591b VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x5921 VMOVAPS	%XMM0,0x1b0(%RSP)    [1]

0x592a VPERMILPD	$0x1,0xe0(%RSP),%XMM0    [1]

0x5935 CALL	1160 <expf@plt>

0x593a VMOVAPS	0x1b0(%RSP),%XMM1    [1]

0x5943 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x5949 VMOVAPS	%XMM0,0x1b0(%RSP)    [1]

0x5952 VPSHUFD	$-0x1,0xe0(%RSP),%XMM0    [1]

0x595c CALL	1160 <expf@plt>

0x5961 VMOVAPS	0x1b0(%RSP),%XMM1    [1]

0x596a VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x5970 VMOVAPS	%XMM0,0xe0(%RSP)    [1]

0x5979 VMOVAPS	0x100(%RSP),%YMM0    [1]

0x5982 VZEROUPPER

0x5985 CALL	1160 <expf@plt>

0x598a VMOVAPS	%XMM0,0x1b0(%RSP)    [1]

0x5993 VMOVSHDUP	0x100(%RSP),%XMM0    [1]

0x599c CALL	1160 <expf@plt>

0x59a1 VMOVAPS	0x1b0(%RSP),%XMM1    [1]

0x59aa VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x59b0 VMOVAPS	%XMM0,0x1b0(%RSP)    [1]

0x59b9 VPERMILPD	$0x1,0x100(%RSP),%XMM0    [1]

0x59c4 CALL	1160 <expf@plt>

0x59c9 VMOVAPS	0x1b0(%RSP),%XMM1    [1]

0x59d2 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x59d8 VMOVAPS	%XMM0,0x1b0(%RSP)    [1]

0x59e1 VPSHUFD	$-0x1,0x100(%RSP),%XMM0    [1]

0x59eb CALL	1160 <expf@plt>

0x59f0 VMOVAPS	0x1b0(%RSP),%XMM1    [1]

0x59f9 VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x59ff VINSERTF128	$0x1,0xe0(%RSP),%YMM0,%YMM0    [1]

0x5a0a VMOVAPS	0x3c0(%RSP),%YMM1    [1]

0x5a13 VADDPS	%YMM1,%YMM0,%YMM1

0x5a17 VMOVAPS	%YMM1,0x3c0(%RSP)    [1]

0x5a20 VMOVAPS	0xa0(%RSP),%YMM0    [1]

0x5a29 VEXTRACTF128	$0x1,%YMM0,%XMM0

0x5a2f VMOVAPS	%XMM0,0x100(%RSP)    [1]

0x5a38 VZEROUPPER

0x5a3b CALL	1160 <expf@plt>

0x5a40 VMOVAPS	%XMM0,0xe0(%RSP)    [1]

0x5a49 VMOVSHDUP	0x100(%RSP),%XMM0    [1]

0x5a52 CALL	1160 <expf@plt>

0x5a57 VMOVAPS	0xe0(%RSP),%XMM1    [1]

0x5a60 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x5a66 VMOVAPS	%XMM0,0xe0(%RSP)    [1]

0x5a6f VPERMILPD	$0x1,0x100(%RSP),%XMM0    [1]

0x5a7a CALL	1160 <expf@plt>

0x5a7f VMOVAPS	0xe0(%RSP),%XMM1    [1]

0x5a88 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x5a8e VMOVAPS	%XMM0,0xe0(%RSP)    [1]

0x5a97 VPSHUFD	$-0x1,0x100(%RSP),%XMM0    [1]

0x5aa1 CALL	1160 <expf@plt>

0x5aa6 VMOVAPS	0xe0(%RSP),%XMM1    [1]

0x5aaf VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x5ab5 VMOVAPS	%XMM0,0x100(%RSP)    [1]

0x5abe VMOVAPS	0xa0(%RSP),%YMM0    [1]

0x5ac7 VZEROUPPER

0x5aca CALL	1160 <expf@plt>

0x5acf VMOVAPS	%XMM0,0xe0(%RSP)    [1]

0x5ad8 VMOVSHDUP	0xa0(%RSP),%XMM0    [1]

0x5ae1 CALL	1160 <expf@plt>

0x5ae6 VMOVAPS	0xe0(%RSP),%XMM1    [1]

0x5aef VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x5af5 VMOVAPS	%XMM0,0xe0(%RSP)    [1]

0x5afe VPERMILPD	$0x1,0xa0(%RSP),%XMM0    [1]

0x5b09 CALL	1160 <expf@plt>

0x5b0e VMOVAPS	0xe0(%RSP),%XMM1    [1]

0x5b17 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x5b1d VMOVAPS	%XMM0,0xe0(%RSP)    [1]

0x5b26 VPSHUFD	$-0x1,0xa0(%RSP),%XMM0    [1]

0x5b30 CALL	1160 <expf@plt>

0x5b35 VMOVAPS	0xe0(%RSP),%XMM1    [1]

0x5b3e VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x5b44 VINSERTF128	$0x1,0x100(%RSP),%YMM0,%YMM0    [1]

0x5b4f VMOVAPS	0x3a0(%RSP),%YMM1    [1]

0x5b58 VADDPS	%YMM1,%YMM0,%YMM1

0x5b5c VMOVAPS	%YMM1,0x3a0(%RSP)    [1]

0x5b65 VMOVAPS	0x160(%RSP),%YMM0    [1]

0x5b6e VEXTRACTF128	$0x1,%YMM0,%XMM0

0x5b74 VMOVAPS	%XMM0,0xa0(%RSP)    [1]

0x5b7d VZEROUPPER

0x5b80 CALL	1160 <expf@plt>

0x5b85 VMOVAPS	%XMM0,0x100(%RSP)    [1]

0x5b8e VMOVSHDUP	0xa0(%RSP),%XMM0    [1]

0x5b97 CALL	1160 <expf@plt>

0x5b9c VMOVAPS	0x100(%RSP),%XMM1    [1]

0x5ba5 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x5bab VMOVAPS	%XMM0,0x100(%RSP)    [1]

0x5bb4 VPERMILPD	$0x1,0xa0(%RSP),%XMM0    [1]

0x5bbf CALL	1160 <expf@plt>

0x5bc4 VMOVAPS	0x100(%RSP),%XMM1    [1]

0x5bcd VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x5bd3 VMOVAPS	%XMM0,0x100(%RSP)    [1]

0x5bdc VPSHUFD	$-0x1,0xa0(%RSP),%XMM0    [1]

0x5be6 CALL	1160 <expf@plt>

0x5beb VMOVAPS	0x100(%RSP),%XMM1    [1]

0x5bf4 VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x5bfa VMOVAPS	%XMM0,0xa0(%RSP)    [1]

0x5c03 VMOVAPS	0x160(%RSP),%YMM0    [1]

0x5c0c VZEROUPPER

0x5c0f CALL	1160 <expf@plt>

0x5c14 VMOVAPS	%XMM0,0x100(%RSP)    [1]

0x5c1d VMOVSHDUP	0x160(%RSP),%XMM0    [1]

0x5c26 CALL	1160 <expf@plt>

0x5c2b VMOVAPS	0x100(%RSP),%XMM1    [1]

0x5c34 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x5c3a VMOVAPS	%XMM0,0x100(%RSP)    [1]

0x5c43 VPERMILPD	$0x1,0x160(%RSP),%XMM0    [1]

0x5c4e CALL	1160 <expf@plt>

0x5c53 VMOVAPS	0x100(%RSP),%XMM1    [1]

0x5c5c VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x5c62 VMOVAPS	%XMM0,0x100(%RSP)    [1]

0x5c6b VPSHUFD	$-0x1,0x160(%RSP),%XMM0    [1]

0x5c75 CALL	1160 <expf@plt>

0x5c7a VMOVAPS	0x100(%RSP),%XMM1    [1]

0x5c83 VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x5c89 VINSERTF128	$0x1,0xa0(%RSP),%YMM0,%YMM0    [1]

0x5c94 VMOVAPS	0x3e0(%RSP),%YMM1    [1]

0x5c9d VADDPS	%YMM1,%YMM0,%YMM1

0x5ca1 VMOVAPS	%YMM1,0x3e0(%RSP)    [1]

0x5caa VMOVAPS	0x60(%RSP),%YMM0    [1]

0x5cb0 VEXTRACTF128	$0x1,%YMM0,%XMM0

0x5cb6 VMOVAPS	%XMM0,0x160(%RSP)    [1]

0x5cbf VZEROUPPER

0x5cc2 CALL	1160 <expf@plt>

0x5cc7 VMOVAPS	%XMM0,0xa0(%RSP)    [1]

0x5cd0 VMOVSHDUP	0x160(%RSP),%XMM0    [1]

0x5cd9 CALL	1160 <expf@plt>

0x5cde VMOVAPS	0xa0(%RSP),%XMM1    [1]

0x5ce7 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x5ced VMOVAPS	%XMM0,0xa0(%RSP)    [1]

0x5cf6 VPERMILPD	$0x1,0x160(%RSP),%XMM0    [1]

0x5d01 CALL	1160 <expf@plt>

0x5d06 VMOVAPS	0xa0(%RSP),%XMM1    [1]

0x5d0f VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x5d15 VMOVAPS	%XMM0,0xa0(%RSP)    [1]

0x5d1e VPSHUFD	$-0x1,0x160(%RSP),%XMM0    [1]

0x5d28 CALL	1160 <expf@plt>

0x5d2d VMOVAPS	0xa0(%RSP),%XMM1    [1]

0x5d36 VINSERTPS	$0x30,%XMM0,%XMM1,%XMM0

0x5d3c VMOVAPS	%XMM0,0x160(%RSP)    [1]

0x5d45 VMOVAPS	0x60(%RSP),%YMM0    [1]

0x5d4b VZEROUPPER

0x5d4e CALL	1160 <expf@plt>

0x5d53 VMOVAPS	%XMM0,0xa0(%RSP)    [1]

0x5d5c VMOVSHDUP	0x60(%RSP),%XMM0    [1]

0x5d62 CALL	1160 <expf@plt>

0x5d67 VMOVAPS	0xa0(%RSP),%XMM1    [1]

0x5d70 VINSERTPS	$0x10,%XMM0,%XMM1,%XMM0

0x5d76 VMOVAPS	%XMM0,0xa0(%RSP)    [1]

0x5d7f VPERMILPD	$0x1,0x60(%RSP),%XMM0    [1]

0x5d87 CALL	1160 <expf@plt>

0x5d8c VMOVAPS	0xa0(%RSP),%XMM1    [1]

0x5d95 VINSERTPS	$0x20,%XMM0,%XMM1,%XMM0

0x5d9b VMOVAPS	%XMM0,0xa0(%RSP)    [1]

0x5da4 VPSHUFD	$-0x1,0x60(%RSP),%XMM0    [1]

0x5dab CALL	1160 <expf@plt>

0x5db0 VMOVAPS	0x440(%RSP),%YMM1    [1]

0x5db9 MOV	0x2c0(%RSP),%RDX    [1]

0x5dc1 VMOVAPS	0xa0(%RSP),%XMM2    [1]

0x5dca VINSERTPS	$0x30,%XMM0,%XMM2,%XMM0

0x5dd0 VINSERTF128	$0x1,0x160(%RSP),%YMM0,%YMM0    [1]

0x5ddb VADDPS	%YMM1,%YMM0,%YMM1

0x5ddf ADD	$0x20,%R13

0x5de3 CMP	%R13,%RBX

0x5de6 JNE	5886

/home/eoseret/llm-attention/attention_v2.cpp: 52 - 53

--------------------------------------------------------------------------------

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.14
CQA speedup if FP arith vectorized	1.13
CQA speedup if fully vectorized	4.40
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:52-53
Source loop unroll info	unrolled by 32
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	32
CQA cycles	41.17
CQA cycles if no scalar integer	36.00
CQA cycles if FP arith vectorized	36.35
CQA cycles if fully vectorized	9.36
Front-end cycles	41.17
P0 cycles	4.50
P1 cycles	16.00
P2 cycles	23.00
P3 cycles	23.00
P4 cycles	36.00
P5 cycles	36.00
P6 cycles	0.50
P7 cycles	36.00
P8 cycles	36.00
P9 cycles	36.00
P10 cycles	0.00
P11 cycles	23.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	188.00
Nb uops	247.00
Nb loads	69.00
Nb stores	40.00
Nb stack references	12.00
FLOP/cycle	1.55
Nb FLOP add-sub	64.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	51.50
Bytes prefetched	0.00
Bytes loaded	1352.00
Bytes stored	768.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	84.21
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	57.14
Vector-efficiency ratio all	26.64
Vector-efficiency ratio load	29.41
Vector-efficiency ratio store	30.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.96

Metric	Value
CQA speedup if no scalar integer	1.14
CQA speedup if FP arith vectorized	1.13
CQA speedup if fully vectorized	4.40
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:52-53
Source loop unroll info	unrolled by 32
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	32
CQA cycles	41.17
CQA cycles if no scalar integer	36.00
CQA cycles if FP arith vectorized	36.35
CQA cycles if fully vectorized	9.36
Front-end cycles	41.17
P0 cycles	4.50
P1 cycles	16.00
P2 cycles	23.00
P3 cycles	23.00
P4 cycles	36.00
P5 cycles	36.00
P6 cycles	0.50
P7 cycles	36.00
P8 cycles	36.00
P9 cycles	36.00
P10 cycles	0.00
P11 cycles	23.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	188.00
Nb uops	247.00
Nb loads	69.00
Nb stores	40.00
Nb stack references	12.00
FLOP/cycle	1.55
Nb FLOP add-sub	64.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	51.50
Bytes prefetched	0.00
Bytes loaded	1352.00
Bytes stored	768.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	84.21
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	57.14
Vector-efficiency ratio all	26.64
Vector-efficiency ratio load	29.41
Vector-efficiency ratio store	30.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.96

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:52-53
Module	attention-clang-gnr256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:52-53.

It is main loop of related source loop which is unrolled by 32 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 41.17 to 36.00 cycles (1.14x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 26% of vector register length is used (average across all SSE/AVX instructions).

Details

84% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

57% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

expf@plt: 32 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VINSERTF128: 4 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
VPERMILPD: 8 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
VPSHUFD: 8 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
VZEROUPPER: 8 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53

Vector unaligned load/store instructions

Detected 8 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 4 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
VINSERTF128: 4 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

8 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

64: addition or subtraction

The binary loop is loading 1352 bytes (338 single precision FP elements). The binary loop is storing 768 bytes (192 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	188
nb uops	247
loop length	1382
used x86 registers	4
used mmx registers	0
used xmm registers	3
used ymm registers	6
used zmm registers	0
nb stack references	12

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	41.17 cycles
front end	41.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.50	16.00	23.00	23.00	36.00	36.00	0.50	36.00	36.00	36.00	0.00	23.00
cycles	4.50	16.00	23.00	23.00	36.00	36.00	0.50	36.00	36.00	36.00	0.00	23.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	41.17
Dispatch	36.00
Data deps.	1.00
Overall L1	41.17

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	82%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

INT+FP

all	84%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	57%

Vector efficiency ratios

INT

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	26%
load	30%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

INT+FP

all	26%
load	29%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 41.17 cycles. At this rate:

17% of peak load performance is reached (32.84 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (18.66 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 41.17 to 36.00 cycles (1.14x speedup).

ASM code

In the binary file, the address of the loop is: 5886

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVAPS %YMM1,0x440(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS -0x60(%RDX,%R13,4),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS -0x40(%RDX,%R13,4),%YMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS -0x20(%RDX,%R13,4),%YMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS (%RDX,%R13,4),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPS 0x420(%RSP),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPS %YMM4,%YMM0,%YMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPS %YMM5,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VSUBPS %YMM4,%YMM1,%YMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPS %YMM0,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VSUBPS %YMM4,%YMM2,%YMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPS %YMM0,0x160(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VSUBPS %YMM4,%YMM3,%YMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPS %YMM0,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM5,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x1b0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0xe0(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1b0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x1b0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0xe0(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1b0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x1b0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0xe0(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1b0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPS 0x100(%RSP),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x1b0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x100(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1b0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x1b0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x100(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1b0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x1b0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x100(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1b0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0xe0(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	3	0.33	vect (25.0%)
VMOVAPS 0x3c0(%RSP),%YMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPS %YMM1,%YMM0,%YMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPS %YMM1,0x3c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPS 0xa0(%RSP),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x100(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xe0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x100(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xe0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x100(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xe0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPS 0xa0(%RSP),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0xa0(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xe0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0xa0(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xe0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0xa0(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xe0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0x100(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	3	0.33	vect (25.0%)
VMOVAPS 0x3a0(%RSP),%YMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPS %YMM1,%YMM0,%YMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPS %YMM1,0x3a0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPS 0x160(%RSP),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0xa0(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x100(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0xa0(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x100(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0xa0(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x100(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPS 0x160(%RSP),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x160(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x100(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x160(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x100(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x160(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x100(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0xa0(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	3	0.33	vect (25.0%)
VMOVAPS 0x3e0(%RSP),%YMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPS %YMM1,%YMM0,%YMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPS %YMM1,0x3e0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPS 0x60(%RSP),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x160(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x160(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xa0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x160(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xa0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x160(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xa0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x160(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPS 0x60(%RSP),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x60(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xa0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x60(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xa0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x60(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x440(%RSP),%YMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
MOV 0x2c0(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVAPS 0xa0(%RSP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM2,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0x160(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	3	0.33	vect (25.0%)
VADDPS %YMM1,%YMM0,%YMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x20,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R13,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 5886 <main+0x2b76>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:52-53
Module	attention-clang-gnr256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:52-53.

It is main loop of related source loop which is unrolled by 32 (including vectorization).

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 26% of vector register length is used (average across all SSE/AVX instructions).

Details

84% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

57% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

expf@plt: 32 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VINSERTF128: 4 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
VPERMILPD: 8 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
VPSHUFD: 8 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
VZEROUPPER: 8 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53

Vector unaligned load/store instructions

Detected 8 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 4 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
VINSERTF128: 4 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53
- /home/eoseret/llm-attention/attention_v2.cpp:53

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

8 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

64: addition or subtraction

The binary loop is loading 1352 bytes (338 single precision FP elements). The binary loop is storing 768 bytes (192 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	188
nb uops	247
loop length	1382
used x86 registers	4
used mmx registers	0
used xmm registers	3
used ymm registers	6
used zmm registers	0
nb stack references	12

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	41.17 cycles
front end	41.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.50	16.00	23.00	23.00	36.00	36.00	0.50	36.00	36.00	36.00	0.00	23.00
cycles	4.50	16.00	23.00	23.00	36.00	36.00	0.50	36.00	36.00	36.00	0.00	23.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	41.17
Dispatch	36.00
Data deps.	1.00
Overall L1	41.17

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	82%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

INT+FP

all	84%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	57%

Vector efficiency ratios

INT

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	26%
load	30%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

INT+FP

all	26%
load	29%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 41.17 cycles. At this rate:

17% of peak load performance is reached (32.84 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (18.66 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 5886

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVAPS %YMM1,0x440(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS -0x60(%RDX,%R13,4),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS -0x40(%RDX,%R13,4),%YMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS -0x20(%RDX,%R13,4),%YMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS (%RDX,%R13,4),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVAPS 0x420(%RSP),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VSUBPS %YMM4,%YMM0,%YMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPS %YMM5,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VSUBPS %YMM4,%YMM1,%YMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPS %YMM0,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VSUBPS %YMM4,%YMM2,%YMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPS %YMM0,0x160(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VSUBPS %YMM4,%YMM3,%YMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPS %YMM0,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VEXTRACTF128 $0x1,%YMM5,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x1b0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0xe0(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1b0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x1b0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0xe0(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1b0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x1b0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0xe0(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1b0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPS 0x100(%RSP),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x1b0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x100(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1b0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x1b0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x100(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1b0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x1b0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x100(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x1b0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0xe0(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	3	0.33	vect (25.0%)
VMOVAPS 0x3c0(%RSP),%YMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPS %YMM1,%YMM0,%YMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPS %YMM1,0x3c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPS 0xa0(%RSP),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x100(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xe0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x100(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xe0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x100(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xe0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPS 0xa0(%RSP),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0xa0(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xe0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0xa0(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xe0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0xa0(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xe0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0x100(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	3	0.33	vect (25.0%)
VMOVAPS 0x3a0(%RSP),%YMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPS %YMM1,%YMM0,%YMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPS %YMM1,0x3a0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPS 0x160(%RSP),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0xa0(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x100(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0xa0(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x100(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0xa0(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x100(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPS 0x160(%RSP),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x160(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x100(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x160(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x100(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x160(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x100(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0xa0(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	3	0.33	vect (25.0%)
VMOVAPS 0x3e0(%RSP),%YMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VADDPS %YMM1,%YMM0,%YMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVAPS %YMM1,0x3e0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVAPS 0x60(%RSP),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VEXTRACTF128 $0x1,%YMM0,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMOVAPS %XMM0,0x160(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x160(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xa0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x160(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xa0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x160(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xa0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0x160(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVAPS 0x60(%RSP),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS %XMM0,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VMOVSHDUP 0x60(%RSP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	vect (12.5%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xa0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x10,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPERMILPD $0x1,0x60(%RSP),%XMM0	2	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	1	1	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0xa0(%RSP),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x20,%XMM0,%XMM1,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VMOVAPS %XMM0,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
VPSHUFD $-0x1,0x60(%RSP),%XMM0	2	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	1	0.50	vect (25.0%)
CALL 1160 <expf@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVAPS 0x440(%RSP),%YMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
MOV 0x2c0(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVAPS 0xa0(%RSP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (25.0%)
VINSERTPS $0x30,%XMM0,%XMM2,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	scal (6.3%)
VINSERTF128 $0x1,0x160(%RSP),%YMM0,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	3	0.33	vect (25.0%)
VADDPS %YMM1,%YMM0,%YMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
ADD $0x20,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R13,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 5886 <main+0x2b76>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code