OV - attention-gnr-256 - Function __ocl_svml_l9__svml_sexp_cout_rare_internal

	Function: __ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper	Module: attention-gnr-256	Source: :0-0	Coverage (incl. loops): 0.05% \| (excl. loops): 0.05%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x407a10 SUB	$0x138,%RSP

0x407a17 VMOVUPS	%YMM15,0x100(%RSP)

0x407a20 VMOVUPS	%YMM14,0xe0(%RSP)

0x407a29 VMOVUPS	%YMM13,0xc0(%RSP)

0x407a32 VMOVUPS	%YMM12,0xa0(%RSP)

0x407a3b VMOVUPS	%YMM11,0x80(%RSP)

0x407a44 VMOVUPS	%YMM10,0x60(%RSP)

0x407a4a VMOVUPS	%YMM9,0x40(%RSP)

0x407a50 VMOVUPS	%YMM8,0x20(%RSP)

0x407a56 TEST	$0x1,%DL

0x407a59 JNE	407ae8

0x407a5f TEST	$0x2,%DL

0x407a62 JNE	407b1f

0x407a68 TEST	$0x4,%DL

0x407a6b JNE	407b5a

0x407a71 TEST	$0x8,%DL

0x407a74 JNE	407b95

0x407a7a TEST	$0x10,%DL

0x407a7d JNE	407bd0

0x407a83 TEST	$0x20,%DL

0x407a86 JNE	407c0b

0x407a8c TEST	$0x40,%DL

0x407a8f JNE	407c46

0x407a95 CMP	$0x80,%EDX

0x407a9b JAE	407c84

0x407aa1 VMOVUPS	0x20(%RSP),%YMM8

0x407aa7 VMOVUPS	0x40(%RSP),%YMM9

0x407aad VMOVUPS	0x60(%RSP),%YMM10

0x407ab3 VMOVUPS	0x80(%RSP),%YMM11

0x407abc VMOVUPS	0xa0(%RSP),%YMM12

0x407ac5 VMOVUPS	0xc0(%RSP),%YMM13

0x407ace VMOVUPS	0xe0(%RSP),%YMM14

0x407ad7 VMOVUPS	0x100(%RSP),%YMM15

0x407ae0 ADD	$0x138,%RSP

0x407ae7 RET

0x407ae8 MOV	%RDI,0x18(%RSP)

0x407aed MOV	0x18(%RSP),%RDI

0x407af2 MOV	%RSI,0x10(%RSP)

0x407af7 MOV	0x10(%RSP),%RSI

0x407afc MOV	%EDX,0xc(%RSP)

0x407b00 VZEROUPPER

0x407b03 CALL	407f30 <__svml_sexp_cout_rare_internal>

0x407b08 MOV	0xc(%RSP),%EDX

0x407b0c MOV	0x18(%RSP),%RDI

0x407b11 MOV	0x10(%RSP),%RSI

0x407b16 TEST	$0x2,%DL

0x407b19 JE	407a68

0x407b1f LEA	0x4(%RDI),%RAX

0x407b23 LEA	0x4(%RSI),%RCX

0x407b27 MOV	%RDI,0x18(%RSP)

0x407b2c MOV	%RAX,%RDI

0x407b2f MOV	%RSI,0x10(%RSP)

0x407b34 MOV	%RCX,%RSI

0x407b37 MOV	%EDX,0xc(%RSP)

0x407b3b VZEROUPPER

0x407b3e CALL	407f30 <__svml_sexp_cout_rare_internal>

0x407b43 MOV	0xc(%RSP),%EDX

0x407b47 MOV	0x18(%RSP),%RDI

0x407b4c MOV	0x10(%RSP),%RSI

0x407b51 TEST	$0x4,%DL

0x407b54 JE	407a71

0x407b5a LEA	0x8(%RDI),%RAX

0x407b5e LEA	0x8(%RSI),%RCX

0x407b62 MOV	%RDI,0x18(%RSP)

0x407b67 MOV	%RAX,%RDI

0x407b6a MOV	%RSI,0x10(%RSP)

0x407b6f MOV	%RCX,%RSI

0x407b72 MOV	%EDX,0xc(%RSP)

0x407b76 VZEROUPPER

0x407b79 CALL	407f30 <__svml_sexp_cout_rare_internal>

0x407b7e MOV	0xc(%RSP),%EDX

0x407b82 MOV	0x18(%RSP),%RDI

0x407b87 MOV	0x10(%RSP),%RSI

0x407b8c TEST	$0x8,%DL

0x407b8f JE	407a7a

0x407b95 LEA	0xc(%RDI),%RAX

0x407b99 LEA	0xc(%RSI),%RCX

0x407b9d MOV	%RDI,0x18(%RSP)

0x407ba2 MOV	%RAX,%RDI

0x407ba5 MOV	%RSI,0x10(%RSP)

0x407baa MOV	%RCX,%RSI

0x407bad MOV	%EDX,0xc(%RSP)

0x407bb1 VZEROUPPER

0x407bb4 CALL	407f30 <__svml_sexp_cout_rare_internal>

0x407bb9 MOV	0xc(%RSP),%EDX

0x407bbd MOV	0x18(%RSP),%RDI

0x407bc2 MOV	0x10(%RSP),%RSI

0x407bc7 TEST	$0x10,%DL

0x407bca JE	407a83

0x407bd0 LEA	0x10(%RDI),%RAX

0x407bd4 LEA	0x10(%RSI),%RCX

0x407bd8 MOV	%RDI,0x18(%RSP)

0x407bdd MOV	%RAX,%RDI

0x407be0 MOV	%RSI,0x10(%RSP)

0x407be5 MOV	%RCX,%RSI

0x407be8 MOV	%EDX,0xc(%RSP)

0x407bec VZEROUPPER

0x407bef CALL	407f30 <__svml_sexp_cout_rare_internal>

0x407bf4 MOV	0xc(%RSP),%EDX

0x407bf8 MOV	0x18(%RSP),%RDI

0x407bfd MOV	0x10(%RSP),%RSI

0x407c02 TEST	$0x20,%DL

0x407c05 JE	407a8c

0x407c0b LEA	0x14(%RDI),%RAX

0x407c0f LEA	0x14(%RSI),%RCX

0x407c13 MOV	%RDI,0x18(%RSP)

0x407c18 MOV	%RAX,%RDI

0x407c1b MOV	%RSI,0x10(%RSP)

0x407c20 MOV	%RCX,%RSI

0x407c23 MOV	%EDX,0xc(%RSP)

0x407c27 VZEROUPPER

0x407c2a CALL	407f30 <__svml_sexp_cout_rare_internal>

0x407c2f MOV	0xc(%RSP),%EDX

0x407c33 MOV	0x18(%RSP),%RDI

0x407c38 MOV	0x10(%RSP),%RSI

0x407c3d TEST	$0x40,%DL

0x407c40 JE	407a95

0x407c46 LEA	0x18(%RDI),%RAX

0x407c4a LEA	0x18(%RSI),%RCX

0x407c4e MOV	%RDI,0x18(%RSP)

0x407c53 MOV	%RAX,%RDI

0x407c56 MOV	%RSI,0x10(%RSP)

0x407c5b MOV	%RCX,%RSI

0x407c5e MOV	%EDX,0xc(%RSP)

0x407c62 VZEROUPPER

0x407c65 CALL	407f30 <__svml_sexp_cout_rare_internal>

0x407c6a MOV	0xc(%RSP),%EDX

0x407c6e MOV	0x18(%RSP),%RDI

0x407c73 MOV	0x10(%RSP),%RSI

0x407c78 CMP	$0x80,%EDX

0x407c7e JB	407aa1

0x407c84 ADD	$0x1c,%RDI

0x407c88 ADD	$0x1c,%RSI

0x407c8c VZEROUPPER

0x407c8f CALL	407f30 <__svml_sexp_cout_rare_internal>

0x407c94 JMP	407aa1

0x407c99 NOPL	(%RAX)

0x408650 SUB	$0x138,%RSP

0x408657 VMOVUPS	%YMM15,0x100(%RSP)

0x408660 VMOVUPS	%YMM14,0xe0(%RSP)

0x408669 VMOVUPS	%YMM13,0xc0(%RSP)

0x408672 VMOVUPS	%YMM12,0xa0(%RSP)

0x40867b VMOVUPS	%YMM11,0x80(%RSP)

0x408684 VMOVUPS	%YMM10,0x60(%RSP)

0x40868a VMOVUPS	%YMM9,0x40(%RSP)

0x408690 VMOVUPS	%YMM8,0x20(%RSP)

0x408696 TEST	%EDX,%EDX

0x408698 JNE	4086e1

0x40869a VMOVUPS	0x20(%RSP),%YMM8

0x4086a0 VMOVUPS	0x40(%RSP),%YMM9

0x4086a6 VMOVUPS	0x60(%RSP),%YMM10

0x4086ac VMOVUPS	0x80(%RSP),%YMM11

0x4086b5 VMOVUPS	0xa0(%RSP),%YMM12

0x4086be VMOVUPS	0xc0(%RSP),%YMM13

0x4086c7 VMOVUPS	0xe0(%RSP),%YMM14

0x4086d0 VMOVUPS	0x100(%RSP),%YMM15

0x4086d9 ADD	$0x138,%RSP

0x4086e0 RET

0x4086e1 TEST	$0x1,%DL

0x4086e4 JNE	408735

0x4086e6 TEST	$0x2,%DL

0x4086e9 JNE	408768

0x4086eb TEST	$0x4,%DL

0x4086ee JNE	4087a3

0x4086f4 TEST	$0x8,%DL

0x4086f7 JNE	4087de

0x4086fd TEST	$0x10,%DL

0x408700 JNE	408819

0x408706 TEST	$0x20,%DL

0x408709 JNE	408854

0x40870f TEST	$0x40,%DL

0x408712 JNE	40888f

0x408718 TEST	%DL,%DL

0x40871a JNS	40869a

0x408720 ADD	$0x1c,%RDI

0x408724 ADD	$0x1c,%RSI

0x408728 VZEROUPPER

0x40872b CALL	407f30 <__svml_sexp_cout_rare_internal>

0x408730 JMP	40869a

0x408735 MOV	%RDI,0x18(%RSP)

0x40873a MOV	0x18(%RSP),%RDI

0x40873f MOV	%RSI,0x10(%RSP)

0x408744 MOV	0x10(%RSP),%RSI

0x408749 MOV	%EDX,0xc(%RSP)

0x40874d VZEROUPPER

0x408750 CALL	407f30 <__svml_sexp_cout_rare_internal>

0x408755 MOV	0xc(%RSP),%EDX

0x408759 MOV	0x18(%RSP),%RDI

0x40875e MOV	0x10(%RSP),%RSI

0x408763 TEST	$0x2,%DL

0x408766 JE	4086eb

0x408768 LEA	0x4(%RDI),%RAX

0x40876c LEA	0x4(%RSI),%RCX

0x408770 MOV	%RDI,0x18(%RSP)

0x408775 MOV	%RAX,%RDI

0x408778 MOV	%RSI,0x10(%RSP)

0x40877d MOV	%RCX,%RSI

0x408780 MOV	%EDX,0xc(%RSP)

0x408784 VZEROUPPER

0x408787 CALL	407f30 <__svml_sexp_cout_rare_internal>

0x40878c MOV	0xc(%RSP),%EDX

0x408790 MOV	0x18(%RSP),%RDI

0x408795 MOV	0x10(%RSP),%RSI

0x40879a TEST	$0x4,%DL

0x40879d JE	4086f4

0x4087a3 LEA	0x8(%RDI),%RAX

0x4087a7 LEA	0x8(%RSI),%RCX

0x4087ab MOV	%RDI,0x18(%RSP)

0x4087b0 MOV	%RAX,%RDI

0x4087b3 MOV	%RSI,0x10(%RSP)

0x4087b8 MOV	%RCX,%RSI

0x4087bb MOV	%EDX,0xc(%RSP)

0x4087bf VZEROUPPER

0x4087c2 CALL	407f30 <__svml_sexp_cout_rare_internal>

0x4087c7 MOV	0xc(%RSP),%EDX

0x4087cb MOV	0x18(%RSP),%RDI

0x4087d0 MOV	0x10(%RSP),%RSI

0x4087d5 TEST	$0x8,%DL

0x4087d8 JE	4086fd

0x4087de LEA	0xc(%RDI),%RAX

0x4087e2 LEA	0xc(%RSI),%RCX

0x4087e6 MOV	%RDI,0x18(%RSP)

0x4087eb MOV	%RAX,%RDI

0x4087ee MOV	%RSI,0x10(%RSP)

0x4087f3 MOV	%RCX,%RSI

0x4087f6 MOV	%EDX,0xc(%RSP)

0x4087fa VZEROUPPER

0x4087fd CALL	407f30 <__svml_sexp_cout_rare_internal>

0x408802 MOV	0xc(%RSP),%EDX

0x408806 MOV	0x18(%RSP),%RDI

0x40880b MOV	0x10(%RSP),%RSI

0x408810 TEST	$0x10,%DL

0x408813 JE	408706

0x408819 LEA	0x10(%RDI),%RAX

0x40881d LEA	0x10(%RSI),%RCX

0x408821 MOV	%RDI,0x18(%RSP)

0x408826 MOV	%RAX,%RDI

0x408829 MOV	%RSI,0x10(%RSP)

0x40882e MOV	%RCX,%RSI

0x408831 MOV	%EDX,0xc(%RSP)

0x408835 VZEROUPPER

0x408838 CALL	407f30 <__svml_sexp_cout_rare_internal>

0x40883d MOV	0xc(%RSP),%EDX

0x408841 MOV	0x18(%RSP),%RDI

0x408846 MOV	0x10(%RSP),%RSI

0x40884b TEST	$0x20,%DL

0x40884e JE	40870f

0x408854 LEA	0x14(%RDI),%RAX

0x408858 LEA	0x14(%RSI),%RCX

0x40885c MOV	%RDI,0x18(%RSP)

0x408861 MOV	%RAX,%RDI

0x408864 MOV	%RSI,0x10(%RSP)

0x408869 MOV	%RCX,%RSI

0x40886c MOV	%EDX,0xc(%RSP)

0x408870 VZEROUPPER

0x408873 CALL	407f30 <__svml_sexp_cout_rare_internal>

0x408878 MOV	0xc(%RSP),%EDX

0x40887c MOV	0x18(%RSP),%RDI

0x408881 MOV	0x10(%RSP),%RSI

0x408886 TEST	$0x40,%DL

0x408889 JE	408718

0x40888f LEA	0x18(%RDI),%RAX

0x408893 LEA	0x18(%RSI),%RCX

0x408897 MOV	%RDI,0x18(%RSP)

0x40889c MOV	%RAX,%RDI

0x40889f MOV	%RSI,0x10(%RSP)

0x4088a4 MOV	%RCX,%RSI

0x4088a7 MOV	%EDX,0xc(%RSP)

0x4088ab VZEROUPPER

0x4088ae CALL	407f30 <__svml_sexp_cout_rare_internal>

0x4088b3 MOV	0xc(%RSP),%EDX

0x4088b7 MOV	0x18(%RSP),%RDI

0x4088bc MOV	0x10(%RSP),%RSI

0x4088c1 TEST	%DL,%DL

0x4088c3 JNS	40869a

0x4088c9 JMP	408720

0x4088ce XCHG	%AX,%AX

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.05% of application time for run run_0

Source file and lines
Module	attention-gnr-256

Warnings:

Ignoring paths for analysis
Failed to get the number of paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 51.50 to 15.83 cycles (3.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is partially vectorized. Only 26% of vector register length is used (average across all SSE/AVX instructions).

Details

51% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

27% of SSE/AVX stores are used in vector version.
84% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__svml_sexp_cout_rare_internal: 16 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 16 occurrences►

Vector unaligned load/store instructions

Detected 32 optimal vector unaligned load/store instructions.

Details

VMOVUPS: 32 occurrences►

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries
inform your compiler that your arrays are vector aligned: read your compiler manual.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 824 bytes. The binary function is storing 792 bytes.

General properties

nb instructions	277
nb uops	309
loop length	1296
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	8
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	51.50 cycles
front end	51.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	16.50	11.80	21.33	21.33	37.00	11.60	16.50	37.00	37.00	37.00	11.60	21.33
cycles	16.50	11.80	21.33	21.33	37.00	11.60	16.50	37.00	37.00	37.00	11.60	21.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	51.50
Dispatch	37.00
Overall L1	51.50

Vectorization ratios

INT

all	26%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	84%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	51%
load	100%
store	27%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	84%

Vector efficiency ratios

INT

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	22%

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	26%
load	50%
store	21%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 51.50 cycles. At this rate:

8% of peak load performance is reached (16.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (15.38 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 51.50 to 37.00 cycles (1.39x speedup).

ASM code

In the binary file, the address of the function is: 407a10

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
SUB $0x138,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPS %YMM15,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM14,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM13,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM12,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM11,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM10,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM9,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM8,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
TEST $0x1,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 407ae8 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xd8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST $0x2,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 407b1f <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x10f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST $0x4,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 407b5a <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x14a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST $0x8,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 407b95 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x185>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST $0x10,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 407bd0 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x1c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST $0x20,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 407c0b <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x1fb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST $0x40,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 407c46 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x236>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x80,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 407c84 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x274>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPS 0x20(%RSP),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0x40(%RSP),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0x60(%RSP),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0x80(%RSP),%YMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0xa0(%RSP),%YMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0xc0(%RSP),%YMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0xe0(%RSP),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0x100(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
ADD $0x138,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST $0x2,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 407a68 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x58>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x4(%RDI),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x4(%RSI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST $0x4,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 407a71 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x61>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x8(%RDI),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x8(%RSI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST $0x8,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 407a7a <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x6a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0xc(%RDI),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xc(%RSI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST $0x10,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 407a83 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x73>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x10(%RDI),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x10(%RSI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST $0x20,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 407a8c <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x7c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x14(%RDI),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x14(%RSI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST $0x40,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 407a95 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x85>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x18(%RDI),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x18(%RSI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP $0x80,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 407aa1 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x91>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD $0x1c,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x1c,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 407aa1 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x91>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x138,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPS %YMM15,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM14,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM13,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM12,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM11,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM10,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM9,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM8,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
TEST %EDX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JNE 4086e1 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x91>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPS 0x20(%RSP),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0x40(%RSP),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0x60(%RSP),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0x80(%RSP),%YMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0xa0(%RSP),%YMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0xc0(%RSP),%YMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0xe0(%RSP),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0x100(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
ADD $0x138,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
TEST $0x1,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 408735 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xe5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST $0x2,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 408768 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x118>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST $0x4,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 4087a3 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x153>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST $0x8,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 4087de <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x18e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST $0x10,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 408819 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x1c9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST $0x20,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 408854 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x204>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST $0x40,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 40888f <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x23f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %DL,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNS 40869a <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x4a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD $0x1c,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x1c,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 40869a <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x4a>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST $0x2,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 4086eb <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x9b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x4(%RDI),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x4(%RSI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST $0x4,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 4086f4 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xa4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x8(%RDI),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x8(%RSI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST $0x8,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 4086fd <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xad>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0xc(%RDI),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xc(%RSI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST $0x10,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 408706 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xb6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x10(%RDI),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x10(%RSI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST $0x20,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 40870f <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xbf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x14(%RDI),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x14(%RSI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST $0x40,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 408718 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xc8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x18(%RDI),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x18(%RSI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %DL,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNS 40869a <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x4a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 408720 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xd0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.05% of application time for run run_0

Source file and lines
Module	attention-gnr-256

Warnings:

Ignoring paths for analysis
Failed to get the number of paths

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is partially vectorized. Only 26% of vector register length is used (average across all SSE/AVX instructions).

Details

51% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

27% of SSE/AVX stores are used in vector version.
84% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

CALL instructions

Detected function call instructions.

Details

__svml_sexp_cout_rare_internal: 16 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 16 occurrences►

Vector unaligned load/store instructions

Detected 32 optimal vector unaligned load/store instructions.

Details

VMOVUPS: 32 occurrences►

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries
inform your compiler that your arrays are vector aligned: read your compiler manual.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 824 bytes. The binary function is storing 792 bytes.

General properties

nb instructions	277
nb uops	309
loop length	1296
used x86 registers	6
used mmx registers	0
used xmm registers	0
used ymm registers	8
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	51.50 cycles
front end	51.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	16.50	11.80	21.33	21.33	37.00	11.60	16.50	37.00	37.00	37.00	11.60	21.33
cycles	16.50	11.80	21.33	21.33	37.00	11.60	16.50	37.00	37.00	37.00	11.60	21.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	51.50
Dispatch	37.00
Overall L1	51.50

Vectorization ratios

INT

all	26%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	84%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	51%
load	100%
store	27%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	84%

Vector efficiency ratios

INT

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	22%

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	26%
load	50%
store	21%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 51.50 cycles. At this rate:

8% of peak load performance is reached (16.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (15.38 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 407a10

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
SUB $0x138,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPS %YMM15,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM14,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM13,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM12,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM11,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM10,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM9,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM8,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
TEST $0x1,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 407ae8 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xd8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST $0x2,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 407b1f <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x10f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST $0x4,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 407b5a <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x14a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST $0x8,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 407b95 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x185>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST $0x10,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 407bd0 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x1c0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST $0x20,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 407c0b <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x1fb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST $0x40,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 407c46 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x236>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x80,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JAE 407c84 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x274>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPS 0x20(%RSP),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0x40(%RSP),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0x60(%RSP),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0x80(%RSP),%YMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0xa0(%RSP),%YMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0xc0(%RSP),%YMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0xe0(%RSP),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0x100(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
ADD $0x138,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST $0x2,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 407a68 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x58>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x4(%RDI),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x4(%RSI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST $0x4,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 407a71 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x61>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x8(%RDI),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x8(%RSI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST $0x8,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 407a7a <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x6a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0xc(%RDI),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xc(%RSI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST $0x10,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 407a83 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x73>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x10(%RDI),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x10(%RSI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST $0x20,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 407a8c <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x7c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x14(%RDI),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x14(%RSI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST $0x40,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 407a95 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x85>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x18(%RDI),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x18(%RSI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CMP $0x80,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JB 407aa1 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x91>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD $0x1c,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x1c,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 407aa1 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x91>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x138,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPS %YMM15,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM14,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM13,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM12,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM11,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM10,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM9,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM8,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
TEST %EDX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JNE 4086e1 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x91>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVUPS 0x20(%RSP),%YMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0x40(%RSP),%YMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0x60(%RSP),%YMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0x80(%RSP),%YMM11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0xa0(%RSP),%YMM12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0xc0(%RSP),%YMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0xe0(%RSP),%YMM14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0x100(%RSP),%YMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
ADD $0x138,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
TEST $0x1,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 408735 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xe5>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST $0x2,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 408768 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x118>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST $0x4,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 4087a3 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x153>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST $0x8,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 4087de <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x18e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST $0x10,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 408819 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x1c9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST $0x20,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 408854 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x204>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST $0x40,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 40888f <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x23f>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %DL,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNS 40869a <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x4a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD $0x1c,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x1c,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
JMP 40869a <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x4a>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST $0x2,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 4086eb <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x9b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x4(%RDI),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x4(%RSI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST $0x4,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 4086f4 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xa4>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x8(%RDI),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x8(%RSI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST $0x8,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 4086fd <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xad>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0xc(%RDI),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0xc(%RSI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST $0x10,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 408706 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xb6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x10(%RDI),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x10(%RSI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST $0x20,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 40870f <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xbf>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x14(%RDI),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x14(%RSI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST $0x40,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 408718 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xc8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x18(%RDI),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x18(%RSI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,0xc(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 407f30 <__svml_sexp_cout_rare_internal>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0xc(%RSP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x18(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RSP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
TEST %DL,%DL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNS 40869a <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0x4a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
JMP 408720 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper+0xd0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
○__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper	0.05	0.01

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code