OV - attention-gnr-256 - Function __svml_expf8

	Function: __svml_expf8_l9	Module: attention-gnr-256	Source: :0-0	Coverage (incl. loops): 1.44% \| (excl. loops): 1.44%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x407900 ENDBR64

0x407904 VMOVUPS	0xac34(%RIP),%YMM1

0x40790c VMOVUPS	0xae6c(%RIP),%YMM2

0x407914 VMOVUPS	0xabe4(%RIP),%YMM3

0x40791c VFMADD213PS	%YMM1,%YMM0,%YMM3

0x407921 VSUBPS	%YMM1,%YMM3,%YMM1

0x407925 VANDPS	0xae93(%RIP),%YMM0,%YMM4

0x40792d VPCMPGTD	0xaecb(%RIP),%YMM4,%YMM4

0x407935 VMOVMSKPS	%YMM4,%EAX

0x407939 VPSLLD	$0x17,%YMM3,%YMM3

0x40793e VMOVUPS	0xac3a(%RIP),%YMM4

0x407946 VFNMADD213PS	%YMM0,%YMM1,%YMM4

0x40794b VFNMADD231PS	0xac6c(%RIP),%YMM1,%YMM4

0x407954 VFMADD213PS	0xade3(%RIP),%YMM4,%YMM2

0x40795d VFMADD213PS	0xad9a(%RIP),%YMM4,%YMM2

0x407966 VFMADD213PS	0xad51(%RIP),%YMM4,%YMM2

0x40796f VFMADD213PS	0xad08(%RIP),%YMM4,%YMM2

0x407978 VFMADD213PS	0xacbf(%RIP),%YMM4,%YMM2

0x407981 VPADDD	%YMM2,%YMM3,%YMM1

0x407985 TEST	%EAX,%EAX

0x407987 JNE	40798e

0x407989 VMOVAPS	%YMM1,%YMM0

0x40798d RET

0x40798e MOVZX	%AL,%EAX

0x407991 VMOVUPS	0xaea7(%RIP),%YMM2

0x407999 VBROADCASTSS	0xa81e(%RIP),%YMM3

0x4079a2 VCMPPS	$0x1,%YMM0,%YMM2,%YMM2

0x4079a7 VBLENDVPS	%YMM2,%YMM3,%YMM1,%YMM1

0x4079ad VCMPPS	$0x1,0xaeca(%RIP),%YMM0,%YMM3

0x4079b6 VANDNPS	%YMM1,%YMM3,%YMM1

0x4079ba VORPS	%YMM3,%YMM2,%YMM2

0x4079be VMOVMSKPS	%YMM2,%ECX

0x4079c2 ANDN	%EAX,%ECX,%EDX

0x4079c7 JE	407989

0x4079c9 PUSH	%RBP

0x4079ca MOV	%RSP,%RBP

0x4079cd PUSH	%RSI

0x4079ce PUSH	%RDI

0x4079cf AND	$-0x40,%RSP

0x4079d3 SUB	$0x80,%RSP

0x4079da VMOVUPS	%YMM0,0x40(%RSP)

0x4079e0 VMOVUPS	%YMM1,(%RSP)

0x4079e5 LEA	0x40(%RSP),%RDI

0x4079ea MOV	%RSP,%RSI

0x4079ed CALL	407a10 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper>

0x4079f3 VMOVUPS	(%RSP),%YMM1

0x4079f8 LEA	-0x10(%RBP),%RSP

0x4079fc POP	%RDI

0x4079fd POP	%RSI

0x4079fe POP	%RBP

0x4079ff VMOVAPS	%YMM1,%YMM0

0x407a03 RET

0x407a04 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○55.56	main	attention_v2.cpp:53	attention-gnr-256
○37.04	main	attention_v2.cpp:56	attention-gnr-256
►3.70+	__svml_expf8		attention-gnr-256
○	__svml_expf8_mask_e9		attention-gnr-256
○	main	attention_v2.cpp:56	attention-gnr-256
►3.70+	__svml_expf8		attention-gnr-256
○	__svml_expf8_mask_e9		attention-gnr-256
○	main	attention_v2.cpp:53	attention-gnr-256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 1.44% of application time for run run_0

Source file and lines
Module	attention-gnr-256

This function has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside function: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Your function is highly vectorized. Only 47% of vector register length is used (average across all SSE/AVX instructions).

Details

93% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

95% of SSE/AVX loads are used in vector version.
85% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

FMA

Detected 64 FMA (fused multiply-add) operations.

Type of elements and instruction set

10 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 136 FP arithmetical operations:

72: addition or subtraction (64 inside FMA instructions)
64: multiply (all inside FMA instructions)

The binary function is loading 440 bytes (110 single precision FP elements). The binary function is storing 21 bytes (5 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.29 FP operations per loaded or stored byte.

General properties

nb instructions	35.67
nb uops	36.67
loop length	199.33
used x86 registers	3.67
used mmx registers	0
used xmm registers	0
used ymm registers	5
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	6.11 cycles
front end	6.11 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	6.72	6.72	5.44	5.44	1.00	5.89	3.00	1.00	1.00	1.00	2.33	5.44
cycles	6.72	6.72	5.44	5.44	1.00	5.89	3.00	1.00	1.00	1.00	2.33	5.44

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.11
Dispatch	6.72
Overall L1	7.22

Vectorization ratios

INT

all	75%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	68%

all	97%
load	95%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	93%

INT+FP

all	93%
load	95%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	85%

Vector efficiency ratios

INT

all	39%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	36%

all	48%
load	47%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	47%

INT+FP

all	47%
load	48%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	44%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.22 cycles. At this rate:

32% of peak load performance is reached (62.08 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.42 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

The code analyzed by CQA in that panel excludes loops and represents 1.44% of application time for run run_0

Source file and lines
Module	attention-gnr-256

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Your function is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.50 to 4.33 cycles (1.27x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

FMA

Detected 64 FMA (fused multiply-add) operations.

Vector unaligned load/store instructions

Detected 4 optimal vector unaligned load/store instructions.

Details

VMOVUPS: 4 occurrences►

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries
inform your compiler that your arrays are vector aligned: read your compiler manual.

Type of elements and instruction set

9 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 136 FP arithmetical operations:

72: addition or subtraction (64 inside FMA instructions)
64: multiply (all inside FMA instructions)

The binary function is loading 384 bytes (96 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.35 FP operations per loaded or stored byte.

General properties

nb instructions	23
nb uops	22
loop length	142
used x86 registers	1
used mmx registers	0
used xmm registers	0
used ymm registers	5
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.67 cycles
front end	3.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.50	5.50	4.33	4.33	0.00	3.00	2.00	0.00	0.00	0.00	1.00	4.33
cycles	5.50	5.50	4.33	4.33	0.00	3.00	2.00	0.00	0.00	0.00	1.00	4.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.67
Dispatch	5.50
Overall L1	5.50

Vectorization ratios

INT

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

INT

all	50%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	50%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	50%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.50 cycles. At this rate:

36% of peak load performance is reached (69.82 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 407900

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ENDBR64																N/A
VMOVUPS 0xac34(%RIP),%YMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0xae6c(%RIP),%YMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0xabe4(%RIP),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD213PS %YMM1,%YMM0,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VSUBPS %YMM1,%YMM3,%YMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VANDPS 0xae93(%RIP),%YMM0,%YMM4	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPCMPGTD 0xaecb(%RIP),%YMM4,%YMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	0-3	0.50	vect (50.0%)
VMOVMSKPS %YMM4,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	5	1	vect (50.0%)
VPSLLD $0x17,%YMM3,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (50.0%)
VMOVUPS 0xac3a(%RIP),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFNMADD213PS %YMM0,%YMM1,%YMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFNMADD231PS 0xac6c(%RIP),%YMM1,%YMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PS 0xade3(%RIP),%YMM4,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PS 0xad9a(%RIP),%YMM4,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PS 0xad51(%RIP),%YMM4,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PS 0xad08(%RIP),%YMM4,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PS 0xacbf(%RIP),%YMM4,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VPADDD %YMM2,%YMM3,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
TEST %EAX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 40798e <__svml_expf8_l9+0x8e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVAPS %YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A

The code analyzed by CQA in that panel excludes loops and represents 1.44% of application time for run run_0

Source file and lines
Module	attention-gnr-256

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.83 to 7.33 cycles (1.20x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is partially vectorized. Only 44% of vector register length is used (average across all SSE/AVX instructions).

Details

87% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

93% of SSE/AVX loads are used in vector version.
73% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

FMA

Detected 64 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper: 1 occurrences►

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VBLENDVPS: 1 occurrences►
VCMPPS: 1 occurrences►

Vector unaligned load/store instructions

Detected 8 optimal vector unaligned load/store instructions.

Details

VMOVUPS: 8 occurrences►

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries
inform your compiler that your arrays are vector aligned: read your compiler manual.

Conversion instructions

Detected expensive conversion instructions.

Details

MOVZX: 1 occurrences►

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

11 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 136 FP arithmetical operations:

72: addition or subtraction (64 inside FMA instructions)
64: multiply (all inside FMA instructions)

The binary function is loading 484 bytes (121 single precision FP elements). The binary function is storing 64 bytes (16 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	50
nb uops	53
loop length	255
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	5
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.83 cycles
front end	8.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.33	7.33	6.67	6.67	3.00	7.33	4.00	3.00	3.00	3.00	4.00	6.67
cycles	7.33	7.33	6.67	6.67	3.00	7.33	4.00	3.00	3.00	3.00	4.00	6.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.83
Dispatch	7.33
Overall L1	8.83

Vectorization ratios

INT

all	50%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	40%

all	96%
load	93%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	90%

INT+FP

all	87%
load	93%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	73%

Vector efficiency ratios

INT

all	29%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	48%
load	47%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	45%

INT+FP

all	44%
load	47%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	38%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.83 cycles. At this rate:

28% of peak load performance is reached (54.79 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.25 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 8.83 to 7.33 cycles (1.20x speedup).

ASM code

In the binary file, the address of the function is: 407900

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ENDBR64																N/A
VMOVUPS 0xac34(%RIP),%YMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0xae6c(%RIP),%YMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0xabe4(%RIP),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD213PS %YMM1,%YMM0,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VSUBPS %YMM1,%YMM3,%YMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VANDPS 0xae93(%RIP),%YMM0,%YMM4	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPCMPGTD 0xaecb(%RIP),%YMM4,%YMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	0-3	0.50	vect (50.0%)
VMOVMSKPS %YMM4,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	5	1	vect (50.0%)
VPSLLD $0x17,%YMM3,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (50.0%)
VMOVUPS 0xac3a(%RIP),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFNMADD213PS %YMM0,%YMM1,%YMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFNMADD231PS 0xac6c(%RIP),%YMM1,%YMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PS 0xade3(%RIP),%YMM4,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PS 0xad9a(%RIP),%YMM4,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PS 0xad51(%RIP),%YMM4,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PS 0xad08(%RIP),%YMM4,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PS 0xacbf(%RIP),%YMM4,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VPADDD %YMM2,%YMM3,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
TEST %EAX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JNE 40798e <__svml_expf8_l9+0x8e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVZX %AL,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPS 0xaea7(%RIP),%YMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VBROADCASTSS 0xa81e(%RIP),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VCMPPS $0x1,%YMM0,%YMM2,%YMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBLENDVPS %YMM2,%YMM3,%YMM1,%YMM1	3	1	1	0	0	0	1	0	0	0	0	0	0	2-3	1	vect (50.0%)
VCMPPS $0x1,0xaeca(%RIP),%YMM0,%YMM3	2	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VANDNPS %YMM1,%YMM3,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VORPS %YMM3,%YMM2,%YMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VMOVMSKPS %YMM2,%ECX	1	1	0	0	0	0	0	0	0	0	0	0	0	5	1	vect (50.0%)
ANDN %EAX,%ECX,%EDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1-2	0.33	scal (6.3%)
JE 407989 <__svml_expf8_l9+0x89>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %RSI	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RDI	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x80,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPS %YMM0,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VMOVUPS %YMM1,(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
LEA 0x40(%RSP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSP,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 407a10 <__ocl_svml_l9__svml_sexp_cout_rare_internal_wrapper>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
VMOVUPS (%RSP),%YMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
LEA -0x10(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
VMOVAPS %YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A

The code analyzed by CQA in that panel excludes loops and represents 1.44% of application time for run run_0

Source file and lines
Module	attention-gnr-256

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Your function is highly vectorized. Only 46% of vector register length is used (average across all SSE/AVX instructions).

Details

92% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

93% of SSE/AVX loads are used in vector version.
84% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

512-bits vectorization

FMA

Detected 64 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VBLENDVPS: 1 occurrences►
VCMPPS: 1 occurrences►

Vector unaligned load/store instructions

Detected 5 optimal vector unaligned load/store instructions.

Details

VMOVUPS: 5 occurrences►

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries
inform your compiler that your arrays are vector aligned: read your compiler manual.

Conversion instructions

Detected expensive conversion instructions.

Details

MOVZX: 1 occurrences►

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

11 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 136 FP arithmetical operations:

72: addition or subtraction (64 inside FMA instructions)
64: multiply (all inside FMA instructions)

The binary function is loading 452 bytes (113 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.30 FP operations per loaded or stored byte.

General properties

nb instructions	34
nb uops	35
loop length	201
used x86 registers	3
used mmx registers	0
used xmm registers	0
used ymm registers	5
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.83 cycles
front end	5.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.33	7.33	5.33	5.33	0.00	7.33	3.00	0.00	0.00	0.00	2.00	5.33
cycles	7.33	7.33	5.33	5.33	0.00	7.33	3.00	0.00	0.00	0.00	2.00	5.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.83
Dispatch	7.33
Overall L1	7.33

Vectorization ratios

INT

all	75%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	66%

all	95%
load	92%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	90%

INT+FP

all	92%
load	93%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	84%

Vector efficiency ratios

INT

all	39%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	35%

all	48%
load	46%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	45%

INT+FP

all	46%
load	47%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	43%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 7.33 cycles. At this rate:

32% of peak load performance is reached (61.64 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 407900

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
ENDBR64																N/A
VMOVUPS 0xac34(%RIP),%YMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0xae6c(%RIP),%YMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VMOVUPS 0xabe4(%RIP),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFMADD213PS %YMM1,%YMM0,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VSUBPS %YMM1,%YMM3,%YMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50	vect (50.0%)
VANDPS 0xae93(%RIP),%YMM0,%YMM4	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
VPCMPGTD 0xaecb(%RIP),%YMM4,%YMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	0-3	0.50	vect (50.0%)
VMOVMSKPS %YMM4,%EAX	1	1	0	0	0	0	0	0	0	0	0	0	0	5	1	vect (50.0%)
VPSLLD $0x17,%YMM3,%YMM3	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (50.0%)
VMOVUPS 0xac3a(%RIP),%YMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VFNMADD213PS %YMM0,%YMM1,%YMM4	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VFNMADD231PS 0xac6c(%RIP),%YMM1,%YMM4	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PS 0xade3(%RIP),%YMM4,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PS 0xad9a(%RIP),%YMM4,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PS 0xad51(%RIP),%YMM4,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PS 0xad08(%RIP),%YMM4,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VFMADD213PS 0xacbf(%RIP),%YMM4,%YMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VPADDD %YMM2,%YMM3,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
TEST %EAX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 40798e <__svml_expf8_l9+0x8e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVAPS %YMM1,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (50.0%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
MOVZX %AL,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVUPS 0xaea7(%RIP),%YMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33	vect (50.0%)
VBROADCASTSS 0xa81e(%RIP),%YMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
VCMPPS $0x1,%YMM0,%YMM2,%YMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (50.0%)
VBLENDVPS %YMM2,%YMM3,%YMM1,%YMM1	3	1	1	0	0	0	1	0	0	0	0	0	0	2-3	1	vect (50.0%)
VCMPPS $0x1,0xaeca(%RIP),%YMM0,%YMM3	2	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50	vect (50.0%)
VANDNPS %YMM1,%YMM3,%YMM1	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VORPS %YMM3,%YMM2,%YMM2	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VMOVMSKPS %YMM2,%ECX	1	1	0	0	0	0	0	0	0	0	0	0	0	5	1	vect (50.0%)
ANDN %EAX,%ECX,%EDX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1-2	0.33	scal (6.3%)
JE 407989 <__svml_expf8_l9+0x89>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Name	Coverage (%)	Time (s)
○__svml_expf8_l9	1.44	0.14

Report Configuration

Vectorization

Details

Workaround

512-bits vectorization

FMA

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

FMA

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

FMA

CALL instructions

Details

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

FMA

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround