OV - attention-gcc-gnr-512 - Loop 31

	Loop Id: 31	Module: attention-gcc-gnr-512	Source: attention_v2.cpp:43-61	Coverage: 0.10%

  (30) 0x402ab8 MOV	-0x40(%RBP),%ESI

  (30) 0x402abb MOV	-0x40(%RBP),%EDI

  (30) 0x402abe SHR	$0x4,%ESI

  (30) 0x402ac1 SAL	$0x6,%RSI

  (30) 0x402ac5 VBROADCASTSS	0x1735(%RIP),%ZMM0

  (30) 0x402acf ADD	%R14,%RSI

  (30) 0x402ad2 MOV	%R14,%RAX

  (30) 0x402ad5 NOPW	%CS:(%RAX,%RAX,1)

    (29) 0x402ae0 VMAXPS	(%RAX),%ZMM0,%ZMM0

    (29) 0x402ae6 ADD	$0x40,%RAX

    (29) 0x402aea CMP	%RAX,%RSI

    (29) 0x402aed JNE	402ae0

  (30) 0x402aef VEXTRACTF32X8	$0x1,%ZMM0,%YMM3

  (30) 0x402af6 VMAXPS	%YMM0,%YMM3,%YMM2

  (30) 0x402afa VMOVAPS	%YMM0,%YMM1

  (30) 0x402afe VEXTRACTF32X4	$0x1,%YMM2,%XMM0

  (30) 0x402b05 VMAXPS	%XMM2,%XMM0,%XMM0

  (30) 0x402b09 VMOVHLPS	%XMM0,%XMM0,%XMM2

  (30) 0x402b0d VMAXPS	%XMM0,%XMM2,%XMM2

  (30) 0x402b11 VSHUFPS	$0x55,%XMM2,%XMM2,%XMM0

  (30) 0x402b16 VMAXPS	%XMM2,%XMM0,%XMM0

  (30) 0x402b1a TEST	$0xf,%DIL

  (30) 0x402b1e JE	402bd2

0x402b24 MOV	%EDI,%EAX

0x402b26 VMAXPS	%YMM3,%YMM1,%YMM1

0x402b2a AND	$-0x10,%EAX

0x402b2d MOV	%EAX,%ESI

0x402b2f MOV	%R15D,%EDI

0x402b32 SUB	%EAX,%EDI

0x402b34 CMP	$0x6,%EDI

0x402b37 JBE	402b72

0x402b39 MOV	-0x88(%RBP),%RDX

0x402b40 ADD	-0x48(%RBP),%RAX

0x402b44 VMAXPS	(%RDX,%RAX,4),%YMM1,%YMM0

0x402b49 INC	%EDI

0x402b4b VEXTRACTF32X4	$0x1,%YMM0,%XMM1

0x402b52 VMAXPS	%XMM0,%XMM1,%XMM0

0x402b56 VMOVHLPS	%XMM0,%XMM0,%XMM1

0x402b5a VMAXPS	%XMM0,%XMM1,%XMM1

0x402b5e VSHUFPS	$0x55,%XMM1,%XMM1,%XMM0

0x402b63 VMAXPS	%XMM1,%XMM0,%XMM0

0x402b67 TEST	$0x7,%DIL

0x402b6b JE	402bd2

0x402b6d AND	$-0x8,%EDI

0x402b70 ADD	%EDI,%ESI

0x402b72 MOVSXD	%ESI,%RAX

0x402b75 VMAXSS	(%R14,%RAX,4),%XMM0,%XMM0

0x402b7b CMP	%ESI,%R15D

0x402b7e JLE	402bd2

0x402b80 LEA	0x2(%RSI),%EDI

0x402b83 VMAXSS	0x4(%R14,%RAX,4),%XMM0,%XMM0

0x402b8a CMP	%EDI,%R15D

0x402b8d JL	402bd2

0x402b8f LEA	0x3(%RSI),%EDI

0x402b92 VMAXSS	0x8(%R14,%RAX,4),%XMM0,%XMM0

0x402b99 CMP	%EDI,%R15D

0x402b9c JL	402bd2

0x402b9e LEA	0x4(%RSI),%EDI

0x402ba1 VMAXSS	0xc(%R14,%RAX,4),%XMM0,%XMM0

0x402ba8 CMP	%EDI,%R15D

0x402bab JL	402bd2

0x402bad LEA	0x5(%RSI),%EDI

0x402bb0 VMAXSS	0x10(%R14,%RAX,4),%XMM0,%XMM0

0x402bb7 CMP	%EDI,%R15D

0x402bba JL	402bd2

0x402bbc ADD	$0x6,%ESI

0x402bbf VMAXSS	0x14(%R14,%RAX,4),%XMM0,%XMM0

0x402bc6 CMP	%ESI,%R15D

0x402bc9 JL	402bd2

0x402bcb VMAXSS	0x18(%R14,%RAX,4),%XMM0,%XMM0

  (30) 0x402bd2 MOVL	$0,-0x34(%RBP)

  (30) 0x402bd9 VMOVSS	%XMM0,-0x38(%RBP)

  (30) 0x402bde MOV	%R14,%R12

  (30) 0x402be1 VZEROUPPER

  (30) 0x402be4 NOPL	(%RAX)

    (27) 0x402be8 VMOVSS	(%R12),%XMM1

    (27) 0x402bee ADD	$0x4,%R12

    (27) 0x402bf2 VSUBSS	-0x38(%RBP),%XMM1,%XMM0

    (27) 0x402bf7 CALL	401110 <expf@plt>

    (27) 0x402bfc VADDSS	-0x34(%RBP),%XMM0,%XMM5

    (27) 0x402c01 VMOVSS	%XMM5,-0x34(%RBP)

    (27) 0x402c06 CMP	%R12,%RBX

    (27) 0x402c09 JNE	402be8

  (30) 0x402c0b MOV	-0x60(%RBP),%RAX

  (30) 0x402c0f MOV	-0x48(%RBP),%RCX

  (30) 0x402c13 MOV	%R14,%R13

  (30) 0x402c16 LEA	(%RAX,%RCX,4),%R12

  (30) 0x402c1a NOPW	(%RAX,%RAX,1)

    (28) 0x402c20 VMOVSS	(%R13),%XMM1

    (28) 0x402c26 ADD	$0x4,%R13

    (28) 0x402c2a VSUBSS	-0x38(%RBP),%XMM1,%XMM0

    (28) 0x402c2f ADD	$0x4,%R12

    (28) 0x402c33 CALL	401110 <expf@plt>

    (28) 0x402c38 VDIVSS	-0x34(%RBP),%XMM0,%XMM0

    (28) 0x402c3d VMOVSS	%XMM0,-0x4(%R12)

    (28) 0x402c44 CMP	%R13,%RBX

    (28) 0x402c47 JNE	402c20

  (30) 0x402c49 MOV	-0x54(%RBP),%EDX

  (30) 0x402c4c LEA	0x1(%R15),%R8D

  (30) 0x402c50 CMP	%R8D,%EDX

  (30) 0x402c53 JE	402cd0

  (30) 0x402c55 INCQ	-0x40(%RBP)

  (30) 0x402c59 MOV	-0x80(%RBP),%RDI

  (30) 0x402c5d MOV	-0x50(%RBP),%R13

  (30) 0x402c61 MOV	%EDX,%EAX

  (30) 0x402c63 MOV	-0x40(%RBP),%R15

  (30) 0x402c67 ADD	%RDI,-0x48(%RBP)

  (30) 0x402c6b SUB	%R15D,%EAX

  (30) 0x402c6e MOV	%R13,%RDI

  (30) 0x402c71 LEA	0x4(,%RAX,4),%RDX

  (30) 0x402c79 XOR	%ESI,%ESI

  (30) 0x402c7b MOV	-0x78(%RBP),%R12

  (30) 0x402c7f MOV	%R8D,-0x38(%RBP)

  (30) 0x402c83 ADD	-0x70(%RBP),%R14

  (30) 0x402c87 CALL	401040 <memset@plt>

  (30) 0x402c8c MOV	-0x68(%RBP),%RAX

  (30) 0x402c90 VMOVSS	-0x34(%RBP),%XMM2

  (30) 0x402c95 ADD	%R12,%R13

  (30) 0x402c98 VMOVSS	%XMM2,-0x8(%RAX,%R15,4)

  (30) 0x402c9f MOV	-0x38(%RBP),%R15D

  (30) 0x402ca3 MOV	%R13,-0x50(%RBP)

  (30) 0x402ca7 ADD	%R12,%RBX

  (30) 0x402caa CMP	$0xe,%R15D

  (30) 0x402cae JG	402ab8

/home/eoseret/llm-attention/attention_v2.cpp: 43 - 61

--------------------------------------------------------------------------------

43:    for (int row = 0; row < N; ++row) {

44:       const float *S_row = &S[row * N];

45:

46:       float max_val = -FLT_MAX;

47:       for (int idx = 0; idx <= row; ++idx) // vectorised

48:          if (S_row[idx] > max_val) max_val = S_row[idx];

49:

50:       float sum = 0.0f;

51: #pragma clang loop vectorize(enable)

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

54:

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

57:

58:       for (int idx = row + 1; idx < N; ++idx)

59:          P[row * N + idx] = 0.0f;

60:

61:       D[row] = sum;

Coverage (%)	Name	Source Location	Module
○100.00	main	attention_v2.cpp:283	attention-gcc-gnr-512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.31
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.38
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	micro-operation queue,
Function	softmax(float const, float, float*, int)
Source	attention_v2.cpp:47-48
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.17
CQA cycles if no scalar integer	7.00
CQA cycles if FP arith vectorized	9.17
CQA cycles if fully vectorized	1.09
Front-end cycles	9.17
P0 cycles	8.60
P1 cycles	8.60
P2 cycles	3.33
P3 cycles	3.33
P4 cycles	0.00
P5 cycles	8.50
P6 cycles	8.70
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	8.60
P11 cycles	3.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.00
Nb uops	47.00
Nb loads	10.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.29
Bytes prefetched	0.00
Bytes loaded	76.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	32.00
Vectorization ratio load	12.50
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	34.78
Vector-efficiency ratio all	13.75
Vector-efficiency ratio load	11.72
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.40

Metric	Value
CQA speedup if no scalar integer	1.31
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.38
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	micro-operation queue,
Function	softmax(float const, float, float*, int)
Source	attention_v2.cpp:47-48
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.17
CQA cycles if no scalar integer	7.00
CQA cycles if FP arith vectorized	9.17
CQA cycles if fully vectorized	1.09
Front-end cycles	9.17
P0 cycles	8.60
P1 cycles	8.60
P2 cycles	3.33
P3 cycles	3.33
P4 cycles	0.00
P5 cycles	8.50
P6 cycles	8.70
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	8.60
P11 cycles	3.33
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.00
Nb uops	47.00
Nb loads	10.00
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.29
Bytes prefetched	0.00
Bytes loaded	76.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	32.00
Vectorization ratio load	12.50
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	34.78
Vector-efficiency ratio all	13.75
Vector-efficiency ratio load	11.72
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.40

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	softmax(float const, float, float*, int)
Source file and lines	attention_v2.cpp:43-61
Module	attention-gcc-gnr-512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:43-61.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:47-48.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.17 to 7.00 cycles (1.31x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Type of elements and instruction set

7 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 3 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (four at a time). 2 AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 76 bytes (19 single precision FP elements).

General properties

nb instructions	47
nb uops	47
loop length	174
used x86 registers	7
used mmx registers	0
used xmm registers	2
used ymm registers	3
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.17 cycles
front end	9.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.60	8.60	3.33	3.33	0.00	8.50	8.70	0.00	0.00	0.00	8.60	3.33
cycles	8.60	8.60	3.33	3.33	0.00	8.50	8.70	0.00	0.00	0.00	8.60	3.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.17
Dispatch	8.70
Overall L1	9.17

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	53%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	53%

INT+FP

all	32%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	34%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	18%
load	11%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	13%
load	11%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.17 cycles. At this rate:

4% of peak load performance is reached (8.29 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 9.17 to 8.70 cycles (1.05x speedup).

ASM code

In the binary file, the address of the loop is: 402b2f

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
MOV %EDI,%EAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
VMAXPS %YMM3,%YMM1,%YMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
AND $-0x10,%EAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %EAX,%EDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
CMP $0x6,%EDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
JBE 402b72 <_Z7softmaxPKfPfS1_i+0x142>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x88(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
ADD -0x48(%RBP),%RAX	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	N/A
VMAXPS (%RDX,%RAX,4),%YMM1,%YMM0	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
INC %EDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
VEXTRACTF32X4 $0x1,%YMM0,%XMM1	1	0	0	0	0	1	0	0	0	3	1	vect (25.0%)
VMAXPS %XMM0,%XMM1,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVHLPS %XMM0,%XMM0,%XMM1	1	0	0	0	0	1	0	0	0	1	1	vect (12.5%)
VMAXPS %XMM0,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPS $0x55,%XMM1,%XMM1,%XMM0	1	0	0.50	0	0	0.50	0	0	0	1	0.50	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
TEST $0x7,%DIL	1	0.20	0.20	0	0	0.20	0.20	0.20	0	2	0.20	N/A
JE 402bd2 <_Z7softmaxPKfPfS1_i+0x1a2>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
AND $-0x8,%EDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	scal (6.3%)
ADD %EDI,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOVSXD %ESI,%RAX	1	0	0.33	0	0	0.33	0	0.33	0	1	0.33	N/A
VMAXSS (%R14,%RAX,4),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (6.3%)
CMP %ESI,%R15D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
JLE 402bd2 <_Z7softmaxPKfPfS1_i+0x1a2>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
LEA 0x2(%RSI),%EDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VMAXSS 0x4(%R14,%RAX,4),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (6.3%)
CMP %EDI,%R15D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
JL 402bd2 <_Z7softmaxPKfPfS1_i+0x1a2>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
LEA 0x3(%RSI),%EDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VMAXSS 0x8(%R14,%RAX,4),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (6.3%)
CMP %EDI,%R15D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
JL 402bd2 <_Z7softmaxPKfPfS1_i+0x1a2>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
LEA 0x4(%RSI),%EDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VMAXSS 0xc(%R14,%RAX,4),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (6.3%)
CMP %EDI,%R15D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
JL 402bd2 <_Z7softmaxPKfPfS1_i+0x1a2>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
LEA 0x5(%RSI),%EDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VMAXSS 0x10(%R14,%RAX,4),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (6.3%)
CMP %EDI,%R15D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
JL 402bd2 <_Z7softmaxPKfPfS1_i+0x1a2>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
ADD $0x6,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VMAXSS 0x14(%R14,%RAX,4),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (6.3%)
CMP %ESI,%R15D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JL 402bd2 <_Z7softmaxPKfPfS1_i+0x1a2>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VMAXSS 0x18(%R14,%RAX,4),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (6.3%)

Function	softmax(float const, float, float*, int)
Source file and lines	attention_v2.cpp:43-61
Module	attention-gcc-gnr-512

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:43-61.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:47-48.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.17 to 7.00 cycles (1.31x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 76 bytes (19 single precision FP elements).

General properties

nb instructions	47
nb uops	47
loop length	174
used x86 registers	7
used mmx registers	0
used xmm registers	2
used ymm registers	3
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.17 cycles
front end	9.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.60	8.60	3.33	3.33	0.00	8.50	8.70	0.00	0.00	0.00	8.60	3.33
cycles	8.60	8.60	3.33	3.33	0.00	8.50	8.70	0.00	0.00	0.00	8.60	3.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.17
Dispatch	8.70
Overall L1	9.17

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	53%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	53%

INT+FP

all	32%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	34%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	18%
load	11%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	13%
load	11%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.17 cycles. At this rate:

4% of peak load performance is reached (8.29 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 402b2f

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
MOV %EDI,%EAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
VMAXPS %YMM3,%YMM1,%YMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (50.0%)
AND $-0x10,%EAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %EAX,%EDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
CMP $0x6,%EDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
JBE 402b72 <_Z7softmaxPKfPfS1_i+0x142>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x88(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
ADD -0x48(%RBP),%RAX	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	N/A
VMAXPS (%RDX,%RAX,4),%YMM1,%YMM0	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (50.0%)
INC %EDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
VEXTRACTF32X4 $0x1,%YMM0,%XMM1	1	0	0	0	0	1	0	0	0	3	1	vect (25.0%)
VMAXPS %XMM0,%XMM1,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVHLPS %XMM0,%XMM0,%XMM1	1	0	0	0	0	1	0	0	0	1	1	vect (12.5%)
VMAXPS %XMM0,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPS $0x55,%XMM1,%XMM1,%XMM0	1	0	0.50	0	0	0.50	0	0	0	1	0.50	vect (25.0%)
VMAXPS %XMM1,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
TEST $0x7,%DIL	1	0.20	0.20	0	0	0.20	0.20	0.20	0	2	0.20	N/A
JE 402bd2 <_Z7softmaxPKfPfS1_i+0x1a2>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
AND $-0x8,%EDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	scal (6.3%)
ADD %EDI,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOVSXD %ESI,%RAX	1	0	0.33	0	0	0.33	0	0.33	0	1	0.33	N/A
VMAXSS (%R14,%RAX,4),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (6.3%)
CMP %ESI,%R15D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
JLE 402bd2 <_Z7softmaxPKfPfS1_i+0x1a2>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
LEA 0x2(%RSI),%EDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VMAXSS 0x4(%R14,%RAX,4),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (6.3%)
CMP %EDI,%R15D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
JL 402bd2 <_Z7softmaxPKfPfS1_i+0x1a2>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
LEA 0x3(%RSI),%EDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VMAXSS 0x8(%R14,%RAX,4),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (6.3%)
CMP %EDI,%R15D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
JL 402bd2 <_Z7softmaxPKfPfS1_i+0x1a2>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
LEA 0x4(%RSI),%EDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VMAXSS 0xc(%R14,%RAX,4),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (6.3%)
CMP %EDI,%R15D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
JL 402bd2 <_Z7softmaxPKfPfS1_i+0x1a2>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
LEA 0x5(%RSI),%EDI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VMAXSS 0x10(%R14,%RAX,4),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (6.3%)
CMP %EDI,%R15D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
JL 402bd2 <_Z7softmaxPKfPfS1_i+0x1a2>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
ADD $0x6,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VMAXSS 0x14(%R14,%RAX,4),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (6.3%)
CMP %ESI,%R15D	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JL 402bd2 <_Z7softmaxPKfPfS1_i+0x1a2>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VMAXSS 0x18(%R14,%RAX,4),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (6.3%)

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code