OV - attention-gcc-gnr-512 - Function std::mersenne_twister_engine<unsigned long, 32ul, 624ul, 397ul, 31ul, 2567483615ul, 11ul, 4294967295ul, 7ul, 2636928640ul, 15ul, 4022730752ul, 18ul, 1812433253ul>::_M_gen

	Function: std::mersenne_twister_engine<unsigned long, 32ul, 624ul, 397ul, 31ul, 2567483615ul, 11ul, ...	Module: attention-gcc-gnr-512	Source: random.tcc:397-425 [...]	Coverage (incl. loops): 0.10% \| (excl. loops): 0.00%

/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc: 397 - 425

--------------------------------------------------------------------------------

397:     mersenne_twister_engine<_UIntType, __w, __n, __m, __r, __a, __u, __d,

[...]

404:       for (size_t __k = 0; __k < (__n - __m); ++__k)

405:         {

406: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

407: 			   | (_M_x[__k + 1] & __lower_mask));

408: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

409: 		       ^ ((__y & 0x01) ? __a : 0));

410:         }

411:

412:       for (size_t __k = (__n - __m); __k < (__n - 1); ++__k)

413: 	{

414: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

415: 			   | (_M_x[__k + 1] & __lower_mask));

416: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

417: 		       ^ ((__y & 0x01) ? __a : 0));

418: 	}

419:

420:       _UIntType __y = ((_M_x[__n - 1] & __upper_mask)

421: 		       | (_M_x[0] & __lower_mask));

422:       _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1)

423: 		       ^ ((__y & 0x01) ? __a : 0));

424:       _M_p = 0;

425:     }

0x403300 MOV	$-0x80000000,%RCX

0x403307 MOV	$0x7fffffff,%ESI

0x40330c MOV	$0x1,%R9D

0x403312 MOV	$-0x66f74f21,%R8D

0x403318 LEA	0x700(%RDI),%RDX

0x40331f MOV	%RDI,%RAX

0x403322 VPBROADCASTQ	%RCX,%ZMM5

0x403328 VPBROADCASTQ	%RSI,%ZMM4

0x40332e VPBROADCASTQ	%R9,%ZMM3

0x403334 VPBROADCASTQ	%R8,%ZMM2

0x40333a NOPW	(%RAX,%RAX,1)

(37) 0x403340 VPANDQ	0x8(%RAX),%ZMM4,%ZMM1

(37) 0x40334a VMOVDQA64	%ZMM5,%ZMM0

(37) 0x403350 VPTERNLOGQ	$-0x14,(%RAX),%ZMM1,%ZMM0

(37) 0x403357 VPSRLQ	$0x1,%ZMM0,%ZMM1

(37) 0x40335e VPANDQ	%ZMM3,%ZMM0,%ZMM0

(37) 0x403364 VPMULLQ	%ZMM2,%ZMM0,%ZMM0

(37) 0x40336a ADD	$0x40,%RAX

(37) 0x40336e VPTERNLOGQ	$-0x6a,0xc28(%RAX),%ZMM0,%ZMM1

(37) 0x403379 VMOVDQU64	%ZMM1,-0x40(%RAX)

(37) 0x403380 CMP	%RAX,%RDX

(37) 0x403383 JNE	403340

0x403385 VPBROADCASTQ	%RSI,%XMM1

0x40338b VPANDQ	0x708(%RDI),%XMM1,%XMM1

0x403395 VPBROADCASTQ	%RCX,%XMM0

0x40339b VPTERNLOGQ	$-0x14,0x700(%RDI),%XMM1,%XMM0

0x4033a3 MOV	0x710(%RDI),%RAX

0x4033aa VPBROADCASTQ	%R9,%XMM1

0x4033b0 MOV	0x718(%RDI),%RDX

0x4033b7 VPSRLQ	$0x1,%XMM0,%XMM2

0x4033bc VPANDQ	%XMM1,%XMM0,%XMM0

0x4033c2 VPBROADCASTQ	%R8,%XMM1

0x4033c8 AND	$0x7fffffff,%EDX

0x4033ce VPMULLQ	%XMM1,%XMM0,%XMM0

0x4033d4 AND	$-0x80000000,%RAX

0x4033da OR	%RDX,%RAX

0x4033dd MOV	%RAX,%RDX

0x4033e0 SHR	$0x1,%RDX

0x4033e3 AND	$0x1,%EAX

0x4033e6 NEG	%RAX

0x4033e9 XOR	0x1378(%RDI),%RDX

0x4033f0 AND	$-0x66f74f21,%EAX

0x4033f5 XOR	%RDX,%RAX

0x4033f8 VPTERNLOGQ	$-0x6a,0x1368(%RDI),%XMM0,%XMM2

0x403403 MOV	$-0x80000000,%RCX

0x40340a MOV	$0x7fffffff,%ESI

0x40340f MOV	$0x1,%R9D

0x403415 MOV	$-0x66f74f21,%R8D

0x40341b MOV	%RAX,0x710(%RDI)

0x403422 VMOVDQU	%XMM2,0x700(%RDI)

0x40342a LEA	0x718(%RDI),%RAX

0x403431 LEA	0x1358(%RDI),%RDX

0x403438 VPBROADCASTQ	%RCX,%ZMM5

0x40343e VPBROADCASTQ	%RSI,%ZMM4

0x403444 VPBROADCASTQ	%R9,%ZMM3

0x40344a VPBROADCASTQ	%R8,%ZMM2

0x403450 NOPW	%CS:(%RAX,%RAX,1)

0x40345b NOPW	%CS:(%RAX,%RAX,1)

0x403466 NOPW	%CS:(%RAX,%RAX,1)

0x403471 NOPW	%CS:(%RAX,%RAX,1)

0x40347c NOPL	(%RAX)

(38) 0x403480 VPANDQ	0x8(%RAX),%ZMM4,%ZMM1

(38) 0x40348a VMOVDQA64	%ZMM5,%ZMM0

(38) 0x403490 VPTERNLOGQ	$-0x14,(%RAX),%ZMM1,%ZMM0

(38) 0x403497 VPSRLQ	$0x1,%ZMM0,%ZMM1

(38) 0x40349e VPANDQ	%ZMM3,%ZMM0,%ZMM0

(38) 0x4034a4 VPMULLQ	%ZMM2,%ZMM0,%ZMM0

(38) 0x4034aa ADD	$0x40,%RAX

(38) 0x4034ae VPTERNLOGQ	$-0x6a,-0x758(%RAX),%ZMM0,%ZMM1

(38) 0x4034b9 VMOVDQU64	%ZMM1,-0x40(%RAX)

(38) 0x4034c0 CMP	%RAX,%RDX

(38) 0x4034c3 JNE	403480

0x4034c5 VPBROADCASTQ	%RSI,%YMM1

0x4034cb VPANDQ	0x1360(%RDI),%YMM1,%YMM1

0x4034d5 MOV	0x1378(%RDI),%RAX

0x4034dc MOV	(%RDI),%RDX

0x4034df VPBROADCASTQ	%RCX,%YMM0

0x4034e5 VPTERNLOGQ	$-0x14,0x1358(%RDI),%YMM1,%YMM0

0x4034f0 AND	$0x7fffffff,%EDX

0x4034f6 VPBROADCASTQ	%R9,%YMM1

0x4034fc AND	$-0x80000000,%RAX

0x403502 OR	%RDX,%RAX

0x403505 VPSRLQ	$0x1,%YMM0,%YMM2

0x40350a VPANDQ	%YMM1,%YMM0,%YMM0

0x403510 VPBROADCASTQ	%R8,%YMM1

0x403516 VPMULLQ	%YMM1,%YMM0,%YMM0

0x40351c MOV	%RAX,%RDX

0x40351f SHR	$0x1,%RDX

0x403522 AND	$0x1,%EAX

0x403525 NEG	%RAX

0x403528 XOR	0xc60(%RDI),%RDX

0x40352f AND	$-0x66f74f21,%EAX

0x403534 XOR	%RDX,%RAX

0x403537 MOV	%RAX,0x1378(%RDI)

0x40353e MOVQ	$0,0x1380(%RDI)

0x403549 VPTERNLOGQ	$-0x6a,0xc40(%RDI),%YMM0,%YMM2

0x403551 VMOVDQU	%YMM2,0x1358(%RDI)

0x403559 VZEROUPPER

0x40355c RET

Coverage (%)	Name	Source Location	Module
○50.00	main	random.tcc:462	attention-gcc-gnr-512
○50.00	main	random.tcc:462	attention-gcc-gnr-512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run run_0

Source file and lines	random.tcc:397-425
Module	attention-gcc-gnr-512

The function is defined in /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:397,404-425.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is poorly vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 16.00 to 2.67 cycles (6.00x speedup).

Details

22% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX loads are used in vector version.
40% of SSE/AVX stores are used in vector version.
19% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPMULLQ: 2 occurrences►
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:408
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:416
VPTERNLOGQ: 4 occurrences►
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:406
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:408
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:414
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:416
VZEROUPPER: 1 occurrences►
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:412

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 192 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	77
nb uops	90
loop length	467
used x86 registers	7
used mmx registers	0
used xmm registers	3
used ymm registers	3
used zmm registers	4
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.00 cycles
front end	15.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	10.80	10.80	4.33	4.33	2.50	16.00	10.80	2.50	2.50	2.50	10.60	4.33
cycles	10.80	10.80	4.33	4.33	2.50	16.00	10.80	2.50	2.50	2.50	10.60	4.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.00
Dispatch	16.00
Overall L1	16.00

Vectorization ratios

all	22%
load	50%
store	40%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Vector efficiency ratios

all	16%
load	25%
store	21%
mul	37%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.00 cycles. At this rate:

6% of peak load performance is reached (12.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.50 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 403300

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV $-0x80000000,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x7fffffff,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $-0x66f74f21,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA 0x700(%RDI),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VPBROADCASTQ %RCX,%ZMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPBROADCASTQ %RSI,%ZMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPBROADCASTQ %R9,%ZMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPBROADCASTQ %R8,%ZMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RSI,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPANDQ 0x708(%RDI),%XMM1,%XMM1	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPBROADCASTQ %RCX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPTERNLOGQ $-0x14,0x700(%RDI),%XMM1,%XMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
MOV 0x710(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPBROADCASTQ %R9,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV 0x718(%RDI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPSRLQ $0x1,%XMM0,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VPANDQ %XMM1,%XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VPBROADCASTQ %R8,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
AND $0x7fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
VPMULLQ %XMM1,%XMM0,%XMM0	5	1.50	1.50	0	0	0	0	0	0	0	0	0	0	15	1.50	vect (25.0%)
AND $-0x80000000,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
OR %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x1,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
AND $0x1,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
NEG %RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
XOR 0x1378(%RDI),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	scal (12.5%)
AND $-0x66f74f21,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
VPTERNLOGQ $-0x6a,0x1368(%RDI),%XMM0,%XMM2	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
MOV $-0x80000000,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x7fffffff,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $-0x66f74f21,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %RAX,0x710(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVDQU %XMM2,0x700(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
LEA 0x718(%RDI),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x1358(%RDI),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RCX,%ZMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPBROADCASTQ %RSI,%ZMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPBROADCASTQ %R9,%ZMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPBROADCASTQ %R8,%ZMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RSI,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPANDQ 0x1360(%RDI),%YMM1,%YMM1	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
MOV 0x1378(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RDI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPBROADCASTQ %RCX,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPTERNLOGQ $-0x14,0x1358(%RDI),%YMM1,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.38	vect (50.0%)
AND $0x7fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
VPBROADCASTQ %R9,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
AND $-0x80000000,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
OR %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
VPSRLQ $0x1,%YMM0,%YMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (50.0%)
VPANDQ %YMM1,%YMM0,%YMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPBROADCASTQ %R8,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPMULLQ %YMM1,%YMM0,%YMM0	5	1.50	1.50	0	0	0	0	0	0	0	0	0	0	15	1.50	vect (50.0%)
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x1,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
AND $0x1,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
NEG %RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
XOR 0xc60(%RDI),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	scal (12.5%)
AND $-0x66f74f21,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RAX,0x1378(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0,0x1380(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VPTERNLOGQ $-0x6a,0xc40(%RDI),%YMM0,%YMM2	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.38	vect (50.0%)
VMOVDQU %YMM2,0x1358(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run run_0

Source file and lines	random.tcc:397-425
Module	attention-gcc-gnr-512

The function is defined in /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:397,404-425.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

22% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX loads are used in vector version.
40% of SSE/AVX stores are used in vector version.
19% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VPMULLQ: 2 occurrences►
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:408
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:416
VPTERNLOGQ: 4 occurrences►
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:406
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:408
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:414
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:416
VZEROUPPER: 1 occurrences►
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:412

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 192 bytes. The binary function is storing 72 bytes.

General properties

nb instructions	77
nb uops	90
loop length	467
used x86 registers	7
used mmx registers	0
used xmm registers	3
used ymm registers	3
used zmm registers	4
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	15.00 cycles
front end	15.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	10.80	10.80	4.33	4.33	2.50	16.00	10.80	2.50	2.50	2.50	10.60	4.33
cycles	10.80	10.80	4.33	4.33	2.50	16.00	10.80	2.50	2.50	2.50	10.60	4.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.00
Dispatch	16.00
Overall L1	16.00

Vectorization ratios

all	22%
load	50%
store	40%
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Vector efficiency ratios

all	16%
load	25%
store	21%
mul	37%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.00 cycles. At this rate:

6% of peak load performance is reached (12.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.50 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 403300

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV $-0x80000000,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x7fffffff,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $-0x66f74f21,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA 0x700(%RDI),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VPBROADCASTQ %RCX,%ZMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPBROADCASTQ %RSI,%ZMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPBROADCASTQ %R9,%ZMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPBROADCASTQ %R8,%ZMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RSI,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPANDQ 0x708(%RDI),%XMM1,%XMM1	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
VPBROADCASTQ %RCX,%XMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPTERNLOGQ $-0x14,0x700(%RDI),%XMM1,%XMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
MOV 0x710(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPBROADCASTQ %R9,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
MOV 0x718(%RDI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPSRLQ $0x1,%XMM0,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (25.0%)
VPANDQ %XMM1,%XMM0,%XMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (25.0%)
VPBROADCASTQ %R8,%XMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
AND $0x7fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
VPMULLQ %XMM1,%XMM0,%XMM0	5	1.50	1.50	0	0	0	0	0	0	0	0	0	0	15	1.50	vect (25.0%)
AND $-0x80000000,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
OR %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x1,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
AND $0x1,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
NEG %RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
XOR 0x1378(%RDI),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	scal (12.5%)
AND $-0x66f74f21,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
VPTERNLOGQ $-0x6a,0x1368(%RDI),%XMM0,%XMM2	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.33	vect (25.0%)
MOV $-0x80000000,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x7fffffff,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $0x1,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV $-0x66f74f21,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %RAX,0x710(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVDQU %XMM2,0x700(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (25.0%)
LEA 0x718(%RDI),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x1358(%RDI),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RCX,%ZMM5	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPBROADCASTQ %RSI,%ZMM4	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPBROADCASTQ %R9,%ZMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPBROADCASTQ %R8,%ZMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RSI,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPANDQ 0x1360(%RDI),%YMM1,%YMM1	1	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.40	vect (50.0%)
MOV 0x1378(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV (%RDI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VPBROADCASTQ %RCX,%YMM0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPTERNLOGQ $-0x14,0x1358(%RDI),%YMM1,%YMM0	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.38	vect (50.0%)
AND $0x7fffffff,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
VPBROADCASTQ %R9,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
AND $-0x80000000,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
OR %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
VPSRLQ $0x1,%YMM0,%YMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	2-4	0.50	vect (50.0%)
VPANDQ %YMM1,%YMM0,%YMM0	1	0.33	0.33	0	0	0	0.33	0	0	0	0	0	0	1	0.33	vect (50.0%)
VPBROADCASTQ %R8,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VPMULLQ %YMM1,%YMM0,%YMM0	5	1.50	1.50	0	0	0	0	0	0	0	0	0	0	15	1.50	vect (50.0%)
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
SHR $0x1,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
AND $0x1,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
NEG %RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
XOR 0xc60(%RDI),%RDX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1-2	0.33	scal (12.5%)
AND $-0x66f74f21,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
XOR %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (12.5%)
MOV %RAX,0x1378(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0,0x1380(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VPTERNLOGQ $-0x6a,0xc40(%RDI),%YMM0,%YMM2	2	0.33	0.33	0.33	0.33	0	0.33	0	0	0	0	0	0.33	1	0.38	vect (50.0%)
VMOVDQU %YMM2,0x1358(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50	vect (50.0%)
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A

Name	Coverage (%)	Time (s)
▼std::mersenne_twister_engine::_M_gen_rand()–	0.10	0.01
○Loop 37 - random.tcc:404-409 - attention-gcc-gnr-512	0.05	0.01
○Loop 38 - random.tcc:412-417 - attention-gcc-gnr-512	0.05	0.01

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code