OV - attention-gcc-gnr-512 - Function softmax(float const*, float*, float*, int)

	Function: softmax(float const, float, float*, int)	Module: attention-gcc-gnr-512	Source: attention_v2.cpp:42-63	Coverage (incl. loops): 7.12% \| (excl. loops): 0.00%

/home/eoseret/llm-attention/attention_v2.cpp: 42 - 63

--------------------------------------------------------------------------------

42: {

43:    for (int row = 0; row < N; ++row) {

44:       const float *S_row = &S[row * N];

45:

46:       float max_val = -FLT_MAX;

47:       for (int idx = 0; idx <= row; ++idx) // vectorised

48:          if (S_row[idx] > max_val) max_val = S_row[idx];

49:

50:       float sum = 0.0f;

51: #pragma clang loop vectorize(enable)

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

54:

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

57:

58:       for (int idx = row + 1; idx < N; ++idx)

59:          P[row * N + idx] = 0.0f;

60:

61:       D[row] = sum;

62:    }

63: }

0x402a30 TEST	%ECX,%ECX

0x402a32 JLE	402cf6

0x402a38 LEA	0x8(%RSP),%R10

0x402a3d AND	$-0x40,%RSP

0x402a41 PUSHQ	-0x8(%R10)

0x402a45 MOVSXD	%ECX,%R9

0x402a48 LEA	0x4(,%R9,4),%RAX

0x402a50 PUSH	%RBP

0x402a51 MOV	%RSP,%RBP

0x402a54 PUSH	%R15

0x402a56 XOR	%R15D,%R15D

0x402a59 PUSH	%R14

0x402a5b MOV	%RDI,%R14

0x402a5e PUSH	%R13

0x402a60 PUSH	%R12

0x402a62 PUSH	%R10

0x402a64 PUSH	%RBX

0x402a65 LEA	0x4(%RDI),%RBX

0x402a69 ADD	$-0x80,%RSP

0x402a6d MOV	%RAX,-0x78(%RBP)

0x402a71 LEA	0x4(%RDX),%RAX

0x402a75 MOV	%RAX,-0x50(%RBP)

0x402a79 LEA	(,%R9,4),%RAX

0x402a81 MOV	%ECX,-0x54(%RBP)

0x402a84 MOV	%RSI,-0x68(%RBP)

0x402a88 MOV	%RAX,-0x70(%RBP)

0x402a8c MOVQ	$0,-0x48(%RBP)

0x402a94 MOVQ	$0x1,-0x40(%RBP)

0x402a9c MOV	%R9,-0x80(%RBP)

0x402aa0 MOV	%RDI,-0x88(%RBP)

0x402aa7 MOV	%RDX,-0x60(%RBP)

0x402aab CMP	$0xe,%R15D

0x402aaf JLE	402cb4

0x402ab5 NOPL	(%RAX)

    (30) 0x402ab8 MOV	-0x40(%RBP),%ESI

    (30) 0x402abb MOV	-0x40(%RBP),%EDI

    (30) 0x402abe SHR	$0x4,%ESI

    (30) 0x402ac1 SAL	$0x6,%RSI

    (30) 0x402ac5 VBROADCASTSS	0x1735(%RIP),%ZMM0

    (30) 0x402acf ADD	%R14,%RSI

    (30) 0x402ad2 MOV	%R14,%RAX

    (30) 0x402ad5 NOPW	%CS:(%RAX,%RAX,1)

      (29) 0x402ae0 VMAXPS	(%RAX),%ZMM0,%ZMM0

      (29) 0x402ae6 ADD	$0x40,%RAX

      (29) 0x402aea CMP	%RAX,%RSI

      (29) 0x402aed JNE	402ae0

    (30) 0x402aef VEXTRACTF32X8	$0x1,%ZMM0,%YMM3

    (30) 0x402af6 VMAXPS	%YMM0,%YMM3,%YMM2

    (30) 0x402afa VMOVAPS	%YMM0,%YMM1

    (30) 0x402afe VEXTRACTF32X4	$0x1,%YMM2,%XMM0

    (30) 0x402b05 VMAXPS	%XMM2,%XMM0,%XMM0

    (30) 0x402b09 VMOVHLPS	%XMM0,%XMM0,%XMM2

    (30) 0x402b0d VMAXPS	%XMM0,%XMM2,%XMM2

    (30) 0x402b11 VSHUFPS	$0x55,%XMM2,%XMM2,%XMM0

    (30) 0x402b16 VMAXPS	%XMM2,%XMM0,%XMM0

    (30) 0x402b1a TEST	$0xf,%DIL

    (30) 0x402b1e JE	402bd2

  (31) 0x402b24 MOV	%EDI,%EAX

  (31) 0x402b26 VMAXPS	%YMM3,%YMM1,%YMM1

  (31) 0x402b2a AND	$-0x10,%EAX

  (31) 0x402b2d MOV	%EAX,%ESI

  (31) 0x402b2f MOV	%R15D,%EDI

  (31) 0x402b32 SUB	%EAX,%EDI

  (31) 0x402b34 CMP	$0x6,%EDI

  (31) 0x402b37 JBE	402b72

  (31) 0x402b39 MOV	-0x88(%RBP),%RDX

  (31) 0x402b40 ADD	-0x48(%RBP),%RAX

  (31) 0x402b44 VMAXPS	(%RDX,%RAX,4),%YMM1,%YMM0

  (31) 0x402b49 INC	%EDI

  (31) 0x402b4b VEXTRACTF32X4	$0x1,%YMM0,%XMM1

  (31) 0x402b52 VMAXPS	%XMM0,%XMM1,%XMM0

  (31) 0x402b56 VMOVHLPS	%XMM0,%XMM0,%XMM1

  (31) 0x402b5a VMAXPS	%XMM0,%XMM1,%XMM1

  (31) 0x402b5e VSHUFPS	$0x55,%XMM1,%XMM1,%XMM0

  (31) 0x402b63 VMAXPS	%XMM1,%XMM0,%XMM0

  (31) 0x402b67 TEST	$0x7,%DIL

  (31) 0x402b6b JE	402bd2

  (31) 0x402b6d AND	$-0x8,%EDI

  (31) 0x402b70 ADD	%EDI,%ESI

  (31) 0x402b72 MOVSXD	%ESI,%RAX

  (31) 0x402b75 VMAXSS	(%R14,%RAX,4),%XMM0,%XMM0

  (31) 0x402b7b CMP	%ESI,%R15D

  (31) 0x402b7e JLE	402bd2

  (31) 0x402b80 LEA	0x2(%RSI),%EDI

  (31) 0x402b83 VMAXSS	0x4(%R14,%RAX,4),%XMM0,%XMM0

  (31) 0x402b8a CMP	%EDI,%R15D

  (31) 0x402b8d JL	402bd2

  (31) 0x402b8f LEA	0x3(%RSI),%EDI

  (31) 0x402b92 VMAXSS	0x8(%R14,%RAX,4),%XMM0,%XMM0

  (31) 0x402b99 CMP	%EDI,%R15D

  (31) 0x402b9c JL	402bd2

  (31) 0x402b9e LEA	0x4(%RSI),%EDI

  (31) 0x402ba1 VMAXSS	0xc(%R14,%RAX,4),%XMM0,%XMM0

  (31) 0x402ba8 CMP	%EDI,%R15D

  (31) 0x402bab JL	402bd2

  (31) 0x402bad LEA	0x5(%RSI),%EDI

  (31) 0x402bb0 VMAXSS	0x10(%R14,%RAX,4),%XMM0,%XMM0

  (31) 0x402bb7 CMP	%EDI,%R15D

  (31) 0x402bba JL	402bd2

  (31) 0x402bbc ADD	$0x6,%ESI

  (31) 0x402bbf VMAXSS	0x14(%R14,%RAX,4),%XMM0,%XMM0

  (31) 0x402bc6 CMP	%ESI,%R15D

  (31) 0x402bc9 JL	402bd2

  (31) 0x402bcb VMAXSS	0x18(%R14,%RAX,4),%XMM0,%XMM0

    (30) 0x402bd2 MOVL	$0,-0x34(%RBP)

    (30) 0x402bd9 VMOVSS	%XMM0,-0x38(%RBP)

    (30) 0x402bde MOV	%R14,%R12

    (30) 0x402be1 VZEROUPPER

    (30) 0x402be4 NOPL	(%RAX)

      (27) 0x402be8 VMOVSS	(%R12),%XMM1

      (27) 0x402bee ADD	$0x4,%R12

      (27) 0x402bf2 VSUBSS	-0x38(%RBP),%XMM1,%XMM0

      (27) 0x402bf7 CALL	401110 <expf@plt>

      (27) 0x402bfc VADDSS	-0x34(%RBP),%XMM0,%XMM5

      (27) 0x402c01 VMOVSS	%XMM5,-0x34(%RBP)

      (27) 0x402c06 CMP	%R12,%RBX

      (27) 0x402c09 JNE	402be8

    (30) 0x402c0b MOV	-0x60(%RBP),%RAX

    (30) 0x402c0f MOV	-0x48(%RBP),%RCX

    (30) 0x402c13 MOV	%R14,%R13

    (30) 0x402c16 LEA	(%RAX,%RCX,4),%R12

    (30) 0x402c1a NOPW	(%RAX,%RAX,1)

      (28) 0x402c20 VMOVSS	(%R13),%XMM1

      (28) 0x402c26 ADD	$0x4,%R13

      (28) 0x402c2a VSUBSS	-0x38(%RBP),%XMM1,%XMM0

      (28) 0x402c2f ADD	$0x4,%R12

      (28) 0x402c33 CALL	401110 <expf@plt>

      (28) 0x402c38 VDIVSS	-0x34(%RBP),%XMM0,%XMM0

      (28) 0x402c3d VMOVSS	%XMM0,-0x4(%R12)

      (28) 0x402c44 CMP	%R13,%RBX

      (28) 0x402c47 JNE	402c20

    (30) 0x402c49 MOV	-0x54(%RBP),%EDX

    (30) 0x402c4c LEA	0x1(%R15),%R8D

    (30) 0x402c50 CMP	%R8D,%EDX

    (30) 0x402c53 JE	402cd0

    (30) 0x402c55 INCQ	-0x40(%RBP)

    (30) 0x402c59 MOV	-0x80(%RBP),%RDI

    (30) 0x402c5d MOV	-0x50(%RBP),%R13

    (30) 0x402c61 MOV	%EDX,%EAX

    (30) 0x402c63 MOV	-0x40(%RBP),%R15

    (30) 0x402c67 ADD	%RDI,-0x48(%RBP)

    (30) 0x402c6b SUB	%R15D,%EAX

    (30) 0x402c6e MOV	%R13,%RDI

    (30) 0x402c71 LEA	0x4(,%RAX,4),%RDX

    (30) 0x402c79 XOR	%ESI,%ESI

    (30) 0x402c7b MOV	-0x78(%RBP),%R12

    (30) 0x402c7f MOV	%R8D,-0x38(%RBP)

    (30) 0x402c83 ADD	-0x70(%RBP),%R14

    (30) 0x402c87 CALL	401040 <memset@plt>

    (30) 0x402c8c MOV	-0x68(%RBP),%RAX

    (30) 0x402c90 VMOVSS	-0x34(%RBP),%XMM2

    (30) 0x402c95 ADD	%R12,%R13

    (30) 0x402c98 VMOVSS	%XMM2,-0x8(%RAX,%R15,4)

    (30) 0x402c9f MOV	-0x38(%RBP),%R15D

    (30) 0x402ca3 MOV	%R13,-0x50(%RBP)

    (30) 0x402ca7 ADD	%R12,%RBX

    (30) 0x402caa CMP	$0xe,%R15D

    (30) 0x402cae JG	402ab8

(32) 0x402cb4 VBROADCASTSS	0x1547(%RIP),%YMM1

(32) 0x402cbd VMOVSS	0x153f(%RIP),%XMM0

(32) 0x402cc5 XOR	%EAX,%EAX

(32) 0x402cc7 XOR	%ESI,%ESI

(32) 0x402cc9 JMP	402b2f

0x402cce XCHG	%AX,%AX

0x402cd0 MOV	-0x68(%RBP),%RAX

0x402cd4 VMOVSS	-0x34(%RBP),%XMM2

0x402cd9 MOV	%R15D,%EDX

0x402cdc VMOVSS	%XMM2,(%RAX,%RDX,4)

0x402ce1 SUB	$-0x80,%RSP

0x402ce5 POP	%RBX

0x402ce6 POP	%R10

0x402ce8 POP	%R12

0x402cea POP	%R13

0x402cec POP	%R14

0x402cee POP	%R15

0x402cf0 POP	%RBP

0x402cf1 LEA	-0x8(%R10),%RSP

0x402cf5 RET

0x402cf6 RET

0x402cf7 NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○100.00	main	attention_v2.cpp:283	attention-gcc-gnr-512

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run run_0

Source file and lines	attention_v2.cpp:42-63
Module	attention-gcc-gnr-512

The function is defined in /home/eoseret/llm-attention/attention_v2.cpp:42-63.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.50 to 1.50 cycles (6.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 9.50 to 0.81 cycles (11.69x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by writing data to caches/RAM (the store unit is a bottleneck).

Workaround

Write less array elements

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

PUSH: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:42

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	51
nb uops	52
loop length	186
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.67 cycles
front end	8.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.00	1.33	4.00	4.00	9.50	1.33	2.00	9.50	9.50	9.50	1.33	4.00
cycles	2.00	1.33	4.00	4.00	9.50	1.33	2.00	9.50	9.50	9.50	1.33	4.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.67
Dispatch	9.50
Overall L1	9.50

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	9%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.50 cycles. At this rate:

1% of peak load performance is reached (2.11 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.42 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 402a30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
TEST %ECX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 402cf6 <_Z7softmaxPKfPfS1_i+0x2c6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x8(%RSP),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
PUSHQ -0x8(%R10)	2	0	0	0.33	0.33	0.50	0	0	0.50	0.50	0.50	0	0.33	5-12	0.62	N/A
MOVSXD %ECX,%R9	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA 0x4(,%R9,4),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R10	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
LEA 0x4(%RDI),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x4(%RDX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%R9,4),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %ECX,-0x54(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RSI,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0x1,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R9,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP $0xe,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JLE 402cb4 <_Z7softmaxPKfPfS1_i+0x284>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x68(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS -0x34(%RBP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS %XMM2,(%RAX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
LEA -0x8(%R10),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run run_0

Source file and lines	attention_v2.cpp:42-63
Module	attention-gcc-gnr-512

The function is defined in /home/eoseret/llm-attention/attention_v2.cpp:42-63.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.50 to 1.50 cycles (6.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by writing data to caches/RAM (the store unit is a bottleneck).

Workaround

Write less array elements

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

PUSH: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:42

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 20 bytes. The binary function is storing 80 bytes.

General properties

nb instructions	51
nb uops	52
loop length	186
used x86 registers	14
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.67 cycles
front end	8.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.00	1.33	4.00	4.00	9.50	1.33	2.00	9.50	9.50	9.50	1.33	4.00
cycles	2.00	1.33	4.00	4.00	9.50	1.33	2.00	9.50	9.50	9.50	1.33	4.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.67
Dispatch	9.50
Overall L1	9.50

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	9%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.50 cycles. At this rate:

1% of peak load performance is reached (2.11 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.42 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 402a30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
TEST %ECX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 402cf6 <_Z7softmaxPKfPfS1_i+0x2c6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x8(%RSP),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
PUSHQ -0x8(%R10)	2	0	0	0.33	0.33	0.50	0	0	0.50	0.50	0.50	0	0.33	5-12	0.62	N/A
MOVSXD %ECX,%R9	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA 0x4(,%R9,4),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R10	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
LEA 0x4(%RDI),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x4(%RDX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%R9,4),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %ECX,-0x54(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RSI,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVQ $0x1,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R9,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMP $0xe,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JLE 402cb4 <_Z7softmaxPKfPfS1_i+0x284>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x68(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS -0x34(%RBP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVSS %XMM2,(%RAX,%RDX,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SUB $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
LEA -0x8(%R10),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼softmax(float const, float, float*, int)–	7.12	0.71
▼Loop 32 - attention_v2.cpp:43-61 - attention-gcc-gnr-512–	0.00	0.00
▼Loop 31 - attention_v2.cpp:43-61 - attention-gcc-gnr-512–	0.10	0.01
▼Loop 30 - attention_v2.cpp:43-61 - attention-gcc-gnr-512–	0.05	0.01
○Loop 28 - attention_v2.cpp:55-56 - attention-gcc-gnr-512	6.16	0.61
○Loop 27 - attention_v2.cpp:52-53 - attention-gcc-gnr-512	0.81	0.08
○Loop 29 - attention_v2.cpp:47-48 - attention-gcc-gnr-512	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code