OV - attention-gcc-gnr-256 - Loop 31

	Loop Id: 31	Module: attention-gcc-gnr-256	Source: attention_v2.cpp:43-61	Coverage: 0.10%

  (30) 0x402ab8 MOV	%R13D,%EDX

  (30) 0x402abb SHR	$0x3,%EDX

  (30) 0x402abe SAL	$0x5,%RDX

  (30) 0x402ac2 VBROADCASTSS	0x1739(%RIP),%YMM0

  (30) 0x402acb MOV	%R13D,%ECX

  (30) 0x402ace ADD	%R12,%RDX

  (30) 0x402ad1 MOV	%R12,%RAX

  (30) 0x402ad4 NOPW	%CS:(%RAX,%RAX,1)

  (30) 0x402adf NOP

    (29) 0x402ae0 VMAXPS	(%RAX),%YMM0,%YMM0

    (29) 0x402ae4 ADD	$0x20,%RAX

    (29) 0x402ae8 CMP	%RAX,%RDX

    (29) 0x402aeb JNE	402ae0

  (30) 0x402aed VEXTRACTF32X4	$0x1,%YMM0,%XMM3

  (30) 0x402af4 VMAXPS	%XMM0,%XMM3,%XMM1

  (30) 0x402af8 VMOVHLPS	%XMM1,%XMM1,%XMM2

  (30) 0x402afc VMAXPS	%XMM1,%XMM2,%XMM2

  (30) 0x402b00 VSHUFPS	$0x55,%XMM2,%XMM2,%XMM1

  (30) 0x402b05 VMAXPS	%XMM2,%XMM1,%XMM1

  (30) 0x402b09 TEST	$0x7,%CL

  (30) 0x402b0c JE	402c78

0x402b12 MOV	%ECX,%EAX

0x402b14 AND	$-0x8,%EAX

0x402b17 VMAXPS	%XMM3,%XMM0,%XMM0

0x402b1b MOV	%EAX,%ECX

0x402b1d VZEROUPPER

0x402b20 MOV	-0x3c(%RBP),%EDX

0x402b23 SUB	%EAX,%EDX

0x402b25 CMP	$0x2,%EDX

0x402b28 JBE	402b54

0x402b2a MOV	-0x80(%RBP),%RDI

0x402b2e ADD	-0x48(%RBP),%RAX

0x402b32 VMAXPS	(%RDI,%RAX,4),%XMM0,%XMM0

0x402b37 INC	%EDX

0x402b39 VMOVHLPS	%XMM0,%XMM0,%XMM1

0x402b3d VMAXPS	%XMM0,%XMM1,%XMM0

0x402b41 VSHUFPS	$0x55,%XMM0,%XMM0,%XMM1

0x402b46 VMAXPS	%XMM0,%XMM1,%XMM1

0x402b4a TEST	$0x3,%DL

0x402b4d JE	402b79

0x402b4f AND	$-0x4,%EDX

0x402b52 ADD	%EDX,%ECX

0x402b54 MOV	-0x3c(%RBP),%ESI

0x402b57 MOVSXD	%ECX,%RAX

0x402b5a VMAXSS	(%R12,%RAX,4),%XMM1,%XMM1

0x402b60 CMP	%ECX,%ESI

0x402b62 JLE	402b79

0x402b64 ADD	$0x2,%ECX

0x402b67 VMAXSS	0x4(%R12,%RAX,4),%XMM1,%XMM1

0x402b6e CMP	%ECX,%ESI

0x402b70 JL	402b79

0x402b72 VMAXSS	0x8(%R12,%RAX,4),%XMM1,%XMM1

  (30) 0x402b79 MOVL	$0,-0x34(%RBP)

  (30) 0x402b80 MOV	%R12,%R14

  (30) 0x402b83 VMOVSS	%XMM1,-0x38(%RBP)

  (30) 0x402b88 NOPL	(%RAX,%RAX,1)

    (27) 0x402b90 VMOVSS	(%R14),%XMM0

    (27) 0x402b95 ADD	$0x4,%R14

    (27) 0x402b99 VSUBSS	-0x38(%RBP),%XMM0,%XMM0

    (27) 0x402b9e CALL	401110 <expf@plt>

    (27) 0x402ba3 VADDSS	-0x34(%RBP),%XMM0,%XMM5

    (27) 0x402ba8 VMOVSS	%XMM5,-0x34(%RBP)

    (27) 0x402bad CMP	%R14,%RBX

    (27) 0x402bb0 JNE	402b90

  (30) 0x402bb2 MOV	-0x58(%RBP),%RAX

  (30) 0x402bb6 MOV	-0x48(%RBP),%RSI

  (30) 0x402bba MOV	%R12,%R15

  (30) 0x402bbd LEA	(%RAX,%RSI,4),%R14

  (30) 0x402bc1 NOPL	(%RAX)

    (28) 0x402bc8 VMOVSS	(%R15),%XMM0

    (28) 0x402bcd ADD	$0x4,%R15

    (28) 0x402bd1 VSUBSS	-0x38(%RBP),%XMM0,%XMM0

    (28) 0x402bd6 ADD	$0x4,%R14

    (28) 0x402bda CALL	401110 <expf@plt>

    (28) 0x402bdf VDIVSS	-0x34(%RBP),%XMM0,%XMM0

    (28) 0x402be4 VMOVSS	%XMM0,-0x4(%R14)

    (28) 0x402bea CMP	%R15,%RBX

    (28) 0x402bed JNE	402bc8

  (30) 0x402bef MOV	-0x3c(%RBP),%EAX

  (30) 0x402bf2 MOV	-0x40(%RBP),%EDI

  (30) 0x402bf5 LEA	0x1(%RAX),%ECX

  (30) 0x402bf8 CMP	%ECX,%EDI

  (30) 0x402bfa JE	402c80

  (30) 0x402c00 MOV	-0x78(%RBP),%RSI

  (30) 0x402c04 MOV	-0x50(%RBP),%R15

  (30) 0x402c08 INC	%R13

  (30) 0x402c0b MOV	%EDI,%EAX

  (30) 0x402c0d SUB	%R13D,%EAX

  (30) 0x402c10 ADD	%RSI,-0x48(%RBP)

  (30) 0x402c14 MOV	%R15,%RDI

  (30) 0x402c17 XOR	%ESI,%ESI

  (30) 0x402c19 LEA	0x4(,%RAX,4),%RDX

  (30) 0x402c21 MOV	-0x70(%RBP),%R14

  (30) 0x402c25 MOV	%ECX,-0x38(%RBP)

  (30) 0x402c28 ADD	-0x68(%RBP),%R12

  (30) 0x402c2c CALL	401040 <memset@plt>

  (30) 0x402c31 MOV	-0x38(%RBP),%ECX

  (30) 0x402c34 MOV	-0x60(%RBP),%RAX

  (30) 0x402c38 MOV	%ECX,-0x3c(%RBP)

  (30) 0x402c3b VMOVSS	-0x34(%RBP),%XMM2

  (30) 0x402c40 ADD	%R14,%R15

  (30) 0x402c43 ADD	%R14,%RBX

  (30) 0x402c46 CMPL	$0x6,-0x3c(%RBP)

  (30) 0x402c4a MOV	%R15,-0x50(%RBP)

  (30) 0x402c4e VMOVSS	%XMM2,-0x8(%RAX,%R13,4)

  (30) 0x402c55 JG	402ab8

  (30) 0x402c78 VZEROUPPER

  (30) 0x402c7b JMP	402b79

/home/eoseret/llm-attention/attention_v2.cpp: 43 - 61

--------------------------------------------------------------------------------

43:    for (int row = 0; row < N; ++row) {

44:       const float *S_row = &S[row * N];

45:

46:       float max_val = -FLT_MAX;

47:       for (int idx = 0; idx <= row; ++idx) // vectorised

48:          if (S_row[idx] > max_val) max_val = S_row[idx];

49:

50:       float sum = 0.0f;

51: #pragma clang loop vectorize(enable)

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

54:

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

57:

58:       for (int idx = row + 1; idx < N; ++idx)

59:          P[row * N + idx] = 0.0f;

60:

61:       D[row] = sum;

Coverage (%)	Name	Source Location	Module
○100.00	main	attention_v2.cpp:283	attention-gcc-gnr-256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.44
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	10.11
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18
Bottlenecks	micro-operation queue,
Function	softmax(float const, float, float*, int)
Source	attention_v2.cpp:47-48
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	4.17
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	0.59
Front-end cycles	6.00
P0 cycles	5.00
P1 cycles	5.00
P2 cycles	2.67
P3 cycles	2.67
P4 cycles	0.00
P5 cycles	4.90
P6 cycles	5.10
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	5.00
P11 cycles	2.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	32.00
Nb loads	8.00
Nb stores	0.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.67
Bytes prefetched	0.00
Bytes loaded	52.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	43.75
Vectorization ratio load	20.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	53.85
Vector-efficiency ratio all	13.67
Vector-efficiency ratio load	10.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.38

Metric	Value
CQA speedup if no scalar integer	1.44
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	10.11
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18
Bottlenecks	micro-operation queue,
Function	softmax(float const, float, float*, int)
Source	attention_v2.cpp:47-48
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	4.17
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	0.59
Front-end cycles	6.00
P0 cycles	5.00
P1 cycles	5.00
P2 cycles	2.67
P3 cycles	2.67
P4 cycles	0.00
P5 cycles	4.90
P6 cycles	5.10
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	5.00
P11 cycles	2.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	32.00
Nb loads	8.00
Nb stores	0.00
Nb stack references	3.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.67
Bytes prefetched	0.00
Bytes loaded	52.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	43.75
Vectorization ratio load	20.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	53.85
Vector-efficiency ratio all	13.67
Vector-efficiency ratio load	10.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	6.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.38

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	softmax(float const, float, float*, int)
Source file and lines	attention_v2.cpp:43-61
Module	attention-gcc-gnr-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:43-61.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:47-48.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.00 to 4.17 cycles (1.44x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.00 to 0.59 cycles (10.11x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:47

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time). 4 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 52 bytes (13 single precision FP elements).

General properties

nb instructions	31
nb uops	32
loop length	103
used x86 registers	7
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.00	5.00	2.67	2.67	0.00	4.90	5.10	0.00	0.00	0.00	5.00	2.67
cycles	5.00	5.00	2.67	2.67	0.00	4.90	5.10	0.00	0.00	0.00	5.00	2.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.00
Dispatch	5.10
Overall L1	6.00

Vectorization ratios

INT

all	14%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	66%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	66%

INT+FP

all	43%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	53%

Vector efficiency ratios

INT

all	8%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	17%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

INT+FP

all	13%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

4% of peak load performance is reached (8.67 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.00 to 5.10 cycles (1.18x speedup).

ASM code

In the binary file, the address of the loop is: 402b20

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%EAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VMAXPS %XMM3,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV -0x3c(%RBP),%EDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (6.3%)
SUB %EAX,%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
CMP $0x2,%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
JBE 402b54 <_Z7softmaxPKfPfS1_i+0x124>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x80(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
ADD -0x48(%RBP),%RAX	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	N/A
VMAXPS (%RDI,%RAX,4),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (25.0%)
INC %EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
VMOVHLPS %XMM0,%XMM0,%XMM1	1	0	0	0	0	1	0	0	0	1	1	vect (12.5%)
VMAXPS %XMM0,%XMM1,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPS $0x55,%XMM0,%XMM0,%XMM1	1	0	0.50	0	0	0.50	0	0	0	1	0.50	vect (25.0%)
VMAXPS %XMM0,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
TEST $0x3,%DL	1	0.20	0.20	0	0	0.20	0.20	0.20	0	2	0.20	N/A
JE 402b79 <_Z7softmaxPKfPfS1_i+0x149>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
AND $-0x4,%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	scal (6.3%)
ADD %EDX,%ECX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV -0x3c(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOVSXD %ECX,%RAX	1	0	0.33	0	0	0.33	0	0.33	0	1	0.33	N/A
VMAXSS (%R12,%RAX,4),%XMM1,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (6.3%)
CMP %ECX,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
JLE 402b79 <_Z7softmaxPKfPfS1_i+0x149>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
ADD $0x2,%ECX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VMAXSS 0x4(%R12,%RAX,4),%XMM1,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (6.3%)
CMP %ECX,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JL 402b79 <_Z7softmaxPKfPfS1_i+0x149>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VMAXSS 0x8(%R12,%RAX,4),%XMM1,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (6.3%)

Function	softmax(float const, float, float*, int)
Source file and lines	attention_v2.cpp:43-61
Module	attention-gcc-gnr-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:43-61.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:47-48.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.00 to 4.17 cycles (1.44x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:47

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 52 bytes (13 single precision FP elements).

General properties

nb instructions	31
nb uops	32
loop length	103
used x86 registers	7
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	3

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.00 cycles
front end	6.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	5.00	5.00	2.67	2.67	0.00	4.90	5.10	0.00	0.00	0.00	5.00	2.67
cycles	5.00	5.00	2.67	2.67	0.00	4.90	5.10	0.00	0.00	0.00	5.00	2.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.00
Dispatch	5.10
Overall L1	6.00

Vectorization ratios

INT

all	14%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	25%

all	66%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	66%

INT+FP

all	43%
load	20%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	53%

Vector efficiency ratios

INT

all	8%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	17%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

INT+FP

all	13%
load	10%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

4% of peak load performance is reached (8.67 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 402b20

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput	Vectorization
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x8,%EAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	N/A
VMAXPS %XMM3,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	1	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV -0x3c(%RBP),%EDX	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	scal (6.3%)
SUB %EAX,%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
CMP $0x2,%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
JBE 402b54 <_Z7softmaxPKfPfS1_i+0x124>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
MOV -0x80(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
ADD -0x48(%RBP),%RAX	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33	N/A
VMAXPS (%RDI,%RAX,4),%XMM0,%XMM0	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	vect (25.0%)
INC %EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
VMOVHLPS %XMM0,%XMM0,%XMM1	1	0	0	0	0	1	0	0	0	1	1	vect (12.5%)
VMAXPS %XMM0,%XMM1,%XMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPS $0x55,%XMM0,%XMM0,%XMM1	1	0	0.50	0	0	0.50	0	0	0	1	0.50	vect (25.0%)
VMAXPS %XMM0,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	4	0.50	vect (25.0%)
TEST $0x3,%DL	1	0.20	0.20	0	0	0.20	0.20	0.20	0	2	0.20	N/A
JE 402b79 <_Z7softmaxPKfPfS1_i+0x149>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
AND $-0x4,%EDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1-2	0.20	scal (6.3%)
ADD %EDX,%ECX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
MOV -0x3c(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33	N/A
MOVSXD %ECX,%RAX	1	0	0.33	0	0	0.33	0	0.33	0	1	0.33	N/A
VMAXSS (%R12,%RAX,4),%XMM1,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (6.3%)
CMP %ECX,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	scal (6.3%)
JLE 402b79 <_Z7softmaxPKfPfS1_i+0x149>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
ADD $0x2,%ECX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
VMAXSS 0x4(%R12,%RAX,4),%XMM1,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (6.3%)
CMP %ECX,%ESI	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20	N/A
JL 402b79 <_Z7softmaxPKfPfS1_i+0x149>	1	0.50	0	0	0	0	0.50	0	0	0	0.50	N/A
VMAXSS 0x8(%R12,%RAX,4),%XMM1,%XMM1	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50	scal (6.3%)

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code