OV - attention-gcc-gnr-256 - Loop 30

	Loop Id: 30	Module: attention-gcc-gnr-256	Source: attention_v2.cpp:43-61	Coverage: 0.05%

0x402ab8 MOV	%R13D,%EDX

0x402abb SHR	$0x3,%EDX

0x402abe SAL	$0x5,%RDX

0x402ac2 VBROADCASTSS	0x1739(%RIP),%YMM0

0x402acb MOV	%R13D,%ECX

0x402ace ADD	%R12,%RDX

0x402ad1 MOV	%R12,%RAX

0x402ad4 NOPW	%CS:(%RAX,%RAX,1)

0x402adf NOP

  (29) 0x402ae0 VMAXPS	(%RAX),%YMM0,%YMM0

  (29) 0x402ae4 ADD	$0x20,%RAX

  (29) 0x402ae8 CMP	%RAX,%RDX

  (29) 0x402aeb JNE	402ae0

0x402aed VEXTRACTF32X4	$0x1,%YMM0,%XMM3

0x402af4 VMAXPS	%XMM0,%XMM3,%XMM1

0x402af8 VMOVHLPS	%XMM1,%XMM1,%XMM2

0x402afc VMAXPS	%XMM1,%XMM2,%XMM2

0x402b00 VSHUFPS	$0x55,%XMM2,%XMM2,%XMM1

0x402b05 VMAXPS	%XMM2,%XMM1,%XMM1

0x402b09 TEST	$0x7,%CL

0x402b0c JE	402c78

0x402b79 MOVL	$0,-0x34(%RBP)

0x402b80 MOV	%R12,%R14

0x402b83 VMOVSS	%XMM1,-0x38(%RBP)

0x402b88 NOPL	(%RAX,%RAX,1)

  (27) 0x402b90 VMOVSS	(%R14),%XMM0

  (27) 0x402b95 ADD	$0x4,%R14

  (27) 0x402b99 VSUBSS	-0x38(%RBP),%XMM0,%XMM0

  (27) 0x402b9e CALL	401110 <expf@plt>

  (27) 0x402ba3 VADDSS	-0x34(%RBP),%XMM0,%XMM5

  (27) 0x402ba8 VMOVSS	%XMM5,-0x34(%RBP)

  (27) 0x402bad CMP	%R14,%RBX

  (27) 0x402bb0 JNE	402b90

0x402bb2 MOV	-0x58(%RBP),%RAX

0x402bb6 MOV	-0x48(%RBP),%RSI

0x402bba MOV	%R12,%R15

0x402bbd LEA	(%RAX,%RSI,4),%R14

0x402bc1 NOPL	(%RAX)

  (28) 0x402bc8 VMOVSS	(%R15),%XMM0

  (28) 0x402bcd ADD	$0x4,%R15

  (28) 0x402bd1 VSUBSS	-0x38(%RBP),%XMM0,%XMM0

  (28) 0x402bd6 ADD	$0x4,%R14

  (28) 0x402bda CALL	401110 <expf@plt>

  (28) 0x402bdf VDIVSS	-0x34(%RBP),%XMM0,%XMM0

  (28) 0x402be4 VMOVSS	%XMM0,-0x4(%R14)

  (28) 0x402bea CMP	%R15,%RBX

  (28) 0x402bed JNE	402bc8

0x402bef MOV	-0x3c(%RBP),%EAX

0x402bf2 MOV	-0x40(%RBP),%EDI

0x402bf5 LEA	0x1(%RAX),%ECX

0x402bf8 CMP	%ECX,%EDI

0x402bfa JE	402c80

0x402c00 MOV	-0x78(%RBP),%RSI

0x402c04 MOV	-0x50(%RBP),%R15

0x402c08 INC	%R13

0x402c0b MOV	%EDI,%EAX

0x402c0d SUB	%R13D,%EAX

0x402c10 ADD	%RSI,-0x48(%RBP)

0x402c14 MOV	%R15,%RDI

0x402c17 XOR	%ESI,%ESI

0x402c19 LEA	0x4(,%RAX,4),%RDX

0x402c21 MOV	-0x70(%RBP),%R14

0x402c25 MOV	%ECX,-0x38(%RBP)

0x402c28 ADD	-0x68(%RBP),%R12

0x402c2c CALL	401040 <memset@plt>

0x402c31 MOV	-0x38(%RBP),%ECX

0x402c34 MOV	-0x60(%RBP),%RAX

0x402c38 MOV	%ECX,-0x3c(%RBP)

0x402c3b VMOVSS	-0x34(%RBP),%XMM2

0x402c40 ADD	%R14,%R15

0x402c43 ADD	%R14,%RBX

0x402c46 CMPL	$0x6,-0x3c(%RBP)

0x402c4a MOV	%R15,-0x50(%RBP)

0x402c4e VMOVSS	%XMM2,-0x8(%RAX,%R13,4)

0x402c55 JG	402ab8

0x402c78 VZEROUPPER

0x402c7b JMP	402b79

/home/eoseret/llm-attention/attention_v2.cpp: 43 - 61

--------------------------------------------------------------------------------

43:    for (int row = 0; row < N; ++row) {

44:       const float *S_row = &S[row * N];

45:

46:       float max_val = -FLT_MAX;

47:       for (int idx = 0; idx <= row; ++idx) // vectorised

48:          if (S_row[idx] > max_val) max_val = S_row[idx];

49:

50:       float sum = 0.0f;

51: #pragma clang loop vectorize(enable)

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

54:

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

57:

58:       for (int idx = row + 1; idx < N; ++idx)

59:          P[row * N + idx] = 0.0f;

60:

61:       D[row] = sum;

Coverage (%)	Name	Source Location	Module
○100.00	main	attention_v2.cpp:283	attention-gcc-gnr-256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.69
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	10.80
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.11
Bottlenecks	micro-operation queue,
Function	softmax(float const, float, float*, int)
Source	attention_v2.cpp:43-43,attention_v2.cpp:46-47,attention_v2.cpp:50-52,attention_v2.cpp:58-61
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.83
CQA cycles if no scalar integer	2.67
CQA cycles if FP arith vectorized	9.83
CQA cycles if fully vectorized	0.91
Front-end cycles	9.83
P0 cycles	4.30
P1 cycles	4.10
P2 cycles	4.67
P3 cycles	4.67
P4 cycles	4.00
P5 cycles	4.20
P6 cycles	4.20
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	4.20
P11 cycles	4.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	56.00
Nb uops	59.00
Nb loads	14.00
Nb stores	7.00
Nb stack references	11.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.61
Bytes prefetched	0.00
Bytes loaded	88.00
Bytes stored	36.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	21.88
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	43.75
Vector-efficiency ratio all	12.30
Vector-efficiency ratio load	9.38
Vector-efficiency ratio store	8.04
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.23

Metric	Value
CQA speedup if no scalar integer	3.69
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	10.80
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.11
Bottlenecks	micro-operation queue,
Function	softmax(float const, float, float*, int)
Source	attention_v2.cpp:43-43,attention_v2.cpp:46-47,attention_v2.cpp:50-52,attention_v2.cpp:58-61
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.83
CQA cycles if no scalar integer	2.67
CQA cycles if FP arith vectorized	9.83
CQA cycles if fully vectorized	0.91
Front-end cycles	9.83
P0 cycles	4.30
P1 cycles	4.10
P2 cycles	4.67
P3 cycles	4.67
P4 cycles	4.00
P5 cycles	4.20
P6 cycles	4.20
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	4.20
P11 cycles	4.67
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	56.00
Nb uops	59.00
Nb loads	14.00
Nb stores	7.00
Nb stack references	11.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.61
Bytes prefetched	0.00
Bytes loaded	88.00
Bytes stored	36.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	21.88
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	43.75
Vector-efficiency ratio all	12.30
Vector-efficiency ratio load	9.38
Vector-efficiency ratio store	8.04
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.23

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	softmax(float const, float, float*, int)
Source file and lines	attention_v2.cpp:43-61
Module	attention-gcc-gnr-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:43-61.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:43,46-47,50-52,58-61.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.83 to 2.67 cycles (3.69x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

memset@plt: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:59

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:58
VZEROUPPER: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:47

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 88 bytes (22 single precision FP elements). The binary loop is storing 36 bytes (9 single precision FP elements).

General properties

nb instructions	56
nb uops	59
loop length	238
used x86 registers	11
used mmx registers	0
used xmm registers	4
used ymm registers	1
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.83 cycles
front end	9.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.30	4.10	4.67	4.67	4.00	4.20	4.20	4.00	4.00	4.00	4.20	4.67
cycles	4.30	4.10	4.67	4.67	4.00	4.20	4.20	4.00	4.00	4.00	4.20	4.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.83
Dispatch	4.67
Overall L1	9.83

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	60%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	85%

INT+FP

all	21%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	43%

Vector efficiency ratios

INT

all	10%
load	10%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	16%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

INT+FP

all	12%
load	9%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.83 cycles. At this rate:

4% of peak load performance is reached (8.95 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.66 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 9.83 to 4.67 cycles (2.11x speedup).

ASM code

In the binary file, the address of the loop is: 402b79

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV %R13D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x3,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
SAL $0x5,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
VBROADCASTSS 0x1739(%RIP),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
MOV %R13D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD %R12,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R12,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VEXTRACTF32X4 $0x1,%YMM0,%XMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMAXPS %XMM0,%XMM3,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVHLPS %XMM1,%XMM1,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	vect (12.5%)
VMAXPS %XMM1,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPS $0x55,%XMM2,%XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VMAXPS %XMM2,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
TEST $0x7,%CL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 402c78 <_Z7softmaxPKfPfS1_i+0x248>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R12,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVSS %XMM1,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R12,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA (%RAX,%RSI,4),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x3c(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x40(%RBP),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
LEA 0x1(%RAX),%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %ECX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 402c80 <_Z7softmaxPKfPfS1_i+0x250>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x78(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R13D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RSI,-0x48(%RBP)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x4(,%RAX,4),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x70(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %ECX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD -0x68(%RBP),%R12	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
CALL 401040 <memset@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x38(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV -0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %ECX,-0x3c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVSS -0x34(%RBP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD %R14,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
ADD %R14,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMPL $0x6,-0x3c(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV %R15,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSS %XMM2,-0x8(%RAX,%R13,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JG 402ab8 <_Z7softmaxPKfPfS1_i+0x88>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 402b79 <_Z7softmaxPKfPfS1_i+0x149>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	softmax(float const, float, float*, int)
Source file and lines	attention_v2.cpp:43-61
Module	attention-gcc-gnr-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:43-61.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:43,46-47,50-52,58-61.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.83 to 2.67 cycles (3.69x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

memset@plt: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:59

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

ADD: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:58
VZEROUPPER: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:47

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

General properties

nb instructions	56
nb uops	59
loop length	238
used x86 registers	11
used mmx registers	0
used xmm registers	4
used ymm registers	1
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.83 cycles
front end	9.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.30	4.10	4.67	4.67	4.00	4.20	4.20	4.00	4.00	4.00	4.20	4.67
cycles	4.30	4.10	4.67	4.67	4.00	4.20	4.20	4.00	4.00	4.00	4.20	4.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	9.83
Dispatch	4.67
Overall L1	9.83

Vectorization ratios

INT

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	60%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	85%

INT+FP

all	21%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	43%

Vector efficiency ratios

INT

all	10%
load	10%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	16%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

INT+FP

all	12%
load	9%
store	8%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.83 cycles. At this rate:

4% of peak load performance is reached (8.95 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.66 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 402b79

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV %R13D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SHR $0x3,%EDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
SAL $0x5,%RDX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
VBROADCASTSS 0x1739(%RIP),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	3	0.33	scal (6.3%)
MOV %R13D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD %R12,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %R12,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VEXTRACTF32X4 $0x1,%YMM0,%XMM3	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	vect (25.0%)
VMAXPS %XMM0,%XMM3,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VMOVHLPS %XMM1,%XMM1,%XMM2	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1	vect (12.5%)
VMAXPS %XMM1,%XMM2,%XMM2	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
VSHUFPS $0x55,%XMM2,%XMM2,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50	vect (25.0%)
VMAXPS %XMM2,%XMM1,%XMM1	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	vect (25.0%)
TEST $0x7,%CL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 402c78 <_Z7softmaxPKfPfS1_i+0x248>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R12,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVSS %XMM1,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x58(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x48(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R12,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
LEA (%RAX,%RSI,4),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x3c(%RBP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x40(%RBP),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
LEA 0x1(%RAX),%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
CMP %ECX,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 402c80 <_Z7softmaxPKfPfS1_i+0x250>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x78(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x50(%RBP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R13D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RSI,-0x48(%RBP)	2	0.20	0.20	0.33	0.33	0.50	0.20	0.20	0.50	0.50	0.50	0.20	0.33	1	0.50	scal (12.5%)
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x4(,%RAX,4),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x70(%RBP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %ECX,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD -0x68(%RBP),%R12	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (12.5%)
CALL 401040 <memset@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x38(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV -0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %ECX,-0x3c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVSS -0x34(%RBP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
ADD %R14,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
ADD %R14,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
CMPL $0x6,-0x3c(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV %R15,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSS %XMM2,-0x8(%RAX,%R13,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
JG 402ab8 <_Z7softmaxPKfPfS1_i+0x88>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
JMP 402b79 <_Z7softmaxPKfPfS1_i+0x149>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code