OV - attention-gcc-gnr-256 - Loop 21

	Loop Id: 21	Module: attention-gcc-gnr-256	Source: random.tcc:458-3374 [...]	Coverage: 0.55%

0x401a38 MOV	-0x13c0(%RBP,%RCX,8),%R8    [1]

0x401a40 LEA	0x1(%RCX),%RDI

0x401a44 MOV	%R8,%RCX

0x401a47 SHR	$0xb,%RCX

0x401a4b MOV	%ECX,%ECX

0x401a4d XOR	%R8,%RCX

0x401a50 MOV	%RCX,%R8

0x401a53 SAL	$0x7,%R8

0x401a57 AND	$-0x62d3a980,%R8D

0x401a5e XOR	%RCX,%R8

0x401a61 MOV	%R8,%RCX

0x401a64 SAL	$0xf,%RCX

0x401a68 AND	$-0x103a0000,%ECX

0x401a6e XOR	%R8,%RCX

0x401a71 MOV	%RCX,%R8

0x401a74 SHR	$0x12,%R8

0x401a78 XOR	%R8,%RCX

0x401a7b VCVTUSI2SS	%RCX,%XMM1,%XMM0

0x401a81 MOV	%RDI,-0x40(%RBP)    [1]

0x401a85 VMULSS	%XMM2,%XMM0,%XMM0

0x401a89 VCMPSS	$0x2,%XMM0,%XMM3,%XMM5

0x401a8e VBLENDVPS	%XMM5,%XMM4,%XMM0,%XMM0

0x401a94 VMOVSS	%XMM0,(%R12)    [2]

0x401a9a CMP	$0x26f,%RDI

0x401aa1 JA	401bfb

0x401aa7 LEA	0x1(%RDI),%R8

0x401aab MOV	-0x13c0(%RBP,%RDI,8),%RDI    [1]

0x401ab3 MOV	%R8,-0x40(%RBP)    [1]

0x401ab7 MOV	%RDI,%RCX

0x401aba SHR	$0xb,%RCX

0x401abe MOV	%ECX,%ECX

0x401ac0 XOR	%RDI,%RCX

0x401ac3 MOV	%RCX,%RDI

0x401ac6 SAL	$0x7,%RDI

0x401aca AND	$-0x62d3a980,%EDI

0x401ad0 XOR	%RCX,%RDI

0x401ad3 MOV	%RDI,%RCX

0x401ad6 SAL	$0xf,%RCX

0x401ada AND	$-0x103a0000,%ECX

0x401ae0 XOR	%RDI,%RCX

0x401ae3 MOV	%RCX,%RDI

0x401ae6 SHR	$0x12,%RDI

0x401aea XOR	%RDI,%RCX

0x401aed VCVTUSI2SS	%RCX,%XMM1,%XMM0

0x401af3 VMULSS	%XMM2,%XMM0,%XMM0

0x401af7 VCMPSS	$0x2,%XMM0,%XMM3,%XMM5

0x401afc VBLENDVPS	%XMM5,%XMM4,%XMM0,%XMM0

0x401b02 VMOVSS	%XMM0,(%R13)    [3]

0x401b08 CMP	$0x26f,%R8

0x401b0f JA	401bca

0x401b15 LEA	0x1(%R8),%RCX

0x401b19 MOV	-0x13c0(%RBP,%R8,8),%R8    [1]

0x401b21 ADD	$0x4,%R14

0x401b25 MOV	%R8,%RDI

0x401b28 SHR	$0xb,%RDI

0x401b2c MOV	%EDI,%EDI

0x401b2e XOR	%R8,%RDI

0x401b31 MOV	%RDI,%R8

0x401b34 SAL	$0x7,%R8

0x401b38 AND	$-0x62d3a980,%R8D

0x401b3f XOR	%RDI,%R8

0x401b42 MOV	%R8,%RDI

0x401b45 SAL	$0xf,%RDI

0x401b49 AND	$-0x103a0000,%EDI

0x401b4f XOR	%R8,%RDI

0x401b52 MOV	%RDI,%R8

0x401b55 SHR	$0x12,%R8

0x401b59 XOR	%R8,%RDI

0x401b5c VCVTUSI2SS	%RDI,%XMM1,%XMM0

0x401b62 MOV	%RCX,-0x40(%RBP)    [1]

0x401b66 ADD	$0x4,%R13

0x401b6a ADD	$0x4,%R12

0x401b6e VMULSS	%XMM2,%XMM0,%XMM0

0x401b72 VCMPSS	$0x2,%XMM0,%XMM3,%XMM5

0x401b77 VBLENDVPS	%XMM5,%XMM4,%XMM0,%XMM0

0x401b7d VMOVSS	%XMM0,-0x4(%R14)    [4]

0x401b83 CMP	%R14,%RBX

0x401b86 JE	401c2c

0x401b8c CMP	$0x26f,%RCX

0x401b93 JBE	401a38

0x401b99 LEA	-0x13c0(%RBP),%RDI

0x401ba0 CALL	403140 <_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv>

0x401ba5 MOV	-0x40(%RBP),%RCX    [1]

0x401ba9 VMOVSS	0x2657(%RIP),%XMM4    [5]

0x401bb1 VMOVSS	0x2657(%RIP),%XMM3    [5]

0x401bb9 VMOVSS	0x264b(%RIP),%XMM2    [5]

0x401bc1 VXORPS	%XMM1,%XMM1,%XMM1

0x401bc5 JMP	401a38

0x401bca LEA	-0x13c0(%RBP),%RDI

0x401bd1 CALL	403140 <_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv>

0x401bd6 MOV	-0x40(%RBP),%R8    [1]

0x401bda VMOVSS	0x2626(%RIP),%XMM4    [5]

0x401be2 VMOVSS	0x2626(%RIP),%XMM3    [5]

0x401bea VMOVSS	0x261a(%RIP),%XMM2    [5]

0x401bf2 VXORPS	%XMM1,%XMM1,%XMM1

0x401bf6 JMP	401b15

0x401bfb LEA	-0x13c0(%RBP),%RDI

0x401c02 CALL	403140 <_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv>

0x401c07 MOV	-0x40(%RBP),%RDI    [1]

0x401c0b VMOVSS	0x25f5(%RIP),%XMM4    [5]

0x401c13 VMOVSS	0x25f5(%RIP),%XMM3    [5]

0x401c1b VMOVSS	0x25e9(%RIP),%XMM2    [5]

0x401c23 VXORPS	%XMM1,%XMM1,%XMM1

0x401c27 JMP	401aa7

/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc: 458 - 3374

--------------------------------------------------------------------------------

458:       if (_M_p >= state_size)

459: 	_M_gen_rand();

460:

461:       // Calculate o(x(i)).

462:       result_type __z = _M_x[_M_p++];

463:       __z ^= (__z >> __u) & __d;

464:       __z ^= (__z << __s) & __b;

465:       __z ^= (__z << __t) & __c;

466:       __z ^= (__z >> __l);

[...]

3367: 	  __sum += _RealType(__urng() - __urng.min()) * __tmp;

3368: 	  __tmp *= __r;

3369: 	}

3370:       __ret = __sum / __tmp;

3371:       if (__builtin_expect(__ret >= _RealType(1), 0))

3372: 	{

3373: #if _GLIBCXX_USE_C99_MATH_FUNCS

3374: 	  __ret = std::nextafter(_RealType(1), _RealType(0));

/home/eoseret/llm-attention/attention_v2.cpp: 164 - 167

--------------------------------------------------------------------------------

164:       for (size_t i = 0; i < elemsW; ++i) {

165:          h_WQ[i] = dist(rng);

166:          h_WK[i] = dist(rng);

167:          h_WV[i] = dist(rng);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.98
CQA speedup if FP arith vectorized	2.77
CQA speedup if fully vectorized	13.64
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.59
Bottlenecks	micro-operation queue,
Function	main
Source	random.tcc:458-466,random.tcc:3367-3374,attention_v2.cpp:164-167
Source loop unroll info	unrolled by 3
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	3
CQA cycles	19.83
CQA cycles if no scalar integer	10.00
CQA cycles if FP arith vectorized	7.16
CQA cycles if fully vectorized	1.45
Front-end cycles	19.83
P0 cycles	12.47
P1 cycles	12.30
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	4.50
P5 cycles	12.33
P6 cycles	12.50
P7 cycles	4.50
P8 cycles	4.50
P9 cycles	4.50
P10 cycles	12.40
P11 cycles	5.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	104.00
Nb uops	119.00
Nb loads	15.00
Nb stores	6.00
Nb stack references	2.00
FLOP/cycle	0.15
Nb FLOP add-sub	0.00
Nb FLOP mul	3.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.05
Bytes prefetched	0.00
Bytes loaded	84.00
Bytes stored	36.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	18.18
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	40.00
Vector-efficiency ratio all	11.36
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	9.38
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.25

Metric	Value
CQA speedup if no scalar integer	1.98
CQA speedup if FP arith vectorized	2.77
CQA speedup if fully vectorized	13.64
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.59
Bottlenecks	micro-operation queue,
Function	main
Source	random.tcc:458-466,random.tcc:3367-3374,attention_v2.cpp:164-167
Source loop unroll info	unrolled by 3
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	3
CQA cycles	19.83
CQA cycles if no scalar integer	10.00
CQA cycles if FP arith vectorized	7.16
CQA cycles if fully vectorized	1.45
Front-end cycles	19.83
P0 cycles	12.47
P1 cycles	12.30
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	4.50
P5 cycles	12.33
P6 cycles	12.50
P7 cycles	4.50
P8 cycles	4.50
P9 cycles	4.50
P10 cycles	12.40
P11 cycles	5.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	104.00
Nb uops	119.00
Nb loads	15.00
Nb stores	6.00
Nb stack references	2.00
FLOP/cycle	0.15
Nb FLOP add-sub	0.00
Nb FLOP mul	3.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.05
Bytes prefetched	0.00
Bytes loaded	84.00
Bytes stored	36.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	18.18
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	40.00
Vector-efficiency ratio all	11.36
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	9.38
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	random.tcc:458-3374
Module	attention-gcc-gnr-256

The loop is defined in:

/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:458-466,3367-3374
/home/eoseret/llm-attention/attention_v2.cpp:164-167

It is main loop of related source loop which is unrolled by 3 (including vectorization).
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.83 to 10.00 cycles (1.98x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 19.83 to 1.45 cycles (13.64x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

std::mersenne_twister_engine
::_M_gen_rand(): 3 occurrences►
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:459
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:459
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:459

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VBLENDVPS: 3 occurrences►
VCVTUSI2SS: 3 occurrences►
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:3367
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:3367
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:3367

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 3 occurrences►
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:3367
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:3367
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:3367

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

3: multiply

The binary loop is loading 84 bytes (21 single precision FP elements). The binary loop is storing 36 bytes (9 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	104
nb uops	119
loop length	500
used x86 registers	8
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.83 cycles
front end	19.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	12.47	12.30	5.00	5.00	4.50	12.33	12.50	4.50	4.50	4.50	12.40	5.00
cycles	12.47	12.30	5.00	5.00	4.50	12.33	12.50	4.50	4.50	4.50	12.40	5.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.83
Dispatch	12.50
Overall L1	19.83

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	25%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	66%

INT+FP

all	18%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	10%
load	6%
store	6%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	11%
load	6%
store	9%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 19.83 cycles. At this rate:

2% of peak load performance is reached (4.24 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.82 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 19.83 to 12.50 cycles (1.59x speedup).

ASM code

In the binary file, the address of the loop is: 401b8c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x13c0(%RBP,%RCX,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%RCX),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0xb,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %R8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x7,%R8	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $-0x62d3a980,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0xf,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $-0x103a0000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %R8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x12,%R8	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
XOR %R8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VCVTUSI2SS %RCX,%XMM1,%XMM0	3	0.50	0.50	0	0	0	2	0	0	0	0	0	0	8	2	scal (12.5%)
MOV %RDI,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSS %XMM2,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VCMPSS $0x2,%XMM0,%XMM3,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VBLENDVPS %XMM5,%XMM4,%XMM0,%XMM0	3	1	1	0	0	0	1	0	0	0	0	0	0	2-3	1	vect (25.0%)
VMOVSS %XMM0,(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP $0x26f,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 401bfb <main+0x8fb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x1(%RDI),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x13c0(%RBP,%RDI,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0xb,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %RDI,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x7,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $-0x62d3a980,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0xf,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $-0x103a0000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RDI,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x12,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
XOR %RDI,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VCVTUSI2SS %RCX,%XMM1,%XMM0	3	0.50	0.50	0	0	0	2	0	0	0	0	0	0	8	2	scal (12.5%)
VMULSS %XMM2,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VCMPSS $0x2,%XMM0,%XMM3,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VBLENDVPS %XMM5,%XMM4,%XMM0,%XMM0	3	1	1	0	0	0	1	0	0	0	0	0	0	2-3	1	vect (25.0%)
VMOVSS %XMM0,(%R13)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP $0x26f,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 401bca <main+0x8ca>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x1(%R8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x13c0(%RBP,%R8,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x4,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0xb,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %R8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RDI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x7,%R8	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $-0x62d3a980,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RDI,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0xf,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $-0x103a0000,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %R8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RDI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x12,%R8	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
XOR %R8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VCVTUSI2SS %RDI,%XMM1,%XMM0	3	0.50	0.50	0	0	0	2	0	0	0	0	0	0	8	2	scal (12.5%)
MOV %RCX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD $0x4,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x4,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULSS %XMM2,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VCMPSS $0x2,%XMM0,%XMM3,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VBLENDVPS %XMM5,%XMM4,%XMM0,%XMM0	3	1	1	0	0	0	1	0	0	0	0	0	0	2-3	1	vect (25.0%)
VMOVSS %XMM0,-0x4(%R14)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R14,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 401c2c <main+0x92c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x26f,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JBE 401a38 <main+0x738>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x13c0(%RBP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 403140 <_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x40(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS 0x2657(%RIP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS 0x2657(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS 0x264b(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 401a38 <main+0x738>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
LEA -0x13c0(%RBP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 403140 <_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x40(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS 0x2626(%RIP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS 0x2626(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS 0x261a(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 401b15 <main+0x815>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
LEA -0x13c0(%RBP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 403140 <_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x40(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS 0x25f5(%RIP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS 0x25f5(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS 0x25e9(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 401aa7 <main+0x7a7>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Function	main
Source file and lines	random.tcc:458-3374
Module	attention-gcc-gnr-256

The loop is defined in:

/cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:458-466,3367-3374
/home/eoseret/llm-attention/attention_v2.cpp:164-167

It is main loop of related source loop which is unrolled by 3 (including vectorization).
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

std::mersenne_twister_engine
::_M_gen_rand(): 3 occurrences►
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:459
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:459
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:459

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VBLENDVPS: 3 occurrences►
VCVTUSI2SS: 3 occurrences►
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:3367
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:3367
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:3367

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTUSI2SS (INT32/64 to FP32, scalar): 3 occurrences►
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:3367
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:3367
- /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/random.tcc:3367

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

6 SSE or AVX instructions are processing arithmetic or math operations on single precision FP elements in scalar mode (one at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

3: multiply

The binary loop is loading 84 bytes (21 single precision FP elements). The binary loop is storing 36 bytes (9 single precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	104
nb uops	119
loop length	500
used x86 registers	8
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.83 cycles
front end	19.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	12.47	12.30	5.00	5.00	4.50	12.33	12.50	4.50	4.50	4.50	12.40	5.00
cycles	12.47	12.30	5.00	5.00	4.50	12.33	12.50	4.50	4.50	4.50	12.40	5.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.83
Dispatch	12.50
Overall L1	19.83

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	25%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	66%

INT+FP

all	18%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	10%
load	6%
store	6%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	11%
load	6%
store	9%
mul	6%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 19.83 cycles. At this rate:

2% of peak load performance is reached (4.24 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.82 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 401b8c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
MOV -0x13c0(%RBP,%RCX,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%RCX),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0xb,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %R8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x7,%R8	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $-0x62d3a980,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R8,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0xf,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $-0x103a0000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %R8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RCX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x12,%R8	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
XOR %R8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VCVTUSI2SS %RCX,%XMM1,%XMM0	3	0.50	0.50	0	0	0	2	0	0	0	0	0	0	8	2	scal (12.5%)
MOV %RDI,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMULSS %XMM2,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VCMPSS $0x2,%XMM0,%XMM3,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VBLENDVPS %XMM5,%XMM4,%XMM0,%XMM0	3	1	1	0	0	0	1	0	0	0	0	0	0	2-3	1	vect (25.0%)
VMOVSS %XMM0,(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP $0x26f,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 401bfb <main+0x8fb>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x1(%RDI),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x13c0(%RBP,%RDI,8),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0xb,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %ECX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %RDI,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x7,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $-0x62d3a980,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RCX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0xf,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $-0x103a0000,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RDI,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RCX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x12,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
XOR %RDI,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VCVTUSI2SS %RCX,%XMM1,%XMM0	3	0.50	0.50	0	0	0	2	0	0	0	0	0	0	8	2	scal (12.5%)
VMULSS %XMM2,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VCMPSS $0x2,%XMM0,%XMM3,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VBLENDVPS %XMM5,%XMM4,%XMM0,%XMM0	3	1	1	0	0	0	1	0	0	0	0	0	0	2-3	1	vect (25.0%)
VMOVSS %XMM0,(%R13)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP $0x26f,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JA 401bca <main+0x8ca>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x1(%R8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x13c0(%RBP,%R8,8),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x4,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0xb,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %EDI,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %R8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RDI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x7,%R8	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $-0x62d3a980,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %RDI,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0xf,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
AND $-0x103a0000,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
XOR %R8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %RDI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SHR $0x12,%R8	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
XOR %R8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VCVTUSI2SS %RDI,%XMM1,%XMM0	3	0.50	0.50	0	0	0	2	0	0	0	0	0	0	8	2	scal (12.5%)
MOV %RCX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD $0x4,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x4,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMULSS %XMM2,%XMM0,%XMM0	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VCMPSS $0x2,%XMM0,%XMM3,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50	scal (6.3%)
VBLENDVPS %XMM5,%XMM4,%XMM0,%XMM0	3	1	1	0	0	0	1	0	0	0	0	0	0	2-3	1	vect (25.0%)
VMOVSS %XMM0,-0x4(%R14)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R14,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
JE 401c2c <main+0x92c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x26f,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JBE 401a38 <main+0x738>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x13c0(%RBP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 403140 <_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x40(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS 0x2657(%RIP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS 0x2657(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS 0x264b(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 401a38 <main+0x738>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
LEA -0x13c0(%RBP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 403140 <_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x40(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS 0x2626(%RIP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS 0x2626(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS 0x261a(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 401b15 <main+0x815>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
LEA -0x13c0(%RBP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 403140 <_ZNSt23mersenne_twister_engineImLm32ELm624ELm397ELm31ELm2567483615ELm11ELm4294967295ELm7ELm2636928640ELm15ELm4022730752ELm18ELm1812433253EE11_M_gen_randEv>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x40(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS 0x25f5(%RIP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS 0x25f5(%RIP),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS 0x25e9(%RIP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VXORPS %XMM1,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
JMP 401aa7 <main+0x7a7>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code