OV - attention-gcc-gnr-256 - Loop 17

	Loop Id: 17	Module: attention-gcc-gnr-256	Source: attention_v2.cpp:26-33	Coverage: 1.21%

0x4021b0 MOV	%R11D,%ESI

0x4021b3 VXORPD	%XMM3,%XMM3,%XMM3

0x4021b7 XOR	%EAX,%EAX

0x4021b9 NOPL	(%RAX)

  (16) 0x4021c0 LEA	(%RAX,%RCX,1),%EDX

  (16) 0x4021c3 VCVTSS2SD	(%R14,%RDX,4),%XMM1,%XMM0

  (16) 0x4021c9 MOV	%ESI,%EDX

  (16) 0x4021cb VCVTSS2SD	(%R13,%RDX,4),%XMM1,%XMM2

  (16) 0x4021d2 VMULSD	%XMM2,%XMM0,%XMM0

  (16) 0x4021d6 INC	%EAX

  (16) 0x4021d8 ADD	%R8D,%ESI

  (16) 0x4021db VADDSD	%XMM0,%XMM3,%XMM3

  (16) 0x4021df CMP	%R9D,%EAX

  (16) 0x4021e2 JB	4021c0

0x4021e4 LEA	(%R11,%RDI,1),%EAX

0x4021e8 INC	%R11D

0x4021eb VCVTSD2SS	%XMM3,%XMM3,%XMM3

0x4021ef VMOVSS	%XMM3,(%RBX,%RAX,4)

0x4021f4 CMP	%R8D,%R11D

0x4021f7 JB	4021b0

/home/eoseret/llm-attention/attention_v2.cpp: 26 - 33

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.67
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.52
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.67
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.67
CQA cycles if fully vectorized	0.13
Front-end cycles	1.67
P0 cycles	1.00
P1 cycles	1.10
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	0.50
P5 cycles	1.00
P6 cycles	0.90
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	1.00
P11 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	10.00
Nb uops	10.00
Nb loads	0.00
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.40
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	25.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	33.33
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.58

Metric	Value
CQA speedup if no scalar integer	1.67
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.52
Bottlenecks	micro-operation queue,
Function	main
Source	attention_v2.cpp:26-30,attention_v2.cpp:33-33
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.67
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	1.67
CQA cycles if fully vectorized	0.13
Front-end cycles	1.67
P0 cycles	1.00
P1 cycles	1.10
P2 cycles	0.00
P3 cycles	0.00
P4 cycles	0.50
P5 cycles	1.00
P6 cycles	0.90
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.50
P10 cycles	1.00
P11 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	10.00
Nb uops	10.00
Nb loads	0.00
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.40
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	4.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	25.00
Vectorization ratio load	NA
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	33.33
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	6.25
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.58

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-gcc-gnr-256

The loop is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-33.

Analyzed code is defined in /home/eoseret/llm-attention/attention_v2.cpp:26-30,33.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 1.67 to 1.00 cycles (1.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 1.67 to 0.12 cycles (13.33x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements. Use double instead of single precision only when/where needed by numerical stability and avoid mixing precision. In C/C++, FP constants are double precision by default and must be suffixed by 'f' to make them single precision.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 4 bytes.

General properties

nb instructions	10
nb uops	10
loop length	37
used x86 registers	6
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	1.67 cycles
front end	1.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.00	1.10	0.00	0.00	0.50	1.00	0.90	0.50	0.50	0.50	1.00	0.00
cycles	1.00	1.10	0.00	0.00	0.50	1.00	0.90	0.50	0.50	0.50	1.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.67
Dispatch	1.10
Data deps.	1.00
Overall L1	1.67

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.67 cycles. At this rate:

1% of peak store performance is reached (2.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 1.67 to 1.10 cycles (1.52x speedup).

ASM code

In the binary file, the address of the loop is: 4021b0

Instruction	Nb FU	P0	P1	P4	P5	P6	P7	P8	P9	P10	Latency	Recip. throughput	Vectorization
MOV %R11D,%ESI	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R11,%RDI,1),%EAX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	N/A
INC %R11D	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1	0.20	N/A
VCVTSD2SS %XMM3,%XMM3,%XMM3	2	0.50	0.50	0	1	0	0	0	0	0	5	1	scal (12.5%)
VMOVSS %XMM3,(%RBX,%RAX,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
CMP %R8D,%R11D	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1	0.20	N/A
JB 4021b0 <main+0xeb0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A

Function	main
Source file and lines	attention_v2.cpp:26-33
Module	attention-gcc-gnr-256

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 1.67 to 1.00 cycles (1.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTSD2SS: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTSD2SS (FP64 to FP32, scalar): 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:33

Workaround

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 4 bytes.

General properties

nb instructions	10
nb uops	10
loop length	37
used x86 registers	6
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	1.67 cycles
front end	1.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.00	1.10	0.00	0.00	0.50	1.00	0.90	0.50	0.50	0.50	1.00	0.00
cycles	1.00	1.10	0.00	0.00	0.50	1.00	0.90	0.50	0.50	0.50	1.00	0.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.67
Dispatch	1.10
Data deps.	1.00
Overall L1	1.67

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	33%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Vector efficiency ratios

INT

all	6%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

INT+FP

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.67 cycles. At this rate:

1% of peak store performance is reached (2.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4021b0

Instruction	Nb FU	P0	P1	P4	P5	P6	P7	P8	P9	P10	Latency	Recip. throughput	Vectorization
MOV %R11D,%ESI	1	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R11,%RDI,1),%EAX	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1-2	0.20	N/A
INC %R11D	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1	0.20	N/A
VCVTSD2SS %XMM3,%XMM3,%XMM3	2	0.50	0.50	0	1	0	0	0	0	0	5	1	scal (12.5%)
VMOVSS %XMM3,(%RBX,%RAX,4)	1	0	0	0.50	0	0	0.50	0.50	0.50	0	1	0.50	scal (6.3%)
CMP %R8D,%R11D	1	0.20	0.20	0	0.20	0.20	0	0	0	0.20	1	0.20	N/A
JB 4021b0 <main+0xeb0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Complex instructions

Details

Slow data structures access

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code