OV - attention-gcc-gnr-256 - Function softmax(float const*, float*, float*, int)

	Function: softmax(float const, float, float*, int)	Module: attention-gcc-gnr-256	Source: attention_v2.cpp:42-63	Coverage (incl. loops): 6.93% \| (excl. loops): 0.00%

/home/eoseret/llm-attention/attention_v2.cpp: 42 - 63

--------------------------------------------------------------------------------

42: {

43:    for (int row = 0; row < N; ++row) {

44:       const float *S_row = &S[row * N];

45:

46:       float max_val = -FLT_MAX;

47:       for (int idx = 0; idx <= row; ++idx) // vectorised

48:          if (S_row[idx] > max_val) max_val = S_row[idx];

49:

50:       float sum = 0.0f;

51: #pragma clang loop vectorize(enable)

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

54:

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

57:

58:       for (int idx = row + 1; idx < N; ++idx)

59:          P[row * N + idx] = 0.0f;

60:

61:       D[row] = sum;

62:    }

63: }

0x402a30 TEST	%ECX,%ECX

0x402a32 JLE	402ca8

0x402a38 LEA	0x8(%RSP),%R10

0x402a3d AND	$-0x20,%RSP

0x402a41 PUSHQ	-0x8(%R10)

0x402a45 PUSH	%RBP

0x402a46 MOV	%RSP,%RBP

0x402a49 PUSH	%R15

0x402a4b PUSH	%R14

0x402a4d PUSH	%R13

0x402a4f MOV	$0x1,%R13D

0x402a55 PUSH	%R12

0x402a57 MOV	%RDI,%R12

0x402a5a PUSH	%R10

0x402a5c PUSH	%RBX

0x402a5d LEA	0x4(%RDI),%RBX

0x402a61 SUB	$0x60,%RSP

0x402a65 MOV	%RSI,-0x60(%RBP)

0x402a69 MOVL	$0,-0x3c(%RBP)

0x402a70 MOVSXD	%ECX,%RSI

0x402a73 LEA	0x4(,%RSI,4),%RAX

0x402a7b MOV	%RAX,-0x70(%RBP)

0x402a7f LEA	0x4(%RDX),%RAX

0x402a83 MOV	%RAX,-0x50(%RBP)

0x402a87 CMPL	$0x6,-0x3c(%RBP)

0x402a8b LEA	(,%RSI,4),%RAX

0x402a93 MOV	%ECX,-0x40(%RBP)

0x402a96 MOV	%RAX,-0x68(%RBP)

0x402a9a MOVQ	$0,-0x48(%RBP)

0x402aa2 MOV	%RSI,-0x78(%RBP)

0x402aa6 MOV	%RDI,-0x80(%RBP)

0x402aaa MOV	%RDX,-0x58(%RBP)

0x402aae JLE	402c5b

0x402ab4 NOPL	(%RAX)

    (30) 0x402ab8 MOV	%R13D,%EDX

    (30) 0x402abb SHR	$0x3,%EDX

    (30) 0x402abe SAL	$0x5,%RDX

    (30) 0x402ac2 VBROADCASTSS	0x1739(%RIP),%YMM0

    (30) 0x402acb MOV	%R13D,%ECX

    (30) 0x402ace ADD	%R12,%RDX

    (30) 0x402ad1 MOV	%R12,%RAX

    (30) 0x402ad4 NOPW	%CS:(%RAX,%RAX,1)

    (30) 0x402adf NOP

      (29) 0x402ae0 VMAXPS	(%RAX),%YMM0,%YMM0

      (29) 0x402ae4 ADD	$0x20,%RAX

      (29) 0x402ae8 CMP	%RAX,%RDX

      (29) 0x402aeb JNE	402ae0

    (30) 0x402aed VEXTRACTF32X4	$0x1,%YMM0,%XMM3

    (30) 0x402af4 VMAXPS	%XMM0,%XMM3,%XMM1

    (30) 0x402af8 VMOVHLPS	%XMM1,%XMM1,%XMM2

    (30) 0x402afc VMAXPS	%XMM1,%XMM2,%XMM2

    (30) 0x402b00 VSHUFPS	$0x55,%XMM2,%XMM2,%XMM1

    (30) 0x402b05 VMAXPS	%XMM2,%XMM1,%XMM1

    (30) 0x402b09 TEST	$0x7,%CL

    (30) 0x402b0c JE	402c78

  (31) 0x402b12 MOV	%ECX,%EAX

  (31) 0x402b14 AND	$-0x8,%EAX

  (31) 0x402b17 VMAXPS	%XMM3,%XMM0,%XMM0

  (31) 0x402b1b MOV	%EAX,%ECX

  (31) 0x402b1d VZEROUPPER

  (31) 0x402b20 MOV	-0x3c(%RBP),%EDX

  (31) 0x402b23 SUB	%EAX,%EDX

  (31) 0x402b25 CMP	$0x2,%EDX

  (31) 0x402b28 JBE	402b54

  (31) 0x402b2a MOV	-0x80(%RBP),%RDI

  (31) 0x402b2e ADD	-0x48(%RBP),%RAX

  (31) 0x402b32 VMAXPS	(%RDI,%RAX,4),%XMM0,%XMM0

  (31) 0x402b37 INC	%EDX

  (31) 0x402b39 VMOVHLPS	%XMM0,%XMM0,%XMM1

  (31) 0x402b3d VMAXPS	%XMM0,%XMM1,%XMM0

  (31) 0x402b41 VSHUFPS	$0x55,%XMM0,%XMM0,%XMM1

  (31) 0x402b46 VMAXPS	%XMM0,%XMM1,%XMM1

  (31) 0x402b4a TEST	$0x3,%DL

  (31) 0x402b4d JE	402b79

  (31) 0x402b4f AND	$-0x4,%EDX

  (31) 0x402b52 ADD	%EDX,%ECX

  (31) 0x402b54 MOV	-0x3c(%RBP),%ESI

  (31) 0x402b57 MOVSXD	%ECX,%RAX

  (31) 0x402b5a VMAXSS	(%R12,%RAX,4),%XMM1,%XMM1

  (31) 0x402b60 CMP	%ECX,%ESI

  (31) 0x402b62 JLE	402b79

  (31) 0x402b64 ADD	$0x2,%ECX

  (31) 0x402b67 VMAXSS	0x4(%R12,%RAX,4),%XMM1,%XMM1

  (31) 0x402b6e CMP	%ECX,%ESI

  (31) 0x402b70 JL	402b79

  (31) 0x402b72 VMAXSS	0x8(%R12,%RAX,4),%XMM1,%XMM1

    (30) 0x402b79 MOVL	$0,-0x34(%RBP)

    (30) 0x402b80 MOV	%R12,%R14

    (30) 0x402b83 VMOVSS	%XMM1,-0x38(%RBP)

    (30) 0x402b88 NOPL	(%RAX,%RAX,1)

      (27) 0x402b90 VMOVSS	(%R14),%XMM0

      (27) 0x402b95 ADD	$0x4,%R14

      (27) 0x402b99 VSUBSS	-0x38(%RBP),%XMM0,%XMM0

      (27) 0x402b9e CALL	401110 <expf@plt>

      (27) 0x402ba3 VADDSS	-0x34(%RBP),%XMM0,%XMM5

      (27) 0x402ba8 VMOVSS	%XMM5,-0x34(%RBP)

      (27) 0x402bad CMP	%R14,%RBX

      (27) 0x402bb0 JNE	402b90

    (30) 0x402bb2 MOV	-0x58(%RBP),%RAX

    (30) 0x402bb6 MOV	-0x48(%RBP),%RSI

    (30) 0x402bba MOV	%R12,%R15

    (30) 0x402bbd LEA	(%RAX,%RSI,4),%R14

    (30) 0x402bc1 NOPL	(%RAX)

      (28) 0x402bc8 VMOVSS	(%R15),%XMM0

      (28) 0x402bcd ADD	$0x4,%R15

      (28) 0x402bd1 VSUBSS	-0x38(%RBP),%XMM0,%XMM0

      (28) 0x402bd6 ADD	$0x4,%R14

      (28) 0x402bda CALL	401110 <expf@plt>

      (28) 0x402bdf VDIVSS	-0x34(%RBP),%XMM0,%XMM0

      (28) 0x402be4 VMOVSS	%XMM0,-0x4(%R14)

      (28) 0x402bea CMP	%R15,%RBX

      (28) 0x402bed JNE	402bc8

    (30) 0x402bef MOV	-0x3c(%RBP),%EAX

    (30) 0x402bf2 MOV	-0x40(%RBP),%EDI

    (30) 0x402bf5 LEA	0x1(%RAX),%ECX

    (30) 0x402bf8 CMP	%ECX,%EDI

    (30) 0x402bfa JE	402c80

    (30) 0x402c00 MOV	-0x78(%RBP),%RSI

    (30) 0x402c04 MOV	-0x50(%RBP),%R15

    (30) 0x402c08 INC	%R13

    (30) 0x402c0b MOV	%EDI,%EAX

    (30) 0x402c0d SUB	%R13D,%EAX

    (30) 0x402c10 ADD	%RSI,-0x48(%RBP)

    (30) 0x402c14 MOV	%R15,%RDI

    (30) 0x402c17 XOR	%ESI,%ESI

    (30) 0x402c19 LEA	0x4(,%RAX,4),%RDX

    (30) 0x402c21 MOV	-0x70(%RBP),%R14

    (30) 0x402c25 MOV	%ECX,-0x38(%RBP)

    (30) 0x402c28 ADD	-0x68(%RBP),%R12

    (30) 0x402c2c CALL	401040 <memset@plt>

    (30) 0x402c31 MOV	-0x38(%RBP),%ECX

    (30) 0x402c34 MOV	-0x60(%RBP),%RAX

    (30) 0x402c38 MOV	%ECX,-0x3c(%RBP)

    (30) 0x402c3b VMOVSS	-0x34(%RBP),%XMM2

    (30) 0x402c40 ADD	%R14,%R15

    (30) 0x402c43 ADD	%R14,%RBX

    (30) 0x402c46 CMPL	$0x6,-0x3c(%RBP)

    (30) 0x402c4a MOV	%R15,-0x50(%RBP)

    (30) 0x402c4e VMOVSS	%XMM2,-0x8(%RAX,%R13,4)

    (30) 0x402c55 JG	402ab8

(32) 0x402c5b VBROADCASTSS	0x15a0(%RIP),%XMM0

(32) 0x402c64 VMOVSS	0x1598(%RIP),%XMM1

(32) 0x402c6c XOR	%EAX,%EAX

(32) 0x402c6e XOR	%ECX,%ECX

(32) 0x402c70 JMP	402b20

0x402c75 NOPL	(%RAX)

    (30) 0x402c78 VZEROUPPER

    (30) 0x402c7b JMP	402b79

0x402c80 MOV	-0x3c(%RBP),%R14D

0x402c84 MOV	-0x60(%RBP),%RAX

0x402c88 VMOVSS	-0x34(%RBP),%XMM2

0x402c8d VMOVSS	%XMM2,(%RAX,%R14,4)

0x402c93 ADD	$0x60,%RSP

0x402c97 POP	%RBX

0x402c98 POP	%R10

0x402c9a POP	%R12

0x402c9c POP	%R13

0x402c9e POP	%R14

0x402ca0 POP	%R15

0x402ca2 POP	%RBP

0x402ca3 LEA	-0x8(%R10),%RSP

0x402ca7 RET

0x402ca8 RET

0x402ca9 NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
○100.00	main	attention_v2.cpp:283	attention-gcc-gnr-256

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run run_0

Source file and lines	attention_v2.cpp:42-63
Module	attention-gcc-gnr-256

The function is defined in /home/eoseret/llm-attention/attention_v2.cpp:42-63.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.50 to 1.50 cycles (6.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 9.50 to 0.81 cycles (11.69x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by writing data to caches/RAM (the store unit is a bottleneck).

Workaround

Write less array elements

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

PUSH: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:42

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	51
nb uops	52
loop length	187
used x86 registers	13
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.67 cycles
front end	8.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.00	1.73	4.67	4.67	9.50	1.73	2.00	9.50	9.50	9.50	1.53	4.67
cycles	2.00	1.73	4.67	4.67	9.50	1.73	2.00	9.50	9.50	9.50	1.53	4.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.67
Dispatch	9.50
Overall L1	9.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	9%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	9%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.50 cycles. At this rate:

1% of peak load performance is reached (2.95 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 402a30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
TEST %ECX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 402ca8 <_Z7softmaxPKfPfS1_i+0x278>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x8(%RSP),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
PUSHQ -0x8(%R10)	2	0	0	0.33	0.33	0.50	0	0	0.50	0.50	0.50	0	0.33	5-12	0.62	N/A
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV $0x1,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
PUSH %R10	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
LEA 0x4(%RDI),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x60,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVL $0,-0x3c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVSXD %ECX,%RSI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA 0x4(,%RSI,4),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x4(%RDX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMPL $0x6,-0x3c(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
LEA (,%RSI,4),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %ECX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RSI,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JLE 402c5b <_Z7softmaxPKfPfS1_i+0x22b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x3c(%RBP),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS -0x34(%RBP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS %XMM2,(%RAX,%R14,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x60,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
LEA -0x8(%R10),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run run_0

Source file and lines	attention_v2.cpp:42-63
Module	attention-gcc-gnr-256

The function is defined in /home/eoseret/llm-attention/attention_v2.cpp:42-63.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.50 to 1.50 cycles (6.33x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by writing data to caches/RAM (the store unit is a bottleneck).

Workaround

Write less array elements

No data for this section

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

PUSH: 1 occurrences►
- /home/eoseret/llm-attention/attention_v2.cpp:42

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 28 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	51
nb uops	52
loop length	187
used x86 registers	13
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	12

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.67 cycles
front end	8.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.00	1.73	4.67	4.67	9.50	1.73	2.00	9.50	9.50	9.50	1.53	4.67
cycles	2.00	1.73	4.67	4.67	9.50	1.73	2.00	9.50	9.50	9.50	1.53	4.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.67
Dispatch	9.50
Overall L1	9.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	9%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	6%
load	6%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	9%
load	6%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 9.50 cycles. At this rate:

1% of peak load performance is reached (2.95 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 402a30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
TEST %ECX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JLE 402ca8 <_Z7softmaxPKfPfS1_i+0x278>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA 0x8(%RSP),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x20,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
PUSHQ -0x8(%R10)	2	0	0	0.33	0.33	0.50	0	0	0.50	0.50	0.50	0	0.33	5-12	0.62	N/A
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV $0x1,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
PUSH %R10	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
LEA 0x4(%RDI),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x60,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVL $0,-0x3c(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOVSXD %ECX,%RSI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA 0x4(,%RSI,4),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA 0x4(%RDX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CMPL $0x6,-0x3c(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
LEA (,%RSI,4),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %ECX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RSI,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
JLE 402c5b <_Z7softmaxPKfPfS1_i+0x22b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x3c(%RBP),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSS -0x34(%RBP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
VMOVSS %XMM2,(%RAX,%R14,4)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x60,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
LEA -0x8(%R10),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼softmax(float const, float, float*, int)–	6.93	0.69
▼Loop 32 - attention_v2.cpp:43-61 - attention-gcc-gnr-256–	0.00	0.00
▼Loop 31 - attention_v2.cpp:43-61 - attention-gcc-gnr-256–	0.10	0.01
▼Loop 30 - attention_v2.cpp:43-61 - attention-gcc-gnr-256–	0.05	0.00
○Loop 28 - attention_v2.cpp:55-56 - attention-gcc-gnr-256	6.33	0.63
○Loop 27 - attention_v2.cpp:52-53 - attention-gcc-gnr-256	0.40	0.04
○Loop 29 - attention_v2.cpp:47-48 - attention-gcc-gnr-256	0.05	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code