OV - attention-native - Loop 54

0x128e0 LDP	S0, S1, [X2, #504]    [1]

0x128e4 LDP	S2, S3, [X2], #16    [1]

0x128e8 SUBS	X1, X1, #4

0x128ec STR	S0, [X3]    [2]

0x128f0 STR	S1, [X3, X4,LSL #2]    [2]

0x128f4 STR	S2, [X3, X15]    [2]

0x128f8 STR	S3, [X3, X13]    [2]

0x128fc ADD	X3, X3, X12

0x12900 B.NE	128e0

/home/eoseret/llm-attention/attention.cpp: 245 - 246

--------------------------------------------------------------------------------

245:          for (int j = 0; j < dim; ++j)// vectorized

246:             h_KT[j * context_size + i] = h_K[i * dim + j];

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.78
Bottlenecks	P8, P9, P12, P13, P14,
Function	main
Source	attention.cpp:245-246
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	2.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	2.00
CQA cycles if fully vectorized	0.67
Front-end cycles	1.13
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.58
P3 cycles	0.58
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	0.42
P7 cycles	0.42
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	2.00
P13 cycles	2.00
P14 cycles	2.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	9.00
Nb uops	9.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	12.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	28.57
Vectorization ratio load	100.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	35.71
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.78
Bottlenecks	P8, P9, P12, P13, P14,
Function	main
Source	attention.cpp:245-246
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	2.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	2.00
CQA cycles if fully vectorized	0.67
Front-end cycles	1.13
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.58
P3 cycles	0.58
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	0.42
P7 cycles	0.42
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	2.00
P13 cycles	2.00
P14 cycles	2.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	9.00
Nb uops	9.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	12.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	28.57
Vectorization ratio load	100.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	35.71
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:245-246
Module	attention-native

The loop is defined in /home/eoseret/llm-attention/attention.cpp:245-246.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 35% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 2.00 to 0.67 cycles (3.00x speedup).

Details

28% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 12 bytes.

General properties

nb instructions	9
nb uops	9
loop length	36
used w registers	0
used x registers	7
used b registers	0
used h registers	0
used s registers	4
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.13 cycles
front end	1.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.58	0.58	0.50	0.50	0.42	0.42	2.00	2.00	0.00	0.00	2.00	2.00	2.00	0.00	0.00
cycles	0.50	0.50	0.58	0.58	0.50	0.50	0.42	0.42	2.00	2.00	0.00	0.00	2.00	2.00	2.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.13
Dispatch	2.00
Data deps.	1.00
Overall L1	2.00

Vectorization ratios

all	28%
load	100%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	35%
load	50%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles. At this rate:

12% of peak store performance is reached (6.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 128e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDP S0, S1, [X2, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDP S2, S3, [X2], #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
SUBS X1, X1, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
STR S0, [X3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
STR S1, [X3, X4,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
STR S2, [X3, X15]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
STR S3, [X3, X13]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X3, X3, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B.NE 128e0 <main+0x16c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	attention.cpp:245-246
Module	attention-native

The loop is defined in /home/eoseret/llm-attention/attention.cpp:245-246.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 35% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 2.00 to 0.67 cycles (3.00x speedup).

Details

28% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is storing 12 bytes.

General properties

nb instructions	9
nb uops	9
loop length	36
used w registers	0
used x registers	7
used b registers	0
used h registers	0
used s registers	4
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.13 cycles
front end	1.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.58	0.58	0.50	0.50	0.42	0.42	2.00	2.00	0.00	0.00	2.00	2.00	2.00	0.00	0.00
cycles	0.50	0.50	0.58	0.58	0.50	0.50	0.42	0.42	2.00	2.00	0.00	0.00	2.00	2.00	2.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.13
Dispatch	2.00
Data deps.	1.00
Overall L1	2.00

Vectorization ratios

all	28%
load	100%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	35%
load	50%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles. At this rate:

12% of peak store performance is reached (6.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 128e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDP S0, S1, [X2, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
LDP S2, S3, [X2], #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0.33	0.33	0.33	6	0.33	vect (50.0%)
SUBS X1, X1, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	1	0.33	scal (50.0%)
STR S0, [X3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
STR S1, [X3, X4,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
STR S2, [X3, X15]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
STR S3, [X3, X13]	1	0	0	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50	scal (25.0%)
ADD X3, X3, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	1	0.17	N/A
B.NE 128e0 <main+0x16c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code