OV - attention-native - Loop 49

0x12a60 LDR	X16, [SP, #88]

0x12a64 ADD	X8, X8, #1

0x12a68 CMP	X8, X16

0x12a6c B.EQ	12d18

0x12a70 ORR	W16, WZR, WZR

0x12a74 ORR	W17, WZR, WZR

0x12a78 B	12a94

0x12a80 LDR	X1, [SP, #312]

0x12a84 ADD	W17, W17, #1

0x12a88 ADD	W16, W16, W25

0x12a8c CMP	W17, W1

0x12a90 B.EQ	12a60

0x12a94 MADD	W0, W17, W25, WZR

0x12a98 MADD	W1, W17, W1, WZR

0x12a9c ORR	X18, XZR, XZR

0x12aa0 CMN	W0, W9

0x12aa4 CSINC	W2, W10, WZR, #3

0x12aa8 B	12ad0

  (50) 0x12aac FCVT	S1, D1

  (50) 0x12ab0 LDR	X4, [SP, #272]

  (50) 0x12ab4 ADD	W3, W1, W18

  (50) 0x12ab8 ADD	X18, X18, #1

  (50) 0x12abc FDIV	S1, S1, S0

  (50) 0x12ac0 STR	S1, [X4, W3,UXTW #2]

  (50) 0x12ac4 LDR	X3, [SP, #336]

  (50) 0x12ac8 CMP	X18, X3

  (50) 0x12acc B.EQ	12a80

  (50) 0x12ad0 MOVI	D1, #0

  (50) 0x12ad4 AND	X3, X25, #0x7fffffff

  (50) 0x12ad8 CMP	X3, #4

  (50) 0x12adc B.CC	12aec

  (50) 0x12ae0 CMN	W18, W9

  (50) 0x12ae4 CSINC	W3, W2, WZR, #3

  (50) 0x12ae8 TBZ	W3, #0, 12b8c

  (50) 0x12aec ORR	X3, XZR, XZR

  (50) 0x12af0 ORR	X4, X3, #0x1

  (50) 0x12af4 TBZ	W25, #0, 12b1c

  (50) 0x12af8 ADD	W5, W0, W3

  (50) 0x12afc LDR	S2, [X26, W5,UXTW #2]

  (50) 0x12b00 LDR	X5, [SP, #312]

  (50) 0x12b04 MADD	W3, W3, W5, W18

  (50) 0x12b08 LDR	S3, [X28, W3,UXTW #2]

  (50) 0x12b0c FCVT	D2, S2

  (50) 0x12b10 ORR	X3, XZR, X4

  (50) 0x12b14 FCVT	D3, S3

  (50) 0x12b18 FMADD	D1, D2, D3, D1

  (50) 0x12b1c AND	X5, X25, #0x7fffffff

  (50) 0x12b20 CMP	X5, X4

  (50) 0x12b24 B.EQ	12aac

  (50) 0x12b28 LDR	X7, [SP, #312]

  (50) 0x12b2c AND	X4, X25, #0x7fffffff

  (50) 0x12b30 SUB	X4, X4, X3

  (50) 0x12b34 MADD	X6, X7, X3, XZR

  (50) 0x12b38 ADD	X7, X18, X7

  (50) 0x12b3c ADD	W3, W16, W3

  (50) 0x12b40 ADD	X5, X18, X6

  (50) 0x12b44 ADD	X6, X7, X6

    (51) 0x12b48 LDR	S2, [X26, W3,UXTW #2]

    (51) 0x12b4c LDR	S3, [X28, W5,UXTW #2]

    (51) 0x12b50 ADD	W7, W3, #1

    (51) 0x12b54 SUBS	X4, X4, #2

    (51) 0x12b58 ADD	X5, X5, X15

    (51) 0x12b5c ADD	W3, W3, #2

    (51) 0x12b60 FCVT	D2, S2

    (51) 0x12b64 FCVT	D3, S3

    (51) 0x12b68 FMADD	D1, D2, D3, D1

    (51) 0x12b6c LDR	S2, [X26, W7,UXTW #2]

    (51) 0x12b70 LDR	S3, [X28, W6,UXTW #2]

    (51) 0x12b74 ADD	X6, X6, X15

    (51) 0x12b78 FCVT	D2, S2

    (51) 0x12b7c FCVT	D3, S3

    (51) 0x12b80 FMADD	D1, D2, D3, D1

    (51) 0x12b84 B.NE	12b48

  (50) 0x12b88 B	12aac

  (50) 0x12b8c AND	X3, X25, #0x7fffffff

  (50) 0x12b90 CMP	X3, #16

  (50) 0x12b94 B.CS	12ba4

  (50) 0x12b98 ORR	X5, XZR, XZR

  (50) 0x12b9c MOVI	D1, #0

  (50) 0x12ba0 B	12ca0

  (50) 0x12ba4 AND	X5, X25, #0x0

  (50) 0x12ba8 MOVI	V1.2D, #0

  (50) 0x12bac ORR	W3, WZR, W16

  (50) 0x12bb0 ORR	X4, XZR, X18

  (50) 0x12bb4 MOVI	V2.2D, #0

  (50) 0x12bb8 MOVI	V3.2D, #0

  (50) 0x12bbc MOVI	V5.2D, #0

  (50) 0x12bc0 MOVI	V6.2D, #0

  (50) 0x12bc4 MOVI	V7.2D, #0

  (50) 0x12bc8 MOVI	V4.2D, #0

  (50) 0x12bcc MOVI	V16.2D, #0

  (50) 0x12bd0 HINT	#0

  (50) 0x12bd4 HINT	#0

  (50) 0x12bd8 HINT	#0

  (50) 0x12bdc HINT	#0

    (52) 0x12be0 ADD	X6, X26, W3,UXTW #2

    (52) 0x12be4 SUBS	X5, X5, #16

    (52) 0x12be8 ADD	W3, W3, #16

    (52) 0x12bec LDP	Q17, Q18, [X6]

    (52) 0x12bf0 LDP	Q19, Q20, [X6, #32]

    (52) 0x12bf4 ADD	X6, X28, W4,UXTW #2

    (52) 0x12bf8 ADD	X4, X4, #16

    (52) 0x12bfc FCVTL	V22.2D, V18.2S

    (52) 0x12c00 LDP	Q25, Q26, [X6]

    (52) 0x12c04 LDP	Q27, Q28, [X6, #32]

    (52) 0x12c08 FCVTL2	V18.2D, V18.4S

    (52) 0x12c0c FCVTL	V24.2D, V20.2S

    (52) 0x12c10 FCVTL2	V20.2D, V20.4S

    (52) 0x12c14 FCVTL	V21.2D, V17.2S

    (52) 0x12c18 FCVTL2	V17.2D, V17.4S

    (52) 0x12c1c FCVTL	V23.2D, V19.2S

    (52) 0x12c20 FCVTL2	V19.2D, V19.4S

    (52) 0x12c24 FCVTL	V30.2D, V26.2S

    (52) 0x12c28 FCVTL2	V26.2D, V26.4S

    (52) 0x12c2c FCVTL	V8.2D, V28.2S

    (52) 0x12c30 FCVTL2	V28.2D, V28.4S

    (52) 0x12c34 FCVTL	V29.2D, V25.2S

    (52) 0x12c38 FCVTL2	V25.2D, V25.4S

    (52) 0x12c3c FCVTL	V31.2D, V27.2S

    (52) 0x12c40 FCVTL2	V27.2D, V27.4S

    (52) 0x12c44 FMLA	V6.2D, V26.2D, V18.2D

    (52) 0x12c48 FMLA	V5.2D, V30.2D, V22.2D

    (52) 0x12c4c FMLA	V1.2D, V28.2D, V20.2D

    (52) 0x12c50 FMLA	V16.2D, V8.2D, V24.2D

    (52) 0x12c54 FMLA	V3.2D, V25.2D, V17.2D

    (52) 0x12c58 FMLA	V2.2D, V29.2D, V21.2D

    (52) 0x12c5c FMLA	V4.2D, V27.2D, V19.2D

    (52) 0x12c60 FMLA	V7.2D, V31.2D, V23.2D

    (52) 0x12c64 B.NE	12be0

  (50) 0x12c68 FADD	V2.2D, V5.2D, V2.2D

  (50) 0x12c6c FADD	V3.2D, V6.2D, V3.2D

  (50) 0x12c70 FADD	V5.2D, V16.2D, V7.2D

  (50) 0x12c74 FADD	V1.2D, V1.2D, V4.2D

  (50) 0x12c78 AND	X3, X25, #0x7fffffff

  (50) 0x12c7c FADD	V2.2D, V5.2D, V2.2D

  (50) 0x12c80 FADD	V1.2D, V1.2D, V3.2D

  (50) 0x12c84 FADD	V1.2D, V2.2D, V1.2D

  (50) 0x12c88 FADDP	D1, V1.2D

  (50) 0x12c8c CMP	X3, X12

  (50) 0x12c90 B.EQ	12aac

  (50) 0x12c94 AND	X5, X25, #0x0

  (50) 0x12c98 AND	X3, X25, #0x0

  (50) 0x12c9c CBZ	X11, 12af0

  (50) 0x12ca0 MOVI	V3.2D, #0

  (50) 0x12ca4 MOV	V3.D[0], V1.D[0]

  (50) 0x12ca8 ADD	X3, X14, X5

  (50) 0x12cac ADD	X4, X5, X18

  (50) 0x12cb0 ADD	W5, W16, W5

  (50) 0x12cb4 MOVI	V2.2D, #0

  (50) 0x12cb8 HINT	#0

  (50) 0x12cbc HINT	#0

    (53) 0x12cc0 UBFM	X6, X5, #62, #31

    (53) 0x12cc4 ADDS	X3, X3, #4

    (53) 0x12cc8 ADD	W5, W5, #4

    (53) 0x12ccc LDR	Q1, [X26, X6]

    (53) 0x12cd0 ORR	W6, WZR, W4

    (53) 0x12cd4 UBFM	X6, X6, #62, #61

    (53) 0x12cd8 ADD	X4, X4, #4

    (53) 0x12cdc LDR	Q5, [X28, X6]

    (53) 0x12ce0 FCVTL	V4.2D, V1.2S

    (53) 0x12ce4 FCVTL2	V1.2D, V1.4S

    (53) 0x12ce8 FCVTL	V6.2D, V5.2S

    (53) 0x12cec FCVTL2	V5.2D, V5.4S

    (53) 0x12cf0 FMLA	V2.2D, V5.2D, V1.2D

    (53) 0x12cf4 FMLA	V3.2D, V6.2D, V4.2D

    (53) 0x12cf8 B.NE	12cc0

  (50) 0x12cfc FADD	V1.2D, V3.2D, V2.2D

  (50) 0x12d00 AND	X3, X25, #0x0

  (50) 0x12d04 AND	X4, X25, #0x7fffffff

  (50) 0x12d08 FADDP	D1, V1.2D

  (50) 0x12d0c CMP	X4, X13

  (50) 0x12d10 B.EQ	12aac

  (50) 0x12d14 B	12af0

/home/eoseret/llm-attention/attention.cpp: 26 - 267

--------------------------------------------------------------------------------

26:    for (unsigned int i = 0; i < M; ++i) {

27:       for (unsigned int j = 0; j < N; ++j) {  //vectorized

28:          double sum = 0.0;

29: #pragma clang loop vectorize(enable)

30:          for (unsigned int k = 0; k < K; ++k) { //vectorized

31:             sum += (double)A[i * K + k] * (double)B[k * N + j];

32:          }

33:          C[i * N + j] = alpha * static_cast<float>(sum);

[...]

267:    for (size_t r = 0; r < rept; r++)

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.13
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:26-26,attention.cpp:267-267
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.25
CQA cycles if no scalar integer	2.25
CQA cycles if FP arith vectorized	2.25
CQA cycles if fully vectorized	0.72
Front-end cycles	2.25
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.67
P13 cycles	0.67
P14 cycles	0.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.00
Nb uops	18.00
Nb loads	NA
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	35.42
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	33.33
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	33.33

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.13
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:26-26,attention.cpp:267-267
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.25
CQA cycles if no scalar integer	2.25
CQA cycles if FP arith vectorized	2.25
CQA cycles if fully vectorized	0.72
Front-end cycles	2.25
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.67
P13 cycles	0.67
P14 cycles	0.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.00
Nb uops	18.00
Nb loads	NA
Nb stores	0.00
Nb stack references	2.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	35.42
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	33.33
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	33.33

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:26-267
Module	attention-native

The loop is defined in /home/eoseret/llm-attention/attention.cpp:26-33,267.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:26,267.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 35% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.25 to 0.72 cycles (3.13x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	18
nb uops	18
loop length	72
used w registers	9
used x registers	5
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.25 cycles
front end	2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	2.00	2.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00
cycles	2.00	2.00	2.00	2.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.25
Dispatch	2.00
Overall L1	2.25

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	35%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.25 cycles.

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.25 to 2.00 cycles (1.12x speedup).

ASM code

In the binary file, the address of the loop is: 12a80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X16, [SP, #88]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
ADD X8, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	scal (50.0%)
CMP X8, X16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	scal (50.0%)
B.EQ 12d18 <main+0x1af8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W16, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	scal (25.0%)
ORR W17, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	scal (25.0%)
B 12a94 <main+0x1874>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #312]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
ADD W17, W17, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	scal (25.0%)
ADD W16, W16, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	scal (25.0%)
CMP W17, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.EQ 12a60 <main+0x1840>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W0, W17, W25, WZR	1	0	0	0	0	0	0	1	0	0	0	0	2	1	N/A
MADD W1, W17, W1, WZR	1	0	0	0	0	0	0	1	0	0	0	0	2	1	scal (25.0%)
ORR X18, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	scal (50.0%)
CMN W0, W9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	N/A
CSINC W2, W10, WZR, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	scal (25.0%)
B 12ad0 <main+0x18b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	attention.cpp:26-267
Module	attention-native

The loop is defined in /home/eoseret/llm-attention/attention.cpp:26-33,267.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:26,267.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 35% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.25 to 0.72 cycles (3.13x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	18
nb uops	18
loop length	72
used w registers	9
used x registers	5
used b registers	0
used h registers	0
used s registers	1
used d registers	0
used q registers	0
used v registers	0
used z registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	2.25 cycles
front end	2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	2.00	2.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00
cycles	2.00	2.00	2.00	2.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.25
Dispatch	2.00
Overall L1	2.25

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	35%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.25 cycles.

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.25 to 2.00 cycles (1.12x speedup).

ASM code

In the binary file, the address of the loop is: 12a80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR X16, [SP, #88]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
ADD X8, X8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	scal (50.0%)
CMP X8, X16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	scal (50.0%)
B.EQ 12d18 <main+0x1af8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR W16, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	scal (25.0%)
ORR W17, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	scal (25.0%)
B 12a94 <main+0x1874>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X1, [SP, #312]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	scal (50.0%)
ADD W17, W17, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	scal (25.0%)
ADD W16, W16, W25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	scal (25.0%)
CMP W17, W1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	scal (25.0%)
B.EQ 12a60 <main+0x1840>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MADD W0, W17, W25, WZR	1	0	0	0	0	0	0	1	0	0	0	0	2	1	N/A
MADD W1, W17, W1, WZR	1	0	0	0	0	0	0	1	0	0	0	0	2	1	scal (25.0%)
ORR X18, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	scal (50.0%)
CMN W0, W9	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	1	0.33	N/A
CSINC W2, W10, WZR, #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	1	0.17	scal (25.0%)
B 12ad0 <main+0x18b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code