OV - attention-native - Loop 48

0x131a4 LDR	Q0, [X26, X24]    [2]

0x131a8 FSUB	V0.4S, V0.4S, V17.4S

0x131ac BL	10040

0x131b0 FDIV	V0.4S, V0.4S, V16.4S

0x131b4 ADDS	X23, X23, #4

0x131b8 STR	Q0, [X28, X24]    [1]

0x131bc ADD	X24, X24, #16

0x131c0 B.NE	131a4

/home/eoseret/llm-attention/attention.cpp: 55 - 56

--------------------------------------------------------------------------------

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.50 - 4.50
Bottlenecks	P8, P10,
Function	main
Source	attention.cpp:55-56
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	3.50 - 4.50
CQA cycles if no scalar integer	3.50 - 4.50
CQA cycles if FP arith vectorized	3.50 - 4.50
CQA cycles if fully vectorized	3.50 - 4.50
Front-end cycles	1.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	1.00
P9 cycles	0.75
P10 cycles	0.75
P11 cycles	0.50
P12 cycles	0.83
P13 cycles	0.50
P14 cycles	0.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	3.50 - 4.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	8.00
Nb uops	8.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.29 - 1.78
Nb FLOP add-sub	4.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	2.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	80.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	50.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	90.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	75.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.50 - 4.50
Bottlenecks	P8, P10,
Function	main
Source	attention.cpp:55-56
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	3.50 - 4.50
CQA cycles if no scalar integer	3.50 - 4.50
CQA cycles if FP arith vectorized	3.50 - 4.50
CQA cycles if fully vectorized	3.50 - 4.50
Front-end cycles	1.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	0.50
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	1.00
P9 cycles	0.75
P10 cycles	0.75
P11 cycles	0.50
P12 cycles	0.83
P13 cycles	0.50
P14 cycles	0.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	3.50 - 4.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	8.00
Nb uops	8.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.29 - 1.78
Nb FLOP add-sub	4.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	2.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	80.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	50.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	90.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	75.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:55-56
Module	attention-native

The loop is defined in /home/eoseret/llm-attention/attention.cpp:55-56.

The related source loop is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is partially vectorized. 90% of vector register length is used (average across all VPU instructions).

Details

80% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU addition or subtraction instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.50 to 1.00 cycles (4.50x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:56

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction
4: divide

The binary loop does not load or store any data.

General properties

nb instructions	8
nb uops	8
loop length	32
used w registers	0
used x registers	4
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	1
used v registers	3
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.00 cycles
front end	1.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.00	1.00	0.50	0.50	0.50	0.50	0.50	0.50	1.00	0.75	0.75	0.50	0.83	0.50	0.67	0.00	0.00
cycles	1.00	1.00	0.50	0.50	0.50	0.50	0.50	0.50	1.00	0.75	0.75	0.50	0.83	0.50	0.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	3.50-4.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.00
Dispatch	1.00
DIV/SQRT	3.50-4.50
Data deps.	1.00
Overall L1	3.50-4.50

Vectorization ratios

INT

all	66%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

FP

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	80%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	83%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

FP

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	90%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.50 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 131a4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR Q0, [X26, X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FSUB V0.4S, V0.4S, V17.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
BL 10040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV V0.4S, V0.4S, V16.4S	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-10	3.50-4.50	vect (100.0%)
ADDS X23, X23, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
STR Q0, [X28, X24]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X24, X24, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
B.NE 131a4 <main+0x1f84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	attention.cpp:55-56
Module	attention-native

The loop is defined in /home/eoseret/llm-attention/attention.cpp:55-56.

The related source loop is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is partially vectorized. 90% of vector register length is used (average across all VPU instructions).

Details

80% of VPU instructions are used in vector version (process two or more data elements in vector registers):

50% of VPU addition or subtraction instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.50 to 1.00 cycles (4.50x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:56

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction
4: divide

The binary loop does not load or store any data.

General properties

nb instructions	8
nb uops	8
loop length	32
used w registers	0
used x registers	4
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	1
used v registers	3
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.00 cycles
front end	1.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.00	1.00	0.50	0.50	0.50	0.50	0.50	0.50	1.00	0.75	0.75	0.50	0.83	0.50	0.67	0.00	0.00
cycles	1.00	1.00	0.50	0.50	0.50	0.50	0.50	0.50	1.00	0.75	0.75	0.50	0.83	0.50	0.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	3.50-4.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.00
Dispatch	1.00
DIV/SQRT	3.50-4.50
Data deps.	1.00
Overall L1	3.50-4.50

Vectorization ratios

INT

all	66%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

FP

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	80%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

INT

all	83%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

FP

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	90%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.50 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 131a4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR Q0, [X26, X24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FSUB V0.4S, V0.4S, V17.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
BL 10040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV V0.4S, V0.4S, V16.4S	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-10	3.50-4.50	vect (100.0%)
ADDS X23, X23, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
STR Q0, [X28, X24]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X24, X24, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
B.NE 131a4 <main+0x1f84>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Slow data structures access

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code