OV - attention-native - Loop 44

	Loop Id: 44	Module: attention-native	Source: attention.cpp:43-289 [...]	Coverage: 0.06%

0x12dac LDP	X9, X8, [SP, #80]

0x12db0 ADD	X9, X9, #1

0x12db4 STR	X9, [SP, #80]

0x12db8 CMP	X9, X8

0x12dbc B.EQ	1324c

0x12dc0 ADD	X8, X27, #32

0x12dc4 MOVZ	W9, #1

0x12dc8 STR	XZR, [SP, #192]

0x12dcc ORR	X28, XZR, X27

0x12dd0 STR	X8, [SP, #232]

0x12dd4 LDR	X8, [SP, #272]

0x12dd8 ADD	X12, X8, #32

0x12ddc STR	X8, [SP, #264]

0x12de0 B	12e30

0x12de4 LDP	X26, X8, [SP, #136]

0x12de8 LDR	X9, [SP, #240]

0x12dec LDR	X12, [SP, #208]

0x12df0 ADD	X28, X28, X23

0x12df4 ADD	X9, X9, #1

0x12df8 STR	S22, [X8, X21,LSL #2]

0x12dfc LDR	X8, [SP, #264]

0x12e00 ADD	X12, X12, X23

0x12e04 LDR	X21, [SP, #128]

0x12e08 STR	X22, [SP, #192]

0x12e0c ADD	X8, X8, X23

0x12e10 STR	X8, [SP, #264]

0x12e14 LDR	X8, [SP, #232]

0x12e18 ADD	X8, X8, X23

0x12e1c STR	X8, [SP, #232]

0x12e20 LDR	X8, [SP, #336]

0x12e24 CMP	X22, X8

0x12e28 LDR	X22, [SP, #152]

0x12e2c B.EQ	12dac

0x12e30 AND	X21, X9, #0x0

0x12e34 AND	X8, X9, #0x0

0x12e38 ORR	X26, XZR, X9

0x12e3c STP	X8, X28, [SP, #176]

0x12e40 CMP	X9, #4

0x12e44 B.CS	12e60

0x12e48 MOVN	W9, #128

0x12e4c LDR	X28, [SP, #264]

0x12e50 ORR	X8, XZR, XZR

0x12e54 FMOV	S9, W9

0x12e58 B	12f20

0x12e60 CMP	X26, #16

0x12e64 B.CS	12e80

0x12e68 LDR	X28, [SP, #264]

0x12e6c MOVN	W9, #128

0x12e70 ORR	X8, XZR, XZR

0x12e74 FMOV	S9, W9

0x12e78 B	12ee0

0x12e80 LDR	X28, [SP, #264]

0x12e84 MVNI	V0.4S, #128

0x12e88 MVNI	V1.4S, #128

0x12e8c MVNI	V2.4S, #128

0x12e90 MVNI	V3.4S, #128

0x12e94 AND	X9, X26, #0x0

0x12e98 AND	X8, X26, #0x0

0x12e9c AND	X11, X26, #0x0

0x12ea0 ORR	X10, XZR, X12

  (41) 0x12ea4 LDP	Q4, Q5, [X10, #2016]

  (41) 0x12ea8 SUBS	X11, X11, #16

  (41) 0x12eac FMAXNM	V1.4S, V5.4S, V1.4S

  (41) 0x12eb0 FMAXNM	V0.4S, V4.4S, V0.4S

  (41) 0x12eb4 LDP	Q6, Q7, [X10], #64

  (41) 0x12eb8 FMAXNM	V2.4S, V6.4S, V2.4S

  (41) 0x12ebc FMAXNM	V3.4S, V7.4S, V3.4S

  (41) 0x12ec0 B.NE	12ea4

0x12ec4 FMAXNM	V0.4S, V0.4S, V1.4S

0x12ec8 FMAXNM	V0.4S, V0.4S, V2.4S

0x12ecc FMAXNM	V0.4S, V0.4S, V3.4S

0x12ed0 FMAXNMV	S9, V0.4S

0x12ed4 CMP	X26, X8

0x12ed8 B.EQ	12f34

0x12edc CBZ	X9, 12f20

0x12ee0 DUP	V0.4S, V9.S[0]

0x12ee4 SUB	X9, X8, X21

0x12ee8 ADD	X10, X28, X8,LSL #2

0x12eec AND	X8, X26, #0x0

0x12ef0 HINT	#0

0x12ef4 HINT	#0

0x12ef8 HINT	#0

0x12efc HINT	#0

  (46) 0x12f00 LDR	Q1, [X10], #16

  (46) 0x12f04 ADDS	X9, X9, #4

  (46) 0x12f08 FMAXNM	V0.4S, V1.4S, V0.4S

  (46) 0x12f0c B.NE	12f00

0x12f10 FMAXNMV	S9, V0.4S

0x12f14 B	12f2c

  (45) 0x12f20 LDR	S0, [X28, X8,LSL #2]

  (45) 0x12f24 ADD	X8, X8, #1

  (45) 0x12f28 FMAXNM	S9, S0, S9

  (45) 0x12f2c CMP	X26, X8

  (45) 0x12f30 B.NE	12f20

0x12f34 STR	Q9, [SP, #288]

0x12f38 STR	X12, [SP, #208]

0x12f3c CMP	X26, #4

0x12f40 B.CS	12f60

0x12f60 CMP	X26, #16

0x12f64 B.CS	12f80

0x12f68 ORR	X22, XZR, XZR

0x12f6c MOVI	D22, #0

0x12f70 B	1302c

0x1302c MOVI	V16.2D, #0

0x13030 MOV	V16.S[0], V22.S[0]

0x13034 DUP	V17.4S, V9.S[0]

0x13038 SUB	X23, X22, X21

0x1303c UBFM	X24, X22, #62, #61

0x13040 AND	X22, X26, #0x0

  (43) 0x13044 LDR	Q0, [X28, X24]

  (43) 0x13048 FSUB	V0.4S, V0.4S, V17.4S

  (43) 0x1304c BL	10040

  (43) 0x13050 FADD	V16.4S, V0.4S, V16.4S

  (43) 0x13054 ADDS	X23, X23, #4

  (43) 0x13058 ADD	X24, X24, #16

  (43) 0x1305c B.NE	13044

0x13060 FADDP	V0.4S, V16.4S, V16.4S

0x13064 LDP	X23, X24, [SP, #160]

0x13068 FADDP	S22, V0.2S

0x1306c CMP	X26, X22

0x13070 B.EQ	130a8

0x130a8 STR	X26, [SP, #240]

0x130ac STR	Q22, [SP, #320]

0x130b0 CMP	X26, #4

0x130b4 B.CS	130cc

0x130b8 ORR	X21, XZR, X26

0x130bc ORR	X26, XZR, X28

0x130c0 LDR	X28, [SP, #184]

0x130c4 ORR	X22, XZR, XZR

0x130c8 B	131e0

0x130cc STR	X21, [SP, #120]

0x130d0 CMP	X26, #16

0x130d4 B.CS	130ec

0x130d8 ORR	X21, XZR, X26

0x130dc ORR	X26, XZR, X28

0x130e0 LDR	X28, [SP, #184]

0x130e4 ORR	X22, XZR, XZR

0x130e8 B	1318c

0x130ec LDR	X23, [SP, #232]

0x130f0 LDR	X24, [SP, #208]

0x130f4 LDR	X21, [SP, #176]

0x130f8 DUP	V20.4S, V22.S[0]

0x130fc DUP	V21.4S, V9.S[0]

0x13100 AND	X8, X26, #0x0

0x13104 AND	X22, X26, #0x0

0x13108 STR	X8, [SP, #96]

  (40) 0x1310c LDP	Q0, Q1, [X24, #2016]

  (40) 0x13110 FSUB	V16.4S, V1.4S, V21.4S

  (40) 0x13114 FSUB	V0.4S, V0.4S, V21.4S

  (40) 0x13118 LDP	Q2, Q3, [X24], #64

  (40) 0x1311c FSUB	V17.4S, V2.4S, V21.4S

  (40) 0x13120 FSUB	V18.4S, V3.4S, V21.4S

  (40) 0x13124 BL	10040

  (40) 0x13128 ORR	V19.16B, V0.16B, V0.16B

  (40) 0x1312c ORR	V0.16B, V16.16B, V16.16B

  (40) 0x13130 BL	10040

  (40) 0x13134 ORR	V16.16B, V0.16B, V0.16B

  (40) 0x13138 ORR	V0.16B, V17.16B, V17.16B

  (40) 0x1313c BL	10040

  (40) 0x13140 ORR	V17.16B, V0.16B, V0.16B

  (40) 0x13144 ORR	V0.16B, V18.16B, V18.16B

  (40) 0x13148 BL	10040

  (40) 0x1314c FDIV	V1.4S, V19.4S, V20.4S

  (40) 0x13150 SUBS	X21, X21, #16

  (40) 0x13154 FDIV	V2.4S, V16.4S, V20.4S

  (40) 0x13158 STP	Q1, Q2, [X23, #2016]

  (40) 0x1315c FDIV	V1.4S, V17.4S, V20.4S

  (40) 0x13160 FDIV	V0.4S, V0.4S, V20.4S

  (40) 0x13164 STP	Q1, Q0, [X23], #64

  (40) 0x13168 B.NE	1310c

0x1316c LDP	X23, X24, [SP, #160]

0x13170 LDR	X28, [SP, #184]

0x13174 ORR	X21, XZR, X26

0x13178 CMP	X26, X22

0x1317c LDR	X26, [SP, #264]

0x13180 B.EQ	13208

0x13184 LDR	X8, [SP, #96]

0x13188 CBZ	X8, 131e0

0x1318c LDR	X8, [SP, #120]

0x13190 DUP	V16.4S, V22.S[0]

0x13194 DUP	V17.4S, V9.S[0]

0x13198 UBFM	X24, X22, #62, #61

0x1319c SUB	X23, X22, X8

0x131a0 AND	X22, X21, #0x0

  (48) 0x131a4 LDR	Q0, [X26, X24]

  (48) 0x131a8 FSUB	V0.4S, V0.4S, V17.4S

  (48) 0x131ac BL	10040

  (48) 0x131b0 FDIV	V0.4S, V0.4S, V16.4S

  (48) 0x131b4 ADDS	X23, X23, #4

  (48) 0x131b8 STR	Q0, [X28, X24]

  (48) 0x131bc ADD	X24, X24, #16

  (48) 0x131c0 B.NE	131a4

0x131c4 LDR	X21, [SP, #240]

0x131c8 LDP	X23, X24, [SP, #160]

0x131cc CMP	X21, X22

0x131d0 B.EQ	13208

0x131d4 HINT	#0

0x131d8 HINT	#0

0x131dc HINT	#0

  (47) 0x131e0 LDR	S0, [X26, X22,LSL #2]

  (47) 0x131e4 FSUB	S0, S0, S9

  (47) 0x131e8 BL	101c0

  (47) 0x131ec LDR	Q22, [SP, #320]

  (47) 0x131f0 LDR	Q9, [SP, #288]

  (47) 0x131f4 FDIV	S0, S0, S22

  (47) 0x131f8 STR	S0, [X28, X22,LSL #2]

  (47) 0x131fc ADD	X22, X22, #1

  (47) 0x13200 CMP	X21, X22

  (47) 0x13204 B.NE	131e0

0x13208 LDR	X21, [SP, #192]

0x1320c LDR	X8, [SP, #336]

0x13210 ADD	X22, X21, #1

0x13214 CMP	X22, X8

0x13218 B.CS	12de4

0x1321c LDP	X9, X8, [SP, #104]

0x13220 MOVZ	X10, #4

0x13224 ORR	W1, WZR, WZR

0x13228 MADD	X9, X9, X21, X10

0x1322c SUB	W8, W8, W21

0x13230 UBFM	X8, X8, #62, #31

0x13234 AND	X9, X9, #0x0

0x13238 ADD	X2, X8, #4

0x1323c ADD	X0, X27, X9

0x13240 BL	100c0

0x13244 LDR	Q22, [SP, #320]

0x13248 B	12de4

/home/eoseret/llm-attention/attention.cpp: 43 - 289

--------------------------------------------------------------------------------

43:    for (int row = 0; row < N; ++row) {

44:       const float *S_row = &S[row * N];

45:

46:       float max_val = -FLT_MAX;

47:       for (int idx = 0; idx <= row; ++idx) // vectorised

48:          if (S_row[idx] > max_val) max_val = S_row[idx];

49:

50:       float sum = 0.0f;

51: #pragma clang loop vectorize(enable)

52:       for (int idx = 0; idx <= row; ++idx) // vectorised

53:          sum += expf(S_row[idx] - max_val);

54:

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

57:

58:       for (int idx = row + 1; idx < N; ++idx)

59:          P[row * N + idx] = 0.0f;

60:

61:       D[row] = sum;

[...]

289:    for (size_t r = 0; r < rept; r++)

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.64
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.26
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.26
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:43-44,attention.cpp:47-47,attention.cpp:52-52,attention.cpp:55-55,attention.cpp:58-61,attention.cpp:289-289
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	19.13
CQA cycles if no scalar integer	5.25
CQA cycles if FP arith vectorized	19.07
CQA cycles if fully vectorized	15.12
Front-end cycles	19.13
P0 cycles	12.00
P1 cycles	12.00
P2 cycles	10.58
P3 cycles	10.58
P4 cycles	10.50
P5 cycles	10.50
P6 cycles	10.42
P7 cycles	10.42
P8 cycles	6.25
P9 cycles	6.25
P10 cycles	6.25
P11 cycles	6.25
P12 cycles	15.17
P13 cycles	14.83
P14 cycles	15.00
P15 cycles	6.00
P16 cycles	6.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	160.00
Nb uops	153.00
Nb loads	NA
Nb stores	15.00
Nb stack references	44.00
FLOP/cycle	0.26
Nb FLOP add-sub	5.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.16
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	3.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	16.85
Vectorization ratio load	6.67
Vectorization ratio store	13.33
Vectorization ratio mul	NA
Vectorization ratio add_sub	10.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	22.45
Vector-efficiency ratio all	58.15
Vector-efficiency ratio load	63.33
Vector-efficiency ratio store	58.33
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	55.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	57.14

Metric	Value
CQA speedup if no scalar integer	3.64
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.26
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.26
Bottlenecks	micro-operation queue,
Function	main
Source	attention.cpp:43-44,attention.cpp:47-47,attention.cpp:52-52,attention.cpp:55-55,attention.cpp:58-61,attention.cpp:289-289
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	19.13
CQA cycles if no scalar integer	5.25
CQA cycles if FP arith vectorized	19.07
CQA cycles if fully vectorized	15.12
Front-end cycles	19.13
P0 cycles	12.00
P1 cycles	12.00
P2 cycles	10.58
P3 cycles	10.58
P4 cycles	10.50
P5 cycles	10.50
P6 cycles	10.42
P7 cycles	10.42
P8 cycles	6.25
P9 cycles	6.25
P10 cycles	6.25
P11 cycles	6.25
P12 cycles	15.17
P13 cycles	14.83
P14 cycles	15.00
P15 cycles	6.00
P16 cycles	6.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	160.00
Nb uops	153.00
Nb loads	NA
Nb stores	15.00
Nb stack references	44.00
FLOP/cycle	0.26
Nb FLOP add-sub	5.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.16
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	3.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	16.85
Vectorization ratio load	6.67
Vectorization ratio store	13.33
Vectorization ratio mul	NA
Vectorization ratio add_sub	10.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	22.45
Vector-efficiency ratio all	58.15
Vector-efficiency ratio load	63.33
Vector-efficiency ratio store	58.33
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	55.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	57.14

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:43-289
Module	attention-native

The loop is defined in /home/eoseret/llm-attention/attention.cpp:43-61,289.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:43-44,47,52,55,58-61,289.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.13 to 5.25 cycles (3.64x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 58% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 19.13 to 15.12 cycles (1.26x speedup).

Details

16% of VPU instructions are used in vector version (process two or more data elements in vector registers):

6% of VPU loads are used in vector version.
13% of VPU stores are used in vector version.
10% of VPU addition or subtraction instructions are used in vector version.
22% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:59

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 5 FP arithmetical operations:

5: addition or subtraction

The binary loop is storing 3 bytes.

Arithmetic intensity

Arithmetic intensity is 1.67 FP operations per loaded or stored byte.

General properties

nb instructions	160
nb uops	153
loop length	640
used w registers	5
used x registers	15
used b registers	0
used h registers	0
used s registers	3
used d registers	1
used q registers	2
used v registers	10
used z registers	0
nb stack references	44

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.13 cycles
front end	19.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	12.00	12.00	10.58	10.58	10.50	10.50	10.42	10.42	6.25	6.25	6.25	6.25	15.17	14.83	15.00	6.00	6.00
cycles	12.00	12.00	10.58	10.58	10.50	10.50	10.42	10.42	6.25	6.25	6.25	6.25	15.17	14.83	15.00	6.00	6.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.13
Dispatch	15.17
Overall L1	19.13

Vectorization ratios

INT

all	11%
load	6%
store	13%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	66%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	71%

INT+FP

all	16%
load	6%
store	13%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Vector efficiency ratios

INT

all	55%
load	63%
store	58%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	53%

all	77%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	78%

INT+FP

all	58%
load	63%
store	58%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	55%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	57%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 19.13 cycles. At this rate:

0% of peak store performance is reached (0.16 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 19.13 to 15.17 cycles (1.26x speedup).

ASM code

In the binary file, the address of the loop is: 130a8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDP X9, X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD X9, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X9, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X9, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 1324c <main+0x202c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X27, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR XZR, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X28, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X12, X8, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X8, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 12e30 <main+0x1c10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X26, X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X28, X28, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X9, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR S22, [X8, X21,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X8, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X12, X12, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X22, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, X8, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X8, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X22, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
LDR X22, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B.EQ 12dac <main+0x1b8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X21, X9, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X8, X9, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X8, X28, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
CMP X9, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 12e60 <main+0x1c40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN W9, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X28, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMOV S9, W9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 12f20 <main+0x1d00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X26, #16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 12e80 <main+0x1c60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVN W9, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMOV S9, W9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 12ee0 <main+0x1cc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MVNI V0.4S, #128	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MVNI V1.4S, #128	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MVNI V2.4S, #128	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MVNI V3.4S, #128	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
AND X9, X26, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X8, X26, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X11, X26, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X10, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FMAXNM V0.4S, V0.4S, V1.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMAXNM V0.4S, V0.4S, V2.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMAXNM V0.4S, V0.4S, V3.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMAXNMV S9, V0.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	vect (100.0%)
CMP X26, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 12f34 <main+0x1d14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X9, 12f20 <main+0x1d00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
DUP V0.4S, V9.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SUB X9, X8, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X28, X8,LSL #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
AND X8, X26, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
FMAXNMV S9, V0.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	vect (100.0%)
B 12f2c <main+0x1d0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR Q9, [SP, #288]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR X12, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X26, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 12f60 <main+0x1d40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X26, #16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 12f80 <main+0x1d60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X22, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVI D22, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
B 1302c <main+0x1e0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI V16.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOV V16.S[0], V22.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
DUP V17.4S, V9.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SUB X23, X22, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X24, X22, #62, #61	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
AND X22, X26, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FADDP V0.4S, V16.4S, V16.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDP X23, X24, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
FADDP S22, V0.2S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
CMP X26, X22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 130a8 <main+0x1e88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X26, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR Q22, [SP, #320]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CMP X26, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 130cc <main+0x1eac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X28, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X22, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 131e0 <main+0x1fc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X21, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X26, #16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 130ec <main+0x1ecc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X28, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X22, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 1318c <main+0x1f6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X24, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP V20.4S, V22.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP V21.4S, V9.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
AND X8, X26, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X22, X26, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X23, X24, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X28, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X21, XZR, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X26, X22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
LDR X26, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B.EQ 13208 <main+0x1fe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 131e0 <main+0x1fc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP V16.4S, V22.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP V17.4S, V9.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
UBFM X24, X22, #62, #61	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X23, X22, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
AND X22, X21, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X21, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X23, X24, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CMP X21, X22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 13208 <main+0x1fe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X21, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X22, X21, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X22, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 12de4 <main+0x1bc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
MOVZ X10, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD X9, X9, X21, X10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUB W8, W8, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X8, X8, #62, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X9, X9, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X8, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X27, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q22, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
B 12de4 <main+0x1bc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	attention.cpp:43-289
Module	attention-native

The loop is defined in /home/eoseret/llm-attention/attention.cpp:43-61,289.

Analyzed code is defined in /home/eoseret/llm-attention/attention.cpp:43-44,47,52,55,58-61,289.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.13 to 5.25 cycles (3.64x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

16% of VPU instructions are used in vector version (process two or more data elements in vector registers):

6% of VPU loads are used in vector version.
13% of VPU stores are used in vector version.
10% of VPU addition or subtraction instructions are used in vector version.
22% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences►
- /home/eoseret/llm-attention/attention.cpp:59

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 5 FP arithmetical operations:

5: addition or subtraction

The binary loop is storing 3 bytes.

Arithmetic intensity

Arithmetic intensity is 1.67 FP operations per loaded or stored byte.

General properties

nb instructions	160
nb uops	153
loop length	640
used w registers	5
used x registers	15
used b registers	0
used h registers	0
used s registers	3
used d registers	1
used q registers	2
used v registers	10
used z registers	0
nb stack references	44

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.13 cycles
front end	19.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	12.00	12.00	10.58	10.58	10.50	10.50	10.42	10.42	6.25	6.25	6.25	6.25	15.17	14.83	15.00	6.00	6.00
cycles	12.00	12.00	10.58	10.58	10.50	10.50	10.42	10.42	6.25	6.25	6.25	6.25	15.17	14.83	15.00	6.00	6.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.13
Dispatch	15.17
Overall L1	19.13

Vectorization ratios

INT

all	11%
load	6%
store	13%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	66%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	71%

INT+FP

all	16%
load	6%
store	13%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	22%

Vector efficiency ratios

INT

all	55%
load	63%
store	58%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	53%

all	77%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	75%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	78%

INT+FP

all	58%
load	63%
store	58%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	55%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	57%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 19.13 cycles. At this rate:

0% of peak store performance is reached (0.16 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 130a8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDP X9, X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD X9, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X9, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X9, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 1324c <main+0x202c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X27, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR XZR, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ORR X28, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X12, X8, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X8, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 12e30 <main+0x1c10>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X26, X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X12, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X28, X28, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X9, X9, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR S22, [X8, X21,LSL #2]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (25.0%)
LDR X8, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X12, X12, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X22, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X8, X8, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X8, X8, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X22, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
LDR X22, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B.EQ 12dac <main+0x1b8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND X21, X9, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X8, X9, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X8, X28, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
CMP X9, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 12e60 <main+0x1c40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVN W9, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X28, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMOV S9, W9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 12f20 <main+0x1d00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X26, #16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 12e80 <main+0x1c60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVN W9, #128	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X8, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
FMOV S9, W9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
B 12ee0 <main+0x1cc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MVNI V0.4S, #128	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MVNI V1.4S, #128	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MVNI V2.4S, #128	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
MVNI V3.4S, #128	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
AND X9, X26, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X8, X26, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X11, X26, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X10, XZR, X12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FMAXNM V0.4S, V0.4S, V1.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMAXNM V0.4S, V0.4S, V2.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMAXNM V0.4S, V0.4S, V3.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
FMAXNMV S9, V0.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	vect (100.0%)
CMP X26, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 12f34 <main+0x1d14>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CBZ X9, 12f20 <main+0x1d00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
DUP V0.4S, V9.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SUB X9, X8, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X28, X8,LSL #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
AND X8, X26, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
FMAXNMV S9, V0.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	vect (100.0%)
B 12f2c <main+0x1d0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR Q9, [SP, #288]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR X12, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X26, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 12f60 <main+0x1d40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP X26, #16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 12f80 <main+0x1d60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X22, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVI D22, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
B 1302c <main+0x1e0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVI V16.2D, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOV V16.S[0], V22.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
DUP V17.4S, V9.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
SUB X23, X22, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X24, X22, #62, #61	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
AND X22, X26, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FADDP V0.4S, V16.4S, V16.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDP X23, X24, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
FADDP S22, V0.2S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
CMP X26, X22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 130a8 <main+0x1e88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X26, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR Q22, [SP, #320]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CMP X26, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 130cc <main+0x1eac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X28, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X22, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 131e0 <main+0x1fc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STR X21, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X26, #16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 130ec <main+0x1ecc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X26, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X28, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X22, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 1318c <main+0x1f6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X23, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X24, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP V20.4S, V22.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP V21.4S, V9.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
AND X8, X26, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X22, X26, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X23, X24, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR X28, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X21, XZR, X26	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X26, X22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
LDR X26, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
B.EQ 13208 <main+0x1fe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X8, 131e0 <main+0x1fc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
DUP V16.4S, V22.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP V17.4S, V9.S[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
UBFM X24, X22, #62, #61	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X23, X22, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
AND X22, X21, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X21, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X23, X24, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
CMP X21, X22	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 13208 <main+0x1fe8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR X21, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X8, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X22, X21, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X22, X8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.CS 12de4 <main+0x1bc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X9, X8, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
MOVZ X10, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MADD X9, X9, X21, X10	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
SUB W8, W8, W21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X8, X8, #62, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND X9, X9, #0x0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X2, X8, #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X27, X9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 100c0 <@plt_start@+0xa0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR Q22, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
B 12de4 <main+0x1bc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

CALL instructions

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code