OV - attention-native - Loop 40

	Loop Id: 40	Module: attention-native	Source: attention.cpp:55-56	Coverage: 0.06%

0x1310c LDP	Q0, Q1, [X24, #2016]    [2]

0x13110 FSUB	V16.4S, V1.4S, V21.4S

0x13114 FSUB	V0.4S, V0.4S, V21.4S

0x13118 LDP	Q2, Q3, [X24], #64    [2]

0x1311c FSUB	V17.4S, V2.4S, V21.4S

0x13120 FSUB	V18.4S, V3.4S, V21.4S

0x13124 BL	10040

0x13128 ORR	V19.16B, V0.16B, V0.16B

0x1312c ORR	V0.16B, V16.16B, V16.16B

0x13130 BL	10040

0x13134 ORR	V16.16B, V0.16B, V0.16B

0x13138 ORR	V0.16B, V17.16B, V17.16B

0x1313c BL	10040

0x13140 ORR	V17.16B, V0.16B, V0.16B

0x13144 ORR	V0.16B, V18.16B, V18.16B

0x13148 BL	10040

0x1314c FDIV	V1.4S, V19.4S, V20.4S

0x13150 SUBS	X21, X21, #16

0x13154 FDIV	V2.4S, V16.4S, V20.4S

0x13158 STP	Q1, Q2, [X23, #2016]    [1]

0x1315c FDIV	V1.4S, V17.4S, V20.4S

0x13160 FDIV	V0.4S, V0.4S, V20.4S

0x13164 STP	Q1, Q0, [X23], #64    [1]

0x13168 B.NE	1310c

/home/eoseret/llm-attention/attention.cpp: 55 - 56

--------------------------------------------------------------------------------

55:       for (int idx = 0; idx <= row; ++idx)  //vectorised

56:          P[row * N + idx] = expf(S_row[idx] - max_val) / sum;

Coverage (%)	Name	Module
►100.00+	__libc_start_call_main	libc.so.6
○	__libc_start_main	libc.so.6
○	_start	attention-native

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.50 - 4.50
Bottlenecks	P8, P10,
Function	main
Source	attention.cpp:55-56
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	16
CQA cycles	13.99 - 18.02
CQA cycles if no scalar integer	13.99 - 18.02
CQA cycles if FP arith vectorized	13.99 - 18.02
CQA cycles if fully vectorized	13.99 - 18.02
Front-end cycles	3.00
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	0.83
P5 cycles	0.83
P6 cycles	0.67
P7 cycles	0.67
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	1.33
P13 cycles	1.33
P14 cycles	1.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	13.99 - 18.02
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	24.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.29 - 1.78
Nb FLOP add-sub	16.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	3.50 - 4.50
Bottlenecks	P8, P10,
Function	main
Source	attention.cpp:55-56
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	16
CQA cycles	13.99 - 18.02
CQA cycles if no scalar integer	13.99 - 18.02
CQA cycles if FP arith vectorized	13.99 - 18.02
CQA cycles if fully vectorized	13.99 - 18.02
Front-end cycles	3.00
P0 cycles	2.50
P1 cycles	2.50
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	0.83
P5 cycles	0.83
P6 cycles	0.67
P7 cycles	0.67
P8 cycles	4.00
P9 cycles	4.00
P10 cycles	4.00
P11 cycles	4.00
P12 cycles	1.33
P13 cycles	1.33
P14 cycles	1.33
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	13.99 - 18.02
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	24.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.29 - 1.78
Nb FLOP add-sub	16.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	main
Source file and lines	attention.cpp:55-56
Module	attention-native

The loop is defined in /home/eoseret/llm-attention/attention.cpp:55-56.

The related source loop is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 18.02 to 3.00 cycles (6.01x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 4 occurrences►
- /home/eoseret/llm-attention/attention.cpp:56
- /home/eoseret/llm-attention/attention.cpp:56
- /home/eoseret/llm-attention/attention.cpp:56
- /home/eoseret/llm-attention/attention.cpp:56

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

16: addition or subtraction
16: divide

The binary loop does not load or store any data.

General properties

nb instructions	24
nb uops	24
loop length	96
used w registers	0
used x registers	3
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	4
used v registers	10
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.00 cycles
front end	3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	2.00	2.00	0.83	0.83	0.67	0.67	4.00	4.00	4.00	4.00	1.33	1.33	1.33	0.00	0.00
cycles	2.50	2.50	2.00	2.00	0.83	0.83	0.67	0.67	4.00	4.00	4.00	4.00	1.33	1.33	1.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	13.99-18.02
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.00
Dispatch	4.00
DIV/SQRT	13.99-18.02
Data deps.	1.00
Overall L1	13.99-18.02

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

Vector efficiency ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.02 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 1310c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDP Q0, Q1, [X24, #2016]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FSUB V16.4S, V1.4S, V21.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V0.4S, V0.4S, V21.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDP Q2, Q3, [X24], #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FSUB V17.4S, V2.4S, V21.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V18.4S, V3.4S, V21.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
BL 10040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR V19.16B, V0.16B, V0.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ORR V0.16B, V16.16B, V16.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
BL 10040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR V16.16B, V0.16B, V0.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ORR V0.16B, V17.16B, V17.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
BL 10040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR V17.16B, V0.16B, V0.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ORR V0.16B, V18.16B, V18.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
BL 10040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV V1.4S, V19.4S, V20.4S	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-10	3.50-4.50	vect (100.0%)
SUBS X21, X21, #16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
FDIV V2.4S, V16.4S, V20.4S	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-10	3.50-4.50	vect (100.0%)
STP Q1, Q2, [X23, #2016]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	1	vect (100.0%)
FDIV V1.4S, V17.4S, V20.4S	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-10	3.50-4.50	vect (100.0%)
FDIV V0.4S, V0.4S, V20.4S	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-10	3.50-4.50	vect (100.0%)
STP Q1, Q0, [X23], #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
B.NE 1310c <main+0x1eec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	main
Source file and lines	attention.cpp:55-56
Module	attention-native

The loop is defined in /home/eoseret/llm-attention/attention.cpp:55-56.

The related source loop is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 18.02 to 3.00 cycles (6.01x speedup).

CALL instructions

Detected function call instructions.

Details

unknown: 4 occurrences►
- /home/eoseret/llm-attention/attention.cpp:56
- /home/eoseret/llm-attention/attention.cpp:56
- /home/eoseret/llm-attention/attention.cpp:56
- /home/eoseret/llm-attention/attention.cpp:56

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

16: addition or subtraction
16: divide

The binary loop does not load or store any data.

General properties

nb instructions	24
nb uops	24
loop length	96
used w registers	0
used x registers	3
used b registers	0
used h registers	0
used s registers	0
used d registers	0
used q registers	4
used v registers	10
used z registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.00 cycles
front end	3.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	2.00	2.00	0.83	0.83	0.67	0.67	4.00	4.00	4.00	4.00	1.33	1.33	1.33	0.00	0.00
cycles	2.50	2.50	2.00	2.00	0.83	0.83	0.67	0.67	4.00	4.00	4.00	4.00	1.33	1.33	1.33	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	13.99-18.02
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.00
Dispatch	4.00
DIV/SQRT	13.99-18.02
Data deps.	1.00
Overall L1	13.99-18.02

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

Vector efficiency ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	100%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 18.02 cycles.

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 1310c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDP Q0, Q1, [X24, #2016]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FSUB V16.4S, V1.4S, V21.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V0.4S, V0.4S, V21.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDP Q2, Q3, [X24], #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FSUB V17.4S, V2.4S, V21.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V18.4S, V3.4S, V21.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
BL 10040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR V19.16B, V0.16B, V0.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ORR V0.16B, V16.16B, V16.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
BL 10040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR V16.16B, V0.16B, V0.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ORR V0.16B, V17.16B, V17.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
BL 10040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR V17.16B, V0.16B, V0.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ORR V0.16B, V18.16B, V18.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
BL 10040 <@plt_start@+0x20>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FDIV V1.4S, V19.4S, V20.4S	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-10	3.50-4.50	vect (100.0%)
SUBS X21, X21, #16	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
FDIV V2.4S, V16.4S, V20.4S	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-10	3.50-4.50	vect (100.0%)
STP Q1, Q2, [X23, #2016]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	1	vect (100.0%)
FDIV V1.4S, V17.4S, V20.4S	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-10	3.50-4.50	vect (100.0%)
FDIV V0.4S, V0.4S, V20.4S	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-10	3.50-4.50	vect (100.0%)
STP Q1, Q0, [X23], #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
B.NE 1310c <main+0x1eec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Expensive FP math instructions/calls

CALL instructions

Details

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code